from m5.params import *
from m5.proxy import *
-from System import System
+
+from m5.objects.System import System
class AlphaSystem(System):
type = 'AlphaSystem'
from m5.SimObject import SimObject
from m5.params import *
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
class AlphaTLB(BaseTLB):
type = 'AlphaTLB'
from m5.proxy import *
from m5.SimObject import SimObject
-from ArmPMU import ArmPMU
-from ISACommon import VecRegRenameMode
+from m5.objects.ArmPMU import ArmPMU
+from m5.objects.ISACommon import VecRegRenameMode
# Enum for DecoderFlavour
class DecoderFlavour(Enum): vals = ['Generic']
from m5.SimObject import SimObject
from m5.params import *
-from CPUTracers import NativeTrace
+from m5.objects.CPUTracers import NativeTrace
class ArmNativeTrace(NativeTrace):
type = 'ArmNativeTrace'
from m5.params import *
from m5.params import isNullPointer
from m5.proxy import *
-from Gic import ArmInterruptPin
+from m5.objects.Gic import ArmInterruptPin
class ProbeEvent(object):
def __init__(self, pmu, _eventId, obj, *listOfNames):
from m5.params import *
from m5.SimObject import *
-from Serial import SerialDevice
-from Terminal import Terminal
+from m5.objects.Serial import SerialDevice
+from m5.objects.Terminal import Terminal
class ArmSemihosting(SimObject):
type = 'ArmSemihosting'
from m5.SimObject import *
from m5.util.fdthelper import *
-from System import System
-from ArmSemihosting import ArmSemihosting
+from m5.objects.System import System
+from m5.objects.ArmSemihosting import ArmSemihosting
class ArmMachineType(Enum):
map = {
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
-from MemObject import MemObject
-from BaseTLB import BaseTLB
+from m5.objects.MemObject import MemObject
+from m5.objects.BaseTLB import BaseTLB
# Basic stage 1 translation objects
class ArmTableWalker(MemObject):
from m5.SimObject import SimObject
from m5.params import *
-from InstTracer import InstTracer
+from m5.objects.InstTracer import InstTracer
class TarmacParser(InstTracer):
type = 'TarmacParser'
from m5.params import *
from m5.proxy import *
-from System import System
+from m5.objects.System import System
class MipsSystem(System):
type = 'MipsSystem'
from m5.SimObject import SimObject
from m5.params import *
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
class MipsTLB(BaseTLB):
type = 'MipsTLB'
from m5.SimObject import SimObject
from m5.params import *
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
class PowerTLB(BaseTLB):
type = 'PowerTLB'
# Robert Scheffel
from m5.params import *
-from System import System
+from m5.objects.System import System
class RiscvSystem(System):
type = 'RiscvSystem'
from m5.SimObject import SimObject
from m5.params import *
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
class RiscvTLB(BaseTLB):
type = 'RiscvTLB'
from m5.SimObject import SimObject
from m5.params import *
-from CPUTracers import NativeTrace
+
+from m5.objects.CPUTracers import NativeTrace
class SparcNativeTrace(NativeTrace):
type = 'SparcNativeTrace'
from m5.params import *
-from SimpleMemory import SimpleMemory
-from System import System
+from m5.objects.SimpleMemory import SimpleMemory
+from m5.objects.System import System
class SparcSystem(System):
type = 'SparcSystem'
from m5.SimObject import SimObject
from m5.params import *
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
class SparcTLB(BaseTLB):
type = 'SparcTLB'
from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
-from Device import BasicPioDevice
+
+from m5.objects.Device import BasicPioDevice
class X86LocalApic(BasicPioDevice):
type = 'X86LocalApic'
from m5.SimObject import SimObject
from m5.params import *
-from CPUTracers import NativeTrace
+
+from m5.objects.CPUTracers import NativeTrace
class X86NativeTrace(NativeTrace):
type = 'X86NativeTrace'
# Authors: Gabe Black
from m5.params import *
-from E820 import X86E820Table, X86E820Entry
-from SMBios import X86SMBiosSMBiosTable
-from IntelMP import X86IntelMPFloatingPointer, X86IntelMPConfigTable
-from ACPI import X86ACPIRSDP
-from System import System
+
+from m5.objects.E820 import X86E820Table, X86E820Entry
+from m5.objects.SMBios import X86SMBiosSMBiosTable
+from m5.objects.IntelMP import X86IntelMPFloatingPointer, X86IntelMPConfigTable
+from m5.objects.ACPI import X86ACPIRSDP
+from m5.objects.System import System
class X86System(System):
type = 'X86System'
from m5.params import *
from m5.proxy import *
-from BaseTLB import BaseTLB
-from MemObject import MemObject
+from m5.objects.BaseTLB import BaseTLB
+from m5.objects.MemObject import MemObject
class X86PagetableWalker(MemObject):
type = 'X86PagetableWalker'
from m5.SimObject import SimObject
from m5.params import *
-from Graphics import *
+from m5.objects.Graphics import *
class VncInput(SimObject):
from m5.proxy import *
from m5.util.fdthelper import *
-from XBar import L2XBar
-from InstTracer import InstTracer
-from CPUTracers import ExeTracer
-from MemObject import MemObject
-from SubSystem import SubSystem
-from ClockDomain import *
-from Platform import Platform
+from m5.objects.XBar import L2XBar
+from m5.objects.InstTracer import InstTracer
+from m5.objects.CPUTracers import ExeTracer
+from m5.objects.MemObject import MemObject
+from m5.objects.SubSystem import SubSystem
+from m5.objects.ClockDomain import *
+from m5.objects.Platform import Platform
default_tracer = ExeTracer()
if buildEnv['TARGET_ISA'] == 'alpha':
- from AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
- from AlphaInterrupts import AlphaInterrupts
- from AlphaISA import AlphaISA
+ from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
+ from m5.objects.AlphaInterrupts import AlphaInterrupts
+ from m5.objects.AlphaISA import AlphaISA
default_isa_class = AlphaISA
elif buildEnv['TARGET_ISA'] == 'sparc':
- from SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
- from SparcInterrupts import SparcInterrupts
- from SparcISA import SparcISA
+ from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
+ from m5.objects.SparcInterrupts import SparcInterrupts
+ from m5.objects.SparcISA import SparcISA
default_isa_class = SparcISA
elif buildEnv['TARGET_ISA'] == 'x86':
- from X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
- from X86LocalApic import X86LocalApic
- from X86ISA import X86ISA
+ from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
+ from m5.objects.X86LocalApic import X86LocalApic
+ from m5.objects.X86ISA import X86ISA
default_isa_class = X86ISA
elif buildEnv['TARGET_ISA'] == 'mips':
- from MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
- from MipsInterrupts import MipsInterrupts
- from MipsISA import MipsISA
+ from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
+ from m5.objects.MipsInterrupts import MipsInterrupts
+ from m5.objects.MipsISA import MipsISA
default_isa_class = MipsISA
elif buildEnv['TARGET_ISA'] == 'arm':
- from ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
- from ArmTLB import ArmStage2IMMU, ArmStage2DMMU
- from ArmInterrupts import ArmInterrupts
- from ArmISA import ArmISA
+ from m5.objects.ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
+ from m5.objects.ArmTLB import ArmStage2IMMU, ArmStage2DMMU
+ from m5.objects.ArmInterrupts import ArmInterrupts
+ from m5.objects.ArmISA import ArmISA
default_isa_class = ArmISA
elif buildEnv['TARGET_ISA'] == 'power':
- from PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
- from PowerInterrupts import PowerInterrupts
- from PowerISA import PowerISA
+ from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
+ from m5.objects.PowerInterrupts import PowerInterrupts
+ from m5.objects.PowerISA import PowerISA
default_isa_class = PowerISA
elif buildEnv['TARGET_ISA'] == 'riscv':
- from RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
- from RiscvInterrupts import RiscvInterrupts
- from RiscvISA import RiscvISA
+ from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
+ from m5.objects.RiscvInterrupts import RiscvInterrupts
+ from m5.objects.RiscvISA import RiscvISA
default_isa_class = RiscvISA
class BaseCPU(MemObject):
from m5.SimObject import SimObject
from m5.params import *
-from InstTracer import InstTracer
+from m5.objects.InstTracer import InstTracer
class ExeTracer(InstTracer):
type = 'ExeTracer'
# Authors: Nathan Binkert
from m5.params import *
-from BaseCPU import BaseCPU
+
+from m5.objects.BaseCPU import BaseCPU
class CheckerCPU(BaseCPU):
type = 'CheckerCPU'
# Authors: Geoffrey Blake
from m5.params import *
-from CheckerCPU import CheckerCPU
+from m5.objects.CheckerCPU import CheckerCPU
class DummyChecker(CheckerCPU):
type = 'DummyChecker'
from m5.SimObject import SimObject
from m5.params import *
-from InstTracer import InstTracer
+
+from m5.objects.InstTracer import InstTracer
class InstPBTrace(InstTracer):
type = 'InstPBTrace'
from m5.params import *
from m5.proxy import *
-from BaseCPU import BaseCPU
-from KvmVM import KvmVM
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.KvmVM import KvmVM
class BaseKvmCPU(BaseCPU):
type = 'BaseKvmCPU'
from m5.params import *
from m5.SimObject import *
-from BaseKvmCPU import BaseKvmCPU
+
+from m5.objects.BaseKvmCPU import BaseKvmCPU
class X86KvmCPU(BaseKvmCPU):
type = 'X86KvmCPU'
from m5.params import *
from m5.proxy import *
from m5.SimObject import SimObject
-from BaseCPU import BaseCPU
-from DummyChecker import DummyChecker
-from BranchPredictor import *
-from TimingExpr import TimingExpr
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.DummyChecker import DummyChecker
+from m5.objects.BranchPredictor import *
+from m5.objects.TimingExpr import TimingExpr
-from FuncUnit import OpClass
+from m5.objects.FuncUnit import OpClass
class MinorOpClass(SimObject):
"""Boxing of OpClass to get around build problems and provide a hook for
from m5.SimObject import SimObject
from m5.params import *
-from FuncUnit import *
-from FuncUnitConfig import *
+from m5.objects.FuncUnit import *
+from m5.objects.FuncUnitConfig import *
class FUPool(SimObject):
type = 'FUPool'
from m5.SimObject import SimObject
from m5.defines import buildEnv
from m5.params import *
-from FuncUnit import *
+
+from m5.objects.FuncUnit import *
class IntALU(FUDesc):
opList = [ OpDesc(opClass='IntAlu') ]
from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
-from BaseCPU import BaseCPU
-from FUPool import *
-from O3Checker import O3Checker
-from BranchPredictor import *
+
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.FUPool import *
+from m5.objects.O3Checker import O3Checker
+from m5.objects.BranchPredictor import *
class FetchPolicy(ScopedEnum):
vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ]
def addCheckerCpu(self):
if buildEnv['TARGET_ISA'] in ['arm']:
- from ArmTLB import ArmTLB
+ from m5.objects.ArmTLB import ArmTLB
self.checker = O3Checker(workload=self.workload,
exitOnError=False,
# Authors: Nathan Binkert
from m5.params import *
-from CheckerCPU import CheckerCPU
+from m5.objects.CheckerCPU import CheckerCPU
class O3Checker(CheckerCPU):
type = 'O3Checker'
# Andreas Hansson
# Thomas Grass
-from Probe import *
+from m5.objects.Probe import *
class ElasticTrace(ProbeListenerObject):
type = 'ElasticTrace'
#
# Authors: Matt Horsnell
-from Probe import *
+from m5.objects.Probe import *
class SimpleTrace(ProbeListenerObject):
type = 'SimpleTrace'
# Authors: Nathan Binkert
from m5.params import *
-from BaseSimpleCPU import BaseSimpleCPU
-from SimPoint import SimPoint
+from m5.objects.BaseSimpleCPU import BaseSimpleCPU
+from m5.objects.SimPoint import SimPoint
class AtomicSimpleCPU(BaseSimpleCPU):
"""Simple CPU model executing a configurable number of
from m5.defines import buildEnv
from m5.params import *
-from BaseCPU import BaseCPU
-from DummyChecker import DummyChecker
-from BranchPredictor import *
+
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.DummyChecker import DummyChecker
+from m5.objects.BranchPredictor import *
class BaseSimpleCPU(BaseCPU):
type = 'BaseSimpleCPU'
def addCheckerCpu(self):
if buildEnv['TARGET_ISA'] in ['arm']:
- from ArmTLB import ArmTLB
+ from m5.objects.ArmTLB import ArmTLB
self.checker = DummyChecker(workload = self.workload)
self.checker.itb = ArmTLB(size = self.itb.size)
# Authors: Andreas Sandberg
from m5.params import *
-from AtomicSimpleCPU import AtomicSimpleCPU
+from m5.objects.AtomicSimpleCPU import AtomicSimpleCPU
class NonCachingSimpleCPU(AtomicSimpleCPU):
"""Simple CPU model based on the atomic CPU. Unlike the atomic CPU,
# Authors: Nathan Binkert
from m5.params import *
-from BaseSimpleCPU import BaseSimpleCPU
+
+from m5.objects.BaseSimpleCPU import BaseSimpleCPU
class TimingSimpleCPU(BaseSimpleCPU):
type = 'TimingSimpleCPU'
# Authors: Curtis Dunham
from m5.params import *
-from Probe import ProbeListenerObject
+from m5.objects.Probe import ProbeListenerObject
class SimPoint(ProbeListenerObject):
"""Probe for collecting SimPoint Basic Block Vectors (BBVs)."""
# Authors: Brad Beckmann
from m5.SimObject import SimObject
-from MemObject import MemObject
from m5.params import *
from m5.proxy import *
+from m5.objects.MemObject import MemObject
+
class DirectedGenerator(SimObject):
type = 'DirectedGenerator'
abstract = True
#
# Authors: Tushar Krishna
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
from m5.params import *
from m5.proxy import *
#
# Authors: Nathan Binkert
# Andreas Hansson
-
-from MemObject import MemObject
from m5.params import *
from m5.proxy import *
+from m5.objects.MemObject import MemObject
+
class MemTest(MemObject):
type = 'MemTest'
cxx_header = "cpu/testers/memtest/memtest.hh"
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
-
-from MemObject import MemObject
from m5.params import *
from m5.proxy import *
+from m5.objects.MemObject import MemObject
+
class RubyTester(MemObject):
type = 'RubyTester'
cxx_header = "cpu/testers/rubytest/RubyTester.hh"
from m5.params import *
from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
# Types of Stream Generators.
# Those are orthogonal to the other generators in the TrafficGen
from m5.defines import buildEnv
from m5.SimObject import *
-from BaseTrafficGen import *
+
+from m5.objects.BaseTrafficGen import *
class PyTrafficGen(BaseTrafficGen):
type = 'PyTrafficGen'
# Sascha Bischoff
from m5.params import *
-from BaseTrafficGen import *
+from m5.objects.BaseTrafficGen import *
# The behaviour of this traffic generator is specified in a
# configuration file, and this file describes a state transition graph
# Thomas Grass
from m5.params import *
-from BaseCPU import BaseCPU
+from m5.objects.BaseCPU import BaseCPU
class TraceCPU(BaseCPU):
"""Trace CPU model which replays traces generated in a prior simulation
# Authors: Nathan Binkert
from m5.params import *
-from Device import BasicPioDevice
+from m5.objects.Device import BasicPioDevice
class BadDevice(BasicPioDevice):
type = 'BadDevice'
from m5.params import *
from m5.proxy import *
from m5.util.fdthelper import *
-from MemObject import MemObject
+
+from m5.objects.MemObject import MemObject
class PioDevice(MemObject):
type = 'PioDevice'
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
+
class Platform(SimObject):
type = 'Platform'
abstract = True
from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
-from Device import BasicPioDevice
+
+from m5.objects.Device import BasicPioDevice
class AlphaBackdoor(BasicPioDevice):
type = 'AlphaBackdoor'
from m5.params import *
from m5.proxy import *
-from BadDevice import BadDevice
-from AlphaBackdoor import AlphaBackdoor
-from Device import BasicPioDevice, IsaFake, BadAddr
-from PciHost import GenericPciHost
-from Platform import Platform
-from Uart import Uart8250
+from m5.objects.BadDevice import BadDevice
+from m5.objects.AlphaBackdoor import AlphaBackdoor
+from m5.objects.Device import BasicPioDevice, IsaFake, BadAddr
+from m5.objects.PciHost import GenericPciHost
+from m5.objects.Platform import Platform
+from m5.objects.Uart import Uart8250
class TsunamiCChip(BasicPioDevice):
type = 'TsunamiCChip'
from m5.params import *
from m5.SimObject import SimObject
-from Device import BasicPioDevice
+from m5.objects.Device import BasicPioDevice
from m5.proxy import *
from m5.util.fdthelper import *
from m5.params import *
from m5.proxy import *
-from AbstractNVM import *
+
+from m5.objects.AbstractNVM import *
#Distribution of the data.
#sequential: sequential (address n+1 is likely to be on the same plane as n)
from m5.util.fdthelper import *
from m5.SimObject import SimObject
-from Device import PioDevice
-from Platform import Platform
+from m5.objects.Device import PioDevice
+from m5.objects.Platform import Platform
class BaseGic(PioDevice):
type = 'BaseGic'
# Authors: Andreas Sandberg
from m5.params import *
-from Device import BasicPioDevice
-from Gic import *
+
+from m5.objects.Device import BasicPioDevice
+from m5.objects.Gic import *
class NoMaliGpuType(Enum): vals = [
'T60x',
from m5.params import *
from m5.proxy import *
from m5.util.fdthelper import *
-from ClockDomain import ClockDomain
-from VoltageDomain import VoltageDomain
-from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
-from PciHost import *
-from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
-from Ide import *
-from Platform import Platform
-from Terminal import Terminal
-from Uart import Uart
-from SimpleMemory import SimpleMemory
-from Gic import *
-from EnergyCtrl import EnergyCtrl
-from ClockedObject import ClockedObject
-from ClockDomain import SrcClockDomain
-from SubSystem import SubSystem
-from Graphics import ImageFormat
-from ClockedObject import ClockedObject
-from PS2 import *
-from VirtIOMMIO import MmioVirtIO
+from m5.objects.ClockDomain import ClockDomain
+from m5.objects.VoltageDomain import VoltageDomain
+from m5.objects.Device import \
+ BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
+from m5.objects.PciHost import *
+from m5.objects.Ethernet import NSGigE, IGbE_igb, IGbE_e1000
+from m5.objects.Ide import *
+from m5.objects.Platform import Platform
+from m5.objects.Terminal import Terminal
+from m5.objects.Uart import Uart
+from m5.objects.SimpleMemory import SimpleMemory
+from m5.objects.Gic import *
+from m5.objects.EnergyCtrl import EnergyCtrl
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.ClockDomain import SrcClockDomain
+from m5.objects.SubSystem import SubSystem
+from m5.objects.Graphics import ImageFormat
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.PS2 import *
+from m5.objects.VirtIOMMIO import MmioVirtIO
# Platforms with KVM support should generally use in-kernel GIC
# emulation. Use a GIC model that automatically switches between
# gem5's GIC model and KVM's GIC model if KVM is available.
try:
- from KvmGic import MuxingKvmGic
+ from m5.objects.KvmGic import MuxingKvmGic
kvm_gicv2_class = MuxingKvmGic
except ImportError:
# KVM support wasn't compiled into gem5. Fallback to a
import sys
from m5.params import *
from m5.proxy import *
-from Device import DmaDevice
-from AbstractNVM import *
+from m5.objects.Device import DmaDevice
+from m5.objects.AbstractNVM import *
class UFSHostDevice(DmaDevice):
type = 'UFSHostDevice'
from m5.params import *
from m5.proxy import *
-from Device import BasicPioDevice
-from Gic import ArmInterruptPin
-from VirtIO import VirtIODeviceBase, VirtIODummyDevice
+from m5.objects.Device import BasicPioDevice
+from m5.objects.Gic import ArmInterruptPin
+from m5.objects.VirtIO import VirtIODeviceBase, VirtIODummyDevice
class MmioVirtIO(BasicPioDevice):
type = 'MmioVirtIO'
from m5.SimObject import SimObject
from m5.params import *
-from Device import BasicPioDevice
+from m5.objects.Device import BasicPioDevice
class I2CDevice(SimObject):
type = 'I2CDevice'
from m5.params import *
from m5.proxy import *
-from BadDevice import BadDevice
-from Device import BasicPioDevice
-from Platform import Platform
-from Uart import Uart8250
+from m5.objects.BadDevice import BadDevice
+from m5.objects.Device import BasicPioDevice
+from m5.objects.Platform import Platform
+from m5.objects.Uart import Uart8250
class MaltaCChip(BasicPioDevice):
type = 'MaltaCChip'
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
-from PciDevice import PciDevice
+from m5.objects.PciDevice import PciDevice
class EtherObject(SimObject):
type = 'EtherObject'
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
-from PciDevice import PciDevice
+
+from m5.objects.PciDevice import PciDevice
class CopyEngine(PciDevice):
type = 'CopyEngine'
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
-from Device import DmaDevice
-from PciHost import PciHost
+from m5.objects.Device import DmaDevice
+from m5.objects.PciHost import PciHost
class PciDevice(DmaDevice):
type = 'PciDevice'
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
-from Device import PioDevice
-from Platform import Platform
+from m5.objects.Device import PioDevice
+from m5.objects.Platform import Platform
class PciHost(PioDevice):
type = 'PciHost'
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
-from Serial import SerialDevice
+
+from m5.objects.Serial import SerialDevice
class Terminal(SerialDevice):
type = 'Terminal'
from m5.params import *
from m5.proxy import *
-from Device import BasicPioDevice
-from Serial import SerialDevice
+
+from m5.objects.Device import BasicPioDevice
+from m5.objects.Serial import SerialDevice
class Uart(BasicPioDevice):
type = 'Uart'
from m5.params import *
from m5.proxy import *
-from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
-from Platform import Platform
-from Terminal import Terminal
-from Uart import Uart8250
+
+from m5.objects.Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
+from m5.objects.Platform import Platform
+from m5.objects.Terminal import Terminal
+from m5.objects.Uart import Uart8250
class MmDisk(BasicPioDevice):
from m5.SimObject import SimObject
from m5.params import *
-from PciDevice import PciDevice
+from m5.objects.PciDevice import PciDevice
class IdeID(Enum): vals = ['master', 'slave']
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
-from Device import PioDevice
-from PciDevice import PciDevice
+from m5.objects.Device import PioDevice
+from m5.objects.PciDevice import PciDevice
class VirtIODeviceBase(SimObject):
from m5.params import *
from m5.proxy import *
-from VirtIO import VirtIODeviceBase
+from m5.objects.VirtIO import VirtIODeviceBase
class VirtIO9PBase(VirtIODeviceBase):
type = 'VirtIO9PBase'
from m5.params import *
from m5.proxy import *
-from VirtIO import VirtIODeviceBase
+from m5.objects.VirtIO import VirtIODeviceBase
class VirtIOBlock(VirtIODeviceBase):
type = 'VirtIOBlock'
from m5.params import *
from m5.proxy import *
-from VirtIO import VirtIODeviceBase
-from Serial import SerialDevice
+from m5.objects.VirtIO import VirtIODeviceBase
+from m5.objects.Serial import SerialDevice
class VirtIOConsole(VirtIODeviceBase):
type = 'VirtIOConsole'
from m5.params import *
from m5.proxy import *
-from Device import BasicPioDevice
-from X86IntPin import X86IntSourcePin
+from m5.objects.Device import BasicPioDevice
+from m5.objects.X86IntPin import X86IntSourcePin
class Cmos(BasicPioDevice):
type = 'Cmos'
from m5.params import *
from m5.proxy import *
-from Device import BasicPioDevice
-from X86IntPin import X86IntSourcePin
-from PS2 import *
+from m5.objects.Device import BasicPioDevice
+from m5.objects.X86IntPin import X86IntSourcePin
+from m5.objects.PS2 import *
class I8042(BasicPioDevice):
type = 'I8042'
from m5.params import *
from m5.proxy import *
-from Device import BasicPioDevice
-from X86IntPin import X86IntSinkPin
+from m5.objects.Device import BasicPioDevice
+from m5.objects.X86IntPin import X86IntSinkPin
class I82094AA(BasicPioDevice):
type = 'I82094AA'
from m5.params import *
from m5.proxy import *
-from Device import BasicPioDevice
+from m5.objects.Device import BasicPioDevice
class I8237(BasicPioDevice):
type = 'I8237'
from m5.params import *
from m5.proxy import *
-from Device import BasicPioDevice
-from X86IntPin import X86IntSourcePin
+from m5.objects.Device import BasicPioDevice
+from m5.objects.X86IntPin import X86IntSourcePin
class I8254(BasicPioDevice):
type = 'I8254'
from m5.params import *
from m5.proxy import *
-from Device import BasicPioDevice
-from X86IntPin import X86IntSourcePin, X86IntSinkPin
+from m5.objects.Device import BasicPioDevice
+from m5.objects.X86IntPin import X86IntSourcePin, X86IntSinkPin
class X86I8259CascadeMode(Enum):
map = {'I8259Master' : 0,
from m5.params import *
from m5.proxy import *
-from Device import IsaFake
-from Platform import Platform
-from SouthBridge import SouthBridge
-from Terminal import Terminal
-from Uart import Uart8250
-from PciHost import GenericPciHost
+from m5.objects.Device import IsaFake
+from m5.objects.Platform import Platform
+from m5.objects.SouthBridge import SouthBridge
+from m5.objects.Terminal import Terminal
+from m5.objects.Uart import Uart8250
+from m5.objects.PciHost import GenericPciHost
def x86IOAddress(port):
IO_address_space_base = 0x8000000000000000
from m5.params import *
from m5.proxy import *
-from Device import BasicPioDevice
+from m5.objects.Device import BasicPioDevice
class PcSpeaker(BasicPioDevice):
type = 'PcSpeaker'
from m5.params import *
from m5.proxy import *
-from Cmos import Cmos
-from I8042 import I8042
-from I82094AA import I82094AA
-from I8237 import I8237
-from I8254 import I8254
-from I8259 import I8259
-from Ide import IdeController
-from PcSpeaker import PcSpeaker
-from X86IntPin import X86IntLine
+from m5.objects.Cmos import Cmos
+from m5.objects.I8042 import I8042
+from m5.objects.I82094AA import I82094AA
+from m5.objects.I8237 import I8237
+from m5.objects.I8254 import I8254
+from m5.objects.I8259 import I8259
+from m5.objects.Ide import IdeController
+from m5.objects.PcSpeaker import PcSpeaker
+from m5.objects.X86IntPin import X86IntLine
from m5.SimObject import SimObject
def x86IOAddress(port):
# Author: Steve Reinhardt
#
-from ClockedObject import ClockedObject
-from Device import DmaDevice
from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
from m5.SimObject import SimObject
-from MemObject import MemObject
-from Process import EmulatedDriver
-from Bridge import Bridge
-from LdsState import LdsState
+
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.Device import DmaDevice
+from m5.objects.MemObject import MemObject
+from m5.objects.Process import EmulatedDriver
+from m5.objects.Bridge import Bridge
+from m5.objects.LdsState import LdsState
class PrefetchType(Enum): vals = [
'PF_CU',
from m5.params import *
from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
class LdsState(MemObject):
type = 'LdsState'
from m5.params import *
from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
class SimpleCache(MemObject):
type = 'SimpleCache'
# Authors: Jason Lowe-Power
from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
class SimpleMemobj(MemObject):
type = 'SimpleMemobj'
# Andreas Hansson
from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
class AbstractMemory(MemObject):
type = 'AbstractMemory'
# Authors: Andreas Hansson
from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
# An address mapper changes the packet addresses in going from the
# slave port side of the mapper to the master port side. When the
# Andreas Hansson
from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
class Bridge(MemObject):
type = 'Bridge'
from m5.params import *
from m5.proxy import *
-from MemObject import MemObject
-from System import System
+from m5.objects.MemObject import MemObject
+from m5.objects.System import System
# The communication monitor will most typically be used in combination
# with periodic dumping and resetting of stats using schedStatEvent
from m5.params import *
from m5.proxy import *
-from AbstractMemory import *
-from QoSMemCtrl import *
+from m5.objects.AbstractMemory import *
+from m5.objects.QoSMemCtrl import *
# Enum for memory scheduling algorithms, currently First-Come
# First-Served and a First-Row Hit then First-Come First-Served
from m5.params import *
from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
class ExternalMaster(MemObject):
type = 'ExternalMaster'
# Authors: Andrew Bardsley
from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
class ExternalSlave(MemObject):
type = 'ExternalSlave'
# Authors: Erfan Azarkhish
from m5.params import *
-from XBar import *
+from m5.objects.XBar import *
# References:
# [1] http://www.open-silicon.com/open-silicon-ips/hmc/
#
# Authors: Marco Elver
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
# Authors: Andreas Sandberg
from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
class MemDelay(MemObject):
type = 'MemDelay'
#
# Authors: Ron Dreslinski
-from ClockedObject import ClockedObject
+from m5.objects.ClockedObject import ClockedObject
class MemObject(ClockedObject):
type = 'MemObject'
# Erfan Azarkhish
from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
# SerialLink is a simple variation of the Bridge class, with the ability to
# account for the latency of packet serialization.
# Andreas Hansson
from m5.params import *
-from AbstractMemory import *
+from m5.objects.AbstractMemory import *
class SimpleMemory(AbstractMemory):
type = 'SimpleMemory'
# Authors: Nathan Binkert
# Andreas Hansson
-from MemObject import MemObject
-from System import System
+from m5.objects.System import System
from m5.params import *
from m5.proxy import *
from m5.SimObject import SimObject
+from m5.objects.MemObject import MemObject
+
class BaseXBar(MemObject):
type = 'BaseXBar'
abstract = True
from m5.params import *
from m5.proxy import *
from m5.SimObject import SimObject
-from MemObject import MemObject
-from Prefetcher import BasePrefetcher
-from ReplacementPolicies import *
-from Tags import *
+
+from m5.objects.MemObject import MemObject
+from m5.objects.Prefetcher import BasePrefetcher
+from m5.objects.ReplacementPolicies import *
+from m5.objects.Tags import *
# Enum for cache clusivity, currently mostly inclusive or mostly
# Authors: Ron Dreslinski
# Mitch Hayenga
-from ClockedObject import ClockedObject
-from IndexingPolicies import *
from m5.SimObject import *
from m5.params import *
from m5.proxy import *
-from ReplacementPolicies import *
+
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.IndexingPolicies import *
+from m5.objects.ReplacementPolicies import *
class HWPProbeEvent(object):
def __init__(self, prefetcher, obj, *listOfNames):
from m5.params import *
from m5.proxy import *
-from ClockedObject import ClockedObject
-from IndexingPolicies import *
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.IndexingPolicies import *
class BaseTags(ClockedObject):
type = 'BaseTags'
from m5.params import *
from m5.proxy import *
-from BaseMemProbe import BaseMemProbe
+
+from m5.objects.BaseMemProbe import BaseMemProbe
class MemFootprintProbe(BaseMemProbe):
type = "MemFootprintProbe"
from m5.params import *
from m5.proxy import *
-from BaseMemProbe import BaseMemProbe
+from m5.objects.BaseMemProbe import BaseMemProbe
class MemTraceProbe(BaseMemProbe):
type = 'MemTraceProbe'
from m5.params import *
from m5.proxy import *
-from BaseMemProbe import BaseMemProbe
+from m5.objects.BaseMemProbe import BaseMemProbe
class StackDistProbe(BaseMemProbe):
type = 'StackDistProbe'
# Authors: Matteo Andreozzi
from m5.params import *
-from AbstractMemory import AbstractMemory
-from QoSTurnaround import *
+from m5.objects.AbstractMemory import AbstractMemory
+from m5.objects.QoSTurnaround import *
# QoS Queue Selection policy used to select packets among same-QoS queues
class QoSQPolicy(Enum): vals = ["fifo", "lifo", "lrg"]
# Author: Matteo Andreozzi
from m5.params import *
-from QoSMemCtrl import *
+from m5.objects.QoSMemCtrl import *
class QoSMemSinkCtrl(QoSMemCtrl):
type = 'QoSMemSinkCtrl'
# Brad Beckmann
from m5.params import *
-from ClockedObject import ClockedObject
+
+from m5.objects.ClockedObject import ClockedObject
class BasicRouter(ClockedObject):
type = 'BasicRouter'
# Brad Beckmann
from m5.params import *
-from ClockedObject import ClockedObject
-from BasicLink import BasicLink
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.BasicLink import BasicLink
class RubyNetwork(ClockedObject):
type = 'RubyNetwork'
from m5.params import *
from m5.proxy import *
-from ClockedObject import ClockedObject
-from BasicLink import BasicIntLink, BasicExtLink
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.BasicLink import BasicIntLink, BasicExtLink
class NetworkLink(ClockedObject):
type = 'NetworkLink'
from m5.params import *
from m5.proxy import *
-from Network import RubyNetwork
-from BasicRouter import BasicRouter
-from ClockedObject import ClockedObject
+from m5.objects.Network import RubyNetwork
+from m5.objects.BasicRouter import BasicRouter
+from m5.objects.ClockedObject import ClockedObject
class GarnetNetwork(RubyNetwork):
type = 'GarnetNetwork'
from m5.params import *
from m5.proxy import *
from m5.SimObject import SimObject
-from BasicLink import BasicIntLink, BasicExtLink
+from m5.objects.BasicLink import BasicIntLink, BasicExtLink
class SimpleExtLink(BasicExtLink):
type = 'SimpleExtLink'
from m5.params import *
from m5.proxy import *
-from Network import RubyNetwork
-from BasicRouter import BasicRouter
-from MessageBuffer import MessageBuffer
+
+from m5.objects.Network import RubyNetwork
+from m5.objects.BasicRouter import BasicRouter
+from m5.objects.MessageBuffer import MessageBuffer
class SimpleNetwork(RubyNetwork):
type = 'SimpleNetwork'
from m5.params import *
from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
class RubyController(MemObject):
type = 'RubyController'
from m5.params import *
from m5.SimObject import SimObject
-from ReplacementPolicy import ReplacementPolicy
+from m5.objects.ReplacementPolicy import ReplacementPolicy
class LRUReplacementPolicy(ReplacementPolicy):
type = 'LRUReplacementPolicy'
#
# Author: Derek Hower
-from ReplacementPolicy import ReplacementPolicy
+from m5.objects.ReplacementPolicy import ReplacementPolicy
class PseudoLRUReplacementPolicy(ReplacementPolicy):
type = 'PseudoLRUReplacementPolicy'
from m5.params import *
from m5.proxy import *
-from PseudoLRUReplacementPolicy import PseudoLRUReplacementPolicy
+from m5.objects.PseudoLRUReplacementPolicy import PseudoLRUReplacementPolicy
from m5.SimObject import SimObject
class RubyCache(SimObject):
# Authors: Nilay Vaish
from m5.SimObject import SimObject
-from System import System
from m5.params import *
from m5.proxy import *
+from m5.objects.System import System
+
class Prefetcher(SimObject):
type = 'Prefetcher'
cxx_class = 'Prefetcher'
from m5.params import *
from m5.proxy import *
-from Sequencer import *
+
+from m5.objects.Sequencer import *
class RubyGPUCoalescer(RubyPort):
type = 'RubyGPUCoalescer'
# Brad Beckmann
from m5.params import *
-from ClockedObject import ClockedObject
-from SimpleMemory import *
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.SimpleMemory import *
class RubySystem(ClockedObject):
type = 'RubySystem'
from m5.params import *
from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
class RubyPort(MemObject):
type = 'RubyPort'
from m5.params import *
from m5.proxy import *
-from GPUCoalescer import *
+from m5.objects.GPUCoalescer import *
class VIPERCoalescer(RubyGPUCoalescer):
type = 'VIPERCoalescer'
from m5.params import *
from m5.proxy import *
-from MemObject import MemObject
-from ReplacementPolicy import ReplacementPolicy
+from m5.objects.MemObject import MemObject
+from m5.objects.ReplacementPolicy import ReplacementPolicy
class WeightedLRUReplacementPolicy(ReplacementPolicy):
type = "WeightedLRUReplacementPolicy"
code('''
from m5.params import *
from m5.SimObject import SimObject
-from Controller import RubyController
+from m5.objects.Controller import RubyController
class $py_ident(RubyController):
type = '$py_ident'
from m5.params import *
from m5.proxy import *
-from DVFSHandler import *
-from SimpleMemory import *
+from m5.objects.DVFSHandler import *
+from m5.objects.SimpleMemory import *
class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
'atomic_noncaching']
#
# Authors: Andrew Bardsley
-from ClockedObject import ClockedObject
+from m5.objects.ClockedObject import ClockedObject
class TickedObject(ClockedObject):
type = 'TickedObject'
from m5.SimObject import SimObject
from m5.params import *
-from PowerModelState import PowerModelState
+from m5.objects.PowerModelState import PowerModelState
# Represents a power model for a simobj
class MathExprPowerModel(PowerModelState):
# Authors: David Guillen Fandos
from m5.SimObject import *
-from ClockedObject import ClockedObject
+from m5.objects.ClockedObject import ClockedObject
from m5.params import *
from m5.objects import ThermalDomain
projects / gem5.git / commitdiff