radv: Merge the flush bits of CMASK & DCC clear.

Probably won't be much different in practice, but still wrong.

Fixes Coverity issue 1435002.

Not CC'ing to stable since this is only hit if you enable MSAA
DCC via RADV_DEBUG.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 21c950c7823f0635e4a60244e7e6f784a384e0d3..14af2560821492c69f5e866ea964ff8356dc00ca 100644 (file)
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1089,7 +1089,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
                if (!can_avoid_fast_clear_elim)
                        need_decompress_pass = true;
 
-               flush_bits = radv_clear_dcc(cmd_buffer, iview->image, reset_value);
+               flush_bits |= radv_clear_dcc(cmd_buffer, iview->image, reset_value);
 
                radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
                                                  need_decompress_pass);