bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Wed, 15 Feb 2012 17:23:31 +0000 (18:23 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Wed, 15 Feb 2012 17:23:31 +0000 (18:23 +0100)
examples/simple_gpio.py
migen/bank/csrgen.py
migen/bank/description.py

index 019c11950ad37a90434ba262d7b9f57757698350..1a7387914dfbda53aa0bb8a405873e79733a4e80 100644 (file)
@@ -1,17 +1,18 @@
 from migen.fhdl.structure import *
 from migen.fhdl import verilog
 from migen.bank import description, csrgen
+from migen.bank.description import READ_ONLY, WRITE_ONLY
 
-ninputs = 4
-noutputs = 31
+ninputs = 32
+noutputs = 32
 
 oreg = description.RegisterField("o", noutputs)
-ireg = description.RegisterRaw("i", ninputs)
+ireg = description.RegisterField("i", ninputs, READ_ONLY, WRITE_ONLY)
 
 # input path
 gpio_in = Signal(BV(ninputs))
 gpio_in_s = Signal(BV(ninputs)) # synchronizer
-insync = [gpio_in_s.eq(gpio_in), ireg.w.eq(gpio_in_s)]
+insync = [gpio_in_s.eq(gpio_in), ireg.field.w.eq(gpio_in_s)]
 inf = Fragment(sync=insync)
 
 bank = csrgen.Bank([oreg, ireg])
index 88c43615fb3f35e5ba53819b88a5e89a55e29bf7..c87650898b99f007037723937ba2d2eeb69983c9 100644 (file)
@@ -71,9 +71,12 @@ class Bank:
                for reg in self.description:
                        if isinstance(reg, RegisterFields):
                                for field in reg.fields:
-                                       if field.access_dev == READ_ONLY or field.access_dev == READ_WRITE:
-                                               comb.append(field.r.eq(field.storage))
-                                       if field.access_dev == WRITE_ONLY or field.access_dev == READ_WRITE:
-                                               sync.append(If(field.we, field.storage.eq(field.w)))
+                                       if field.access_bus == READ_ONLY and field.access_dev == WRITE_ONLY:
+                                               comb.append(field.storage.eq(field.w))
+                                       else:
+                                               if field.access_dev == READ_ONLY or field.access_dev == READ_WRITE:
+                                                       comb.append(field.r.eq(field.storage))
+                                               if field.access_dev == WRITE_ONLY or field.access_dev == READ_WRITE:
+                                                       sync.append(If(field.we, field.storage.eq(field.w)))
                
                return Fragment(comb, sync)
index 325738f71a750cfc393a0cb63cc247c5b9de860d..415ed809a9c49a1748952f2a299b39a94ce508b0 100644 (file)
@@ -17,11 +17,14 @@ class Field:
                self.access_bus = access_bus
                self.access_dev = access_dev
                self.storage = Signal(BV(self.size), reset=reset)
-               if self.access_dev == READ_ONLY or self.access_dev == READ_WRITE:
-                       self.r = Signal(BV(self.size))
-               if self.access_dev == WRITE_ONLY or self.access_dev == READ_WRITE:
+               if self.access_bus == READ_ONLY and self.access_dev == WRITE_ONLY:
                        self.w = Signal(BV(self.size))
-                       self.we = Signal()
+               else:
+                       if self.access_dev == READ_ONLY or self.access_dev == READ_WRITE:
+                               self.r = Signal(BV(self.size))
+                       if self.access_dev == WRITE_ONLY or self.access_dev == READ_WRITE:
+                               self.w = Signal(BV(self.size))
+                               self.we = Signal()
 
 class RegisterFields:
        def __init__(self, name, fields):