re PR target/51244 ([SH] Inefficient conditional branch and code around T bit)

	PR target/51244
	* config/sh/predicates.md (general_movsrc_operand,
	general_movdst_operand): Reject T_REG.
	* config/sh/sh.md (*extendqisi2_compact_reg, *extendhisi2_compact_reg,
	movsi_i, movsi_ie, movsi_i_lowpart, *movqi_reg_reg, *movhi_reg_reg):
	Remove T_REG alternatives.
	(*negtstsi): New insn.

From-SVN: r189797

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 790677c26d851b5e7d2ca870f55f2eac5c7d5191..9506f1cb2c632d15b52e260a01941ef47cd990c6 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2012-07-23  Oleg Endo  <olegendo@gcc.gnu.org>
+
+       PR target/51244
+       * config/sh/predicates.md (general_movsrc_operand,
+       general_movdst_operand): Reject T_REG.
+       * config/sh/sh.md (*extendqisi2_compact_reg, *extendhisi2_compact_reg,
+       movsi_i, movsi_ie, movsi_i_lowpart, *movqi_reg_reg, *movhi_reg_reg):
+       Remove T_REG alternatives.
+       (*negtstsi): New insn.
+
 2012-07-23  Oleg Endo  <olegendo@gcc.gnu.org>
 
        PR target/53511

diff --git a/gcc/config/sh/predicates.md b/gcc/config/sh/predicates.md
index 4d793b19c5250cd1a6d519c4103541b403544016..3b9372125471fa0395197764b0c7dbb0df910424 100644 (file)
--- a/gcc/config/sh/predicates.md
+++ b/gcc/config/sh/predicates.md
@@ -382,6 +382,9 @@
 (define_predicate "general_movsrc_operand"
   (match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,const,const_vector")
 {
+  if (t_reg_operand (op, mode))
+    return 0;
+
   if (MEM_P (op))
     {
       rtx inside = XEXP (op, 0);
@@ -455,6 +458,9 @@
 (define_predicate "general_movdst_operand"
   (match_code "subreg,reg,mem")
 {
+  if (t_reg_operand (op, mode))
+    return 0;
+
   /* Only pre dec allowed.  */
   if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC)
     return 0;

diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 08926d990d9ef10bed0670db43cf903e6e5caabc..a8c11b504f3811f7bde2cb9f1311a720a405e5cc 100644 (file)
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -779,6 +779,18 @@
        cmp/pz  %0"
    [(set_attr "type" "mt_group")])
 
+;; FIXME: This is actually wrong.  There is no way to literally move a
+;; general reg to t reg.  Luckily, it seems that this pattern will be only
+;; used when the general reg is known be either '0' or '1' during combine.
+;; What we actually need is reg != 0 -> T, but we have only reg == 0 -> T.
+;; Due to interactions with other patterns, combine fails to pick the latter
+;; and invert the dependent logic.
+(define_insn "*negtstsi"
+  [(set (reg:SI T_REG) (match_operand:SI 0 "arith_reg_operand" "r"))]
+  "TARGET_SH1"
+  "cmp/pl      %0"
+   [(set_attr "type" "mt_group")])
+
 ;; -------------------------------------------------------------------------
 ;; SImode compare and branch
 ;; -------------------------------------------------------------------------
@@ -4793,22 +4805,18 @@ label:
 })
 
 (define_insn "*extendqisi2_compact_reg"
-  [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
-       (sign_extend:SI (match_operand:QI 1 "register_operand" "r,t")))]
+  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
+       (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
   "TARGET_SH1"
-  "@
-       exts.b  %1,%0
-       movt    %0"
-  [(set_attr "type" "arith,arith")])
+  "exts.b      %1,%0"
+  [(set_attr "type" "arith")])
 
 (define_insn "*extendhisi2_compact_reg"
-  [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
-       (sign_extend:SI (match_operand:HI 1 "register_operand" "r,t")))]
+  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
+       (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
   "TARGET_SH1"
-  "@
-       exts.w  %1,%0
-       movt    %0"
-  [(set_attr "type" "arith,arith")])
+  "exts.w      %1,%0"
+  [(set_attr "type" "arith")])
 
 ;; FIXME: Fold non-SH2A and SH2A alternatives with "enabled" attribute.
 ;; See movqi insns.
@@ -5102,9 +5110,9 @@ label:
 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
 (define_insn "movsi_i"
   [(set (match_operand:SI 0 "general_movdst_operand"
-           "=r,r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
+           "=r,r,r,r,r,r,m,<,<,x,l,x,l,r")
        (match_operand:SI 1 "general_movsrc_operand"
-        "Q,r,I08,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
+        "Q,r,I08,mr,x,l,r,x,l,r,r,>,>,i"))]
   "TARGET_SH1
    && ! TARGET_SH2E
    && ! TARGET_SH2A
@@ -5114,11 +5122,9 @@ label:
        mov.l   %1,%0
        mov     %1,%0
        mov     %1,%0
-       cmp/pl  %1
        mov.l   %1,%0
        sts     %1,%0
        sts     %1,%0
-       movt    %0
        mov.l   %1,%0
        sts.l   %1,%0
        sts.l   %1,%0
@@ -5127,8 +5133,8 @@ label:
        lds.l   %1,%0
        lds.l   %1,%0
        fake    %1,%0"
-  [(set_attr "type" "pcload_si,move,movi8,mt_group,load_si,mac_gp,prget,arith,store,mac_mem,pstore,gp_mac,prset,mem_mac,pload,pcload_si")
-   (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
+  [(set_attr "type" "pcload_si,move,movi8,load_si,mac_gp,prget,store,mac_mem,pstore,gp_mac,prset,mem_mac,pload,pcload_si")
+   (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
 
 ;; t/r must come after r/r, lest reload will try to reload stuff like
 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
@@ -5138,9 +5144,9 @@ label:
 ;; TARGET_FMOVD is in effect, and mode switching is done before reload.
 (define_insn "movsi_ie"
   [(set (match_operand:SI 0 "general_movdst_operand"
-           "=r,r,r,r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
+           "=r,r,r,r,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
        (match_operand:SI 1 "general_movsrc_operand"
-        "Q,r,I08,I20,I28,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
+        "Q,r,I08,I20,I28,mr,x,l,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
   "(TARGET_SH2E || TARGET_SH2A)
    && (register_operand (operands[0], SImode)
        || register_operand (operands[1], SImode))"
@@ -5150,11 +5156,9 @@ label:
        mov     %1,%0
        movi20  %1,%0
        movi20s %1,%0
-       cmp/pl  %1
        mov.l   %1,%0
        sts     %1,%0
        sts     %1,%0
-       movt    %0
        mov.l   %1,%0
        sts.l   %1,%0
        sts.l   %1,%0
@@ -5171,21 +5175,19 @@ label:
        flds    %1,fpul
        fmov    %1,%0
        ! move optimized away"
-  [(set_attr "type" "pcload_si,move,movi8,move,move,*,load_si,mac_gp,prget,arith,store,mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
-   (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
+  [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
+   (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
    (set_attr_alternative "length"
      [(const_int 2)
       (const_int 2)
       (const_int 2)
       (const_int 4)
       (const_int 4)
-      (const_int 2)
       (if_then_else
        (match_test "TARGET_SH2A")
        (const_int 4) (const_int 2))
       (const_int 2)
       (const_int 2)
-      (const_int 2)
       (if_then_else
        (match_test "TARGET_SH2A")
        (const_int 4) (const_int 2))
@@ -5206,8 +5208,8 @@ label:
       (const_int 0)])])
 
 (define_insn "movsi_i_lowpart"
-  [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,r,m,r"))
-       (match_operand:SI 1 "general_movsrc_operand" "Q,r,I08,mr,x,l,t,r,i"))]
+  [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
+       (match_operand:SI 1 "general_movsrc_operand" "Q,r,I08,mr,x,l,r,i"))]
    "TARGET_SH1
     && (register_operand (operands[0], SImode)
         || register_operand (operands[1], SImode))"
@@ -5218,10 +5220,9 @@ label:
        mov.l   %1,%0
        sts     %1,%0
        sts     %1,%0
-       movt    %0
        mov.l   %1,%0
        fake    %1,%0"
-  [(set_attr "type" "pcload,move,arith,load,mac_gp,prget,arith,store,pcload")])
+  [(set_attr "type" "pcload,move,arith,load,mac_gp,prget,store,pcload")])
 
 (define_insn_and_split "load_ra"
   [(set (match_operand:SI 0 "general_movdst_operand" "")
@@ -5488,22 +5489,18 @@ label:
 ;; try other insns and not stick to movqi_reg_reg.
 ;; The same applies to the movhi variants.
 (define_insn "*movqi_reg_reg"
-  [(set (match_operand:QI 0 "arith_reg_dest"   "=r,r")
-       (match_operand:QI 1 "register_operand" "r,t"))]
+  [(set (match_operand:QI 0 "arith_reg_dest" "=r")
+       (match_operand:QI 1 "register_operand" "r"))]
   "TARGET_SH1"
-  "@
-       mov     %1,%0
-       movt    %0"
-  [(set_attr "type" "move,arith")])
+  "mov %1,%0"
+  [(set_attr "type" "move")])
 
 (define_insn "*movhi_reg_reg"
-  [(set (match_operand:HI 0 "arith_reg_dest"   "=r,r")
-       (match_operand:HI 1 "register_operand" "r,t"))]
+  [(set (match_operand:HI 0 "arith_reg_dest" "=r")
+       (match_operand:HI 1 "register_operand" "r"))]
   "TARGET_SH1"
-  "@
-       mov     %1,%0
-       movt    %0"
-  [(set_attr "type" "move,arith")])
+  "mov %1,%0"
+  [(set_attr "type" "move")])
 
 ;; FIXME: The non-SH2A and SH2A variants should be combined by adding
 ;; "enabled" attribute as it is done in other targets.