color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
S_028C74_NUM_FRAGMENTS(log_fragments);
- if (tex->fmask_offset) {
+ if (tex->surface.fmask_offset) {
color_info |= S_028C70_COMPRESSION(1);
unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
}
surf->db_htile_data_base = (tex->buffer.gpu_address +
- tex->htile_offset) >> 8;
+ tex->surface.htile_offset) >> 8;
surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned);
if (sctx->chip_class == GFX9) {
}
surf->db_htile_data_base = (tex->buffer.gpu_address +
- tex->htile_offset) >> 8;
+ tex->surface.htile_offset) >> 8;
surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
if (tex->tc_compatible_htile) {
struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
struct si_texture *tex = (struct si_texture*)surf->texture;
- if (tex->fmask_offset)
+ if (tex->surface.fmask_offset)
tex->dirty_level_mask |= 1 << surf->u.tex.level;
if (tex->dcc_gather_statistics)
tex->separate_dcc_dirty = true;
if (surf->color_is_int10)
sctx->framebuffer.color_is_int10 |= 1 << i;
- if (tex->fmask_offset)
+ if (tex->surface.fmask_offset)
sctx->framebuffer.compressed_cb_mask |= 1 << i;
else
sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
if (cb->base.u.tex.level > 0)
cb_color_info &= C_028C70_FAST_CLEAR;
- if (tex->fmask_offset) {
- cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
+ if (tex->surface.fmask_offset) {
+ cb_color_fmask = (tex->buffer.gpu_address + tex->surface.fmask_offset) >> 8;
cb_color_fmask |= tex->surface.fmask_tile_swizzle;
}
cb_color_info |= S_028C70_DCC_ENABLE(1);
cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
- tex->dcc_offset) >> 8;
+ tex->surface.dcc_offset) >> 8;
unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
dcc_tile_swizzle &= (tex->surface.dcc_alignment - 1) >> 8;
/* Set mutable surface parameters. */
cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
cb_color_base |= tex->surface.tile_swizzle;
- if (!tex->fmask_offset)
+ if (!tex->surface.fmask_offset)
cb_color_fmask = cb_color_base;
if (cb->base.u.tex.level > 0)
cb_color_cmask = cb_color_base;
} else if (sctx->chip_class == GFX9) {
struct gfx9_surf_meta_flags meta;
- if (tex->dcc_offset)
+ if (tex->surface.dcc_offset)
meta = tex->surface.u.gfx9.dcc;
else
meta = tex->surface.u.gfx9.cmask;
/* Set mutable surface parameters. */
cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
cb_color_base |= tex->surface.tile_swizzle;
- if (!tex->fmask_offset)
+ if (!tex->surface.fmask_offset)
cb_color_fmask = cb_color_base;
if (cb->base.u.tex.level > 0)
cb_color_cmask = cb_color_base;
if (level_info->mode == RADEON_SURF_MODE_2D)
cb_color_base |= tex->surface.tile_swizzle;
- if (!tex->fmask_offset)
+ if (!tex->surface.fmask_offset)
cb_color_fmask = cb_color_base;
if (cb->base.u.tex.level > 0)
cb_color_cmask = cb_color_base;
cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
- if (tex->fmask_offset) {
+ if (tex->surface.fmask_offset) {
if (sctx->chip_class >= GFX7)
cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
state[6] = 0;
state[7] = 0;
- if (tex->dcc_offset) {
+ if (tex->surface.dcc_offset) {
state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
}
/* Initialize the sampler view for FMASK. */
- if (tex->fmask_offset) {
+ if (tex->surface.fmask_offset) {
uint32_t format;
- va = tex->buffer.gpu_address + tex->fmask_offset;
+ va = tex->buffer.gpu_address + tex->surface.fmask_offset;
#define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
state[5] |= S_008F24_LAST_ARRAY(last_layer);
}
- if (tex->dcc_offset) {
+ if (tex->surface.dcc_offset) {
state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
} else {
/* The last dword is unused by hw. The shader uses it to clear
}
/* Initialize the sampler view for FMASK. */
- if (tex->fmask_offset) {
+ if (tex->surface.fmask_offset) {
uint32_t data_format, num_format;
- va = tex->buffer.gpu_address + tex->fmask_offset;
+ va = tex->buffer.gpu_address + tex->surface.fmask_offset;
#define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
if (screen->info.chip_class == GFX9) {
static bool si_can_disable_dcc(struct si_texture *tex)
{
/* We can't disable DCC if it can be written by another process. */
- return tex->dcc_offset &&
+ return tex->surface.dcc_offset &&
(!tex->buffer.b.is_shared ||
!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE));
}
static void si_texture_zero_dcc_fields(struct si_texture *tex)
{
- tex->dcc_offset = 0;
- tex->display_dcc_offset = 0;
- tex->dcc_retile_map_offset = 0;
+ tex->surface.dcc_offset = 0;
+ tex->surface.display_dcc_offset = 0;
+ tex->surface.dcc_retile_map_offset = 0;
}
static bool si_texture_discard_dcc(struct si_screen *sscreen,
struct si_texture *tex)
{
if (!si_can_disable_dcc(tex)) {
- assert(tex->display_dcc_offset == 0);
+ assert(tex->surface.display_dcc_offset == 0);
return false;
}
tex->buffer.flags = new_tex->buffer.flags;
tex->surface = new_tex->surface;
- tex->size = new_tex->size;
si_texture_reference(&tex->flushed_depth_texture,
new_tex->flushed_depth_texture);
- tex->fmask_offset = new_tex->fmask_offset;
- tex->cmask_offset = new_tex->cmask_offset;
+ tex->surface.fmask_offset = new_tex->surface.fmask_offset;
+ tex->surface.cmask_offset = new_tex->surface.cmask_offset;
tex->cmask_base_address_reg = new_tex->cmask_base_address_reg;
if (tex->cmask_buffer == &tex->buffer)
else
si_resource_reference(&tex->cmask_buffer, new_tex->cmask_buffer);
- tex->dcc_offset = new_tex->dcc_offset;
+ tex->surface.dcc_offset = new_tex->surface.dcc_offset;
tex->cb_color_info = new_tex->cb_color_info;
memcpy(tex->color_clear_value, new_tex->color_clear_value,
sizeof(tex->color_clear_value));
tex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode;
- tex->htile_offset = new_tex->htile_offset;
+ tex->surface.htile_offset = new_tex->surface.htile_offset;
tex->depth_clear_value = new_tex->depth_clear_value;
tex->dirty_level_mask = new_tex->dirty_level_mask;
tex->stencil_dirty_level_mask = new_tex->stencil_dirty_level_mask;
new_tex->last_dcc_separate_buffer);
if (new_bind_flag == PIPE_BIND_LINEAR) {
- assert(!tex->htile_offset);
+ assert(!tex->surface.htile_offset);
assert(!tex->cmask_buffer);
assert(!tex->surface.fmask_size);
- assert(!tex->dcc_offset);
+ assert(!tex->surface.dcc_offset);
assert(!tex->is_depth);
}
if (sscreen->info.chip_class >= GFX9) {
md.u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
- if (tex->dcc_offset && !tex->dcc_separate_buffer) {
+ if (tex->surface.dcc_offset && !tex->dcc_separate_buffer) {
uint64_t dcc_offset =
- tex->display_dcc_offset ? tex->display_dcc_offset
- : tex->dcc_offset;
+ tex->surface.display_dcc_offset ? tex->surface.display_dcc_offset
+ : tex->surface.dcc_offset;
assert((dcc_offset >> 8) != 0 && (dcc_offset >> 8) < (1 << 24));
md.u.gfx9.dcc_offset_256B = dcc_offset >> 8;
case GFX7:
break;
case GFX8:
- desc[7] = tex->dcc_offset >> 8;
+ desc[7] = tex->surface.dcc_offset >> 8;
break;
case GFX9:
- desc[7] = tex->dcc_offset >> 8;
+ desc[7] = tex->surface.dcc_offset >> 8;
desc[5] &= C_008F24_META_DATA_ADDRESS;
- desc[5] |= S_008F24_META_DATA_ADDRESS(tex->dcc_offset >> 40);
+ desc[5] |= S_008F24_META_DATA_ADDRESS(tex->surface.dcc_offset >> 40);
break;
case GFX10:
desc[6] &= C_00A018_META_DATA_ADDRESS_LO;
- desc[6] |= S_00A018_META_DATA_ADDRESS_LO(tex->dcc_offset >> 8);
- desc[7] = tex->dcc_offset >> 16;
+ desc[6] |= S_00A018_META_DATA_ADDRESS_LO(tex->surface.dcc_offset >> 8);
+ desc[7] = tex->surface.dcc_offset >> 16;
break;
default:
assert(0);
*/
switch (sscreen->info.chip_class) {
case GFX8:
- tex->dcc_offset = (uint64_t)desc[7] << 8;
+ tex->surface.dcc_offset = (uint64_t)desc[7] << 8;
break;
case GFX9:
- tex->dcc_offset =
+ tex->surface.dcc_offset =
((uint64_t)desc[7] << 8) |
((uint64_t)G_008F24_META_DATA_ADDRESS(desc[5]) << 40);
tex->surface.u.gfx9.dcc.pipe_aligned =
break;
case GFX10:
- tex->dcc_offset =
+ tex->surface.dcc_offset =
((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc[6]) << 8) |
((uint64_t)desc[7] << 16);
tex->surface.u.gfx9.dcc.pipe_aligned =
* (it can't be scanned out and rendered to simultaneously)
*/
if (sscreen->info.use_display_dcc_unaligned &&
- tex->dcc_offset &&
+ tex->surface.dcc_offset &&
!tex->surface.u.gfx9.dcc.pipe_aligned &&
!tex->surface.u.gfx9.dcc.rb_aligned)
return true;
/* This needs an explicit flush (flush_resource). */
if (sscreen->info.use_display_dcc_with_retile_blit &&
- tex->display_dcc_offset)
+ tex->surface.display_dcc_offset)
return true;
return false;
* disable it for external clients that want write
* access.
*/
- if ((usage & PIPE_HANDLE_USAGE_SHADER_WRITE && tex->dcc_offset) ||
+ if ((usage & PIPE_HANDLE_USAGE_SHADER_WRITE && tex->surface.dcc_offset) ||
/* Displayable DCC requires an explicit flush. */
(!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
si_has_displayable_dcc(tex))) {
}
if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
- (tex->cmask_buffer || tex->dcc_offset)) {
+ (tex->cmask_buffer || tex->surface.dcc_offset)) {
/* Eliminate fast clear (both CMASK and DCC) */
si_eliminate_fast_color_clear(sctx, tex);
/* eliminate_fast_color_clear flushes the context */
tex->surface.u.gfx9.surf.epitch,
tex->surface.u.gfx9.surf_pitch);
- if (tex->fmask_offset) {
+ if (tex->surface.fmask_offset) {
u_log_printf(log, " FMASK: offset=%"PRIu64", size=%"PRIu64", "
"alignment=%u, swmode=%u, epitch=%u\n",
- tex->fmask_offset,
+ tex->surface.fmask_offset,
tex->surface.fmask_size,
tex->surface.fmask_alignment,
tex->surface.u.gfx9.fmask.swizzle_mode,
if (tex->cmask_buffer) {
u_log_printf(log, " CMask: offset=%"PRIu64", size=%u, "
"alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
- tex->cmask_offset,
+ tex->surface.cmask_offset,
tex->surface.cmask_size,
tex->surface.cmask_alignment,
tex->surface.u.gfx9.cmask.rb_aligned,
tex->surface.u.gfx9.cmask.pipe_aligned);
}
- if (tex->htile_offset) {
+ if (tex->surface.htile_offset) {
u_log_printf(log, " HTile: offset=%"PRIu64", size=%u, alignment=%u, "
"rb_aligned=%u, pipe_aligned=%u\n",
- tex->htile_offset,
+ tex->surface.htile_offset,
tex->surface.htile_size,
tex->surface.htile_alignment,
tex->surface.u.gfx9.htile.rb_aligned,
tex->surface.u.gfx9.htile.pipe_aligned);
}
- if (tex->dcc_offset) {
+ if (tex->surface.dcc_offset) {
u_log_printf(log, " DCC: offset=%"PRIu64", size=%u, "
"alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
- tex->dcc_offset, tex->surface.dcc_size,
+ tex->surface.dcc_offset, tex->surface.dcc_size,
tex->surface.dcc_alignment,
tex->surface.u.gfx9.display_dcc_pitch_max,
tex->surface.num_dcc_levels);
tex->surface.u.legacy.tile_split, tex->surface.u.legacy.pipe_config,
(tex->surface.flags & RADEON_SURF_SCANOUT) != 0);
- if (tex->fmask_offset)
+ if (tex->surface.fmask_offset)
u_log_printf(log, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, "
"bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
- tex->fmask_offset, tex->surface.fmask_size, tex->surface.fmask_alignment,
+ tex->surface.fmask_offset, tex->surface.fmask_size, tex->surface.fmask_alignment,
tex->surface.u.legacy.fmask.pitch_in_pixels,
tex->surface.u.legacy.fmask.bankh,
tex->surface.u.legacy.fmask.slice_tile_max,
if (tex->cmask_buffer)
u_log_printf(log, " CMask: offset=%"PRIu64", size=%u, alignment=%u, "
"slice_tile_max=%u\n",
- tex->cmask_offset, tex->surface.cmask_size, tex->surface.cmask_alignment,
+ tex->surface.cmask_offset, tex->surface.cmask_size, tex->surface.cmask_alignment,
tex->surface.u.legacy.cmask_slice_tile_max);
- if (tex->htile_offset)
+ if (tex->surface.htile_offset)
u_log_printf(log, " HTile: offset=%"PRIu64", size=%u, "
"alignment=%u, TC_compatible = %u\n",
- tex->htile_offset, tex->surface.htile_size,
+ tex->surface.htile_offset, tex->surface.htile_size,
tex->surface.htile_alignment,
tex->tc_compatible_htile);
- if (tex->dcc_offset) {
+ if (tex->surface.dcc_offset) {
u_log_printf(log, " DCC: offset=%"PRIu64", size=%u, alignment=%u\n",
- tex->dcc_offset, tex->surface.dcc_size,
+ tex->surface.dcc_offset, tex->surface.dcc_size,
tex->surface.dcc_alignment);
for (i = 0; i <= tex->buffer.b.b.last_level; i++)
u_log_printf(log, " DCCLevel[%i]: enabled=%u, offset=%u, "
*/
tex->ps_draw_ratio = 0;
- /* TODO: remove these */
- tex->fmask_offset = tex->surface.fmask_offset;
- tex->cmask_offset = tex->surface.cmask_offset;
- tex->htile_offset = tex->surface.htile_offset;
- tex->dcc_offset = tex->surface.dcc_offset;
- tex->display_dcc_offset = tex->surface.display_dcc_offset;
- tex->dcc_retile_map_offset = tex->surface.dcc_retile_map_offset;
- tex->size = tex->surface.total_size;
-
if (tex->is_depth) {
if (sscreen->info.chip_class >= GFX9) {
tex->can_sample_z = true;
/* Now create the backing buffer. */
if (!buf) {
- si_init_resource_fields(sscreen, resource, tex->size,
+ si_init_resource_fields(sscreen, resource, tex->surface.total_size,
tex->surface.surf_alignment);
if (!si_alloc_resource(sscreen, resource))
if (tex->cmask_buffer) {
/* Initialize the cmask to 0xCC (= compressed state). */
si_screen_clear_buffer(sscreen, &tex->cmask_buffer->b.b,
- tex->cmask_offset, tex->surface.cmask_size,
+ tex->surface.cmask_offset, tex->surface.cmask_size,
0xCCCCCCCC);
}
- if (tex->htile_offset) {
+ if (tex->surface.htile_offset) {
uint32_t clear_value = 0;
if (sscreen->info.chip_class >= GFX9 || tex->tc_compatible_htile)
clear_value = 0x0000030F;
si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
- tex->htile_offset,
+ tex->surface.htile_offset,
tex->surface.htile_size,
clear_value);
}
/* Initialize DCC only if the texture is not being imported. */
- if (!buf && tex->dcc_offset) {
+ if (!buf && tex->surface.dcc_offset) {
/* Clear DCC to black for all tiles with DCC enabled.
*
* This fixes corruption in 3DMark Slingshot Extreme, which
tex->buffer.b.b.nr_samples <= 2) {
/* Simple case - all tiles have DCC enabled. */
si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
- tex->dcc_offset,
+ tex->surface.dcc_offset,
tex->surface.dcc_size,
DCC_CLEAR_COLOR_0000);
} else if (sscreen->info.chip_class >= GFX9) {
/* Clear to uncompressed. Clearing this to black is complicated. */
si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
- tex->dcc_offset,
+ tex->surface.dcc_offset,
tex->surface.dcc_size,
DCC_UNCOMPRESSED);
} else {
if (tex->buffer.b.b.nr_samples >= 2) {
/* Clearing this to black is complicated. */
si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
- tex->dcc_offset,
+ tex->surface.dcc_offset,
tex->surface.dcc_size,
DCC_UNCOMPRESSED);
} else {
/* Mipmap levels with DCC. */
if (size) {
si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
- tex->dcc_offset, size,
+ tex->surface.dcc_offset, size,
DCC_CLEAR_COLOR_0000);
}
/* Mipmap levels without DCC. */
if (size != tex->surface.dcc_size) {
si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
- tex->dcc_offset + size,
+ tex->surface.dcc_offset + size,
tex->surface.dcc_size - size,
DCC_UNCOMPRESSED);
}
}
/* Upload the DCC retile map. */
- if (tex->dcc_retile_map_offset) {
+ if (tex->surface.dcc_retile_map_offset) {
/* Use a staging buffer for the upload, because
* the buffer backing the texture is unmappable.
*/
struct pipe_box box;
u_box_1d(0, buf->b.b.width0, &box);
- assert(tex->dcc_retile_map_offset <= UINT_MAX);
+ assert(tex->surface.dcc_retile_map_offset <= UINT_MAX);
mtx_lock(&sscreen->aux_context_lock);
sctx->dma_copy(&sctx->b, &tex->buffer.b.b, 0,
- tex->dcc_retile_map_offset, 0, 0,
+ tex->surface.dcc_retile_map_offset, 0, 0,
&buf->b.b, 0, &box);
sscreen->aux_context->flush(sscreen->aux_context, NULL, 0);
mtx_unlock(&sscreen->aux_context_lock);
/* Initialize the CMASK base register value. */
tex->cmask_base_address_reg =
- (tex->buffer.gpu_address + tex->cmask_offset) >> 8;
+ (tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8;
if (sscreen->debug_flags & DBG(VM)) {
fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
/* Initialize the CMASK base address (needed even without CMASK). */
tex->cmask_base_address_reg =
- (tex->buffer.gpu_address + tex->cmask_offset) >> 8;
+ (tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8;
p_atomic_inc(&sscreen->dirty_tex_counter);
- sctx->num_alloc_tex_transfer_bytes += tex->size;
+ sctx->num_alloc_tex_transfer_bytes += tex->surface.total_size;
}
static void *si_texture_transfer_map(struct pipe_context *ctx,
assert(sctx->chip_class >= GFX8);
- if (tex->dcc_offset)
+ if (tex->surface.dcc_offset)
return; /* already enabled */
/* Enable the DCC stat gathering. */
}
/* dcc_offset is the absolute GPUVM address. */
- tex->dcc_offset = tex->dcc_separate_buffer->gpu_address;
+ tex->surface.dcc_offset = tex->dcc_separate_buffer->gpu_address;
/* no need to flag anything since this is called by fast clear that
* flags framebuffer state
assert(!tex->last_dcc_separate_buffer);
tex->last_dcc_separate_buffer = tex->dcc_separate_buffer;
tex->dcc_separate_buffer = NULL;
- tex->dcc_offset = 0;
+ tex->surface.dcc_offset = 0;
/* no need to flag anything since this is called after
* decompression that re-sets framebuffer state
*/
projects / mesa.git / commitdiff