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diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 0fa664b7d1e3632fb5d8245861f199d72c030de2..5eb1382e98eb115d778ccf8d642fcfb3699078f2 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -45,15 +45,19 @@ Table of contents
 ## Introduction
 
 Simple-V is a type of Vectorisation best described as a "Prefix Loop
-Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR` instruction and
-to the 8086 `REP` Prefix instruction.  More advanced features are similar
-to the Z80 `CPIR` instruction. If naively viewed one-dimensionally as an
+Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR`[^bib_ldir] instruction and
+to the 8086 `REP`[^bib_rep] Prefix instruction.  More advanced features are similar
+to the Z80 `CPIR`[^bib_cpir] instruction. If naively viewed one-dimensionally as an
 actual Vector ISA it introduces over 1.5 million 64-bit True-Scalable
 Vector instructions on the SFFS Subset and closer to 10 million 64-bit
 True-Scalable Vector instructions if introduced on VSX.  SVP64, the
 instruction format used by Simple-V, is therefore best viewed as an
 orthogonal RISC-paradigm "Prefixing" subsystem instead.
 
+[^bib_ldir]:  [Zilog Z80 LDIR](http://z80-heaven.wikidot.com/instructions-set:ldir)
+[^bib_cpir]:  [Zilog Z80 CPIR](http://z80-heaven.wikidot.com/instructions-set:cpir)
+[^bib_rep]: [8086 REP](https://www.felixcloutier.com/x86/rep:repe:repz:repne:repnz)
+
 Except where explicitly stated all bit numbers remain as in the rest of
 the Power ISA: in MSB0 form (the bits are numbered from 0 at the MSB on
 the left and counting up as you move rightwards to the LSB end). All bit