-OBJS += techlibs/achronix/synth_speedster.o
+OBJS += techlibs/achronix/synth_achronix.o
$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_sim.v))
$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map.v))
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
-// Normal mode DFF negedge clk, negedge reset
-module \$_DFF_N_ (input D, C, output Q);
- parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-// Normal mode DFF
-module \$_DFF_P_ (input D, C, output Q);
- parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-
-// Async Active Low Reset DFF
-module \$_DFF_PN0_ (input D, C, R, output Q);
- parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-// Async Active High Reset DFF
-module \$_DFF_PP0_ (input D, C, R, output Q);
- parameter WYSIWYG="TRUE";
- wire R_i = ~ R;
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-// Async Active Low Reset DFF
-module \$_DFF_PN0_ (input D, C, R, output Q);
- parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
-endmodule
-/* */
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
- parameter WYSIWYG="TRUE";
- wire E_i = ~ E;
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
-endmodule
+// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
+// > Achronix eFPGA technology mapping. User must first simulate the generated \
+// > netlist before going to test it on board/custom chip.
+// > Input/Output buffers <
// Input buffer map
module \$__inpad (input I, output O);
PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
endmodule
-
// Output buffer map
module \$__outpad (input I, output O);
PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
endmodule
+// > end buffers <
+// > Look-Up table <
+// > VT: I still think Achronix folks would have choosen a better \
+// > logic architecture.
// LUT Map
-/* 0 -> datac
- 1 -> cin */
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
output Y;
generate
if (WIDTH == 1) begin
- assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
+ // VT: This is not consistent and ACE will complain: assign Y = ~A[0];
+ LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
+ (.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0));
end else
if (WIDTH == 2) begin
- LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0),.din3(1'b0));
+ LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
+ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0));
end else
if(WIDTH == 3) begin
- LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]),.din3(1'b0));
+ LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_
+ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0));
end else
if(WIDTH == 4) begin
- LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
+ LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_
+ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
-endmodule //
+endmodule
+// > end LUT <
+// > Flops <
+// DFF flop
+module \$_DFF_P_ (input D, C, output Q);
+ DFF _TECHMAP_REPLACE_
+ (.q(Q), .d(D), .ck(C));
+endmodule
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
+// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
+// > Achronix eFPGA technology sim models. User must first simulate the generated \
+// > netlist before going to test it on board/custom chip.
+// > Changelog: 1) Removed unused VCC/GND modules
+// > 2) Altera comments here (?). Removed.
+// > 3) Reusing LUT sim model, removed wrong wires and parameters.
-module VCC (output V);
- assign V = 1'b1;
-endmodule // VCC
-
-module GND (output G);
- assign G = 1'b0;
-endmodule // GND
-
-/* Altera MAX10 devices Input Buffer Primitive */
module PADIN (output padout, input padin);
assign padout = padin;
-endmodule // fiftyfivenm_io_ibuf
+endmodule
-/* Altera MAX10 devices Output Buffer Primitive */
module PADOUT (output padout, input padin, input oe);
assign padout = padin;
assign oe = oe;
-endmodule // fiftyfivenm_io_obuf
+endmodule
-/* Altera MAX10 4-input non-fracturable LUT Primitive */
module LUT4 (output dout,
input din0, din1, din2, din3);
-/* Internal parameters which define the behaviour
- of the LUT primitive.
- lut_mask define the lut function, can be expressed in 16-digit bin or hex.
- sum_lutc_input define the type of LUT (combinational | arithmetic).
- dont_touch for retiming || carry options.
- lpm_type for WYSIWYG */
-
-parameter lut_function = 16'hFFFF;
-//parameter dont_touch = "off";
-//parameter lpm_type = "fiftyfivenm_lcell_comb";
-//parameter sum_lutc_input = "datac";
-
-reg [1:0] lut_type;
-reg cout_rt;
+parameter [15:0] lut_function = 16'hFFFF;
reg combout_rt;
wire dataa_w;
wire datab_w;
wire datac_w;
wire datad_w;
-wire cin_w;
assign dataa_w = din0;
assign datab_w = din1;
s1 = datab ? s2[3:2] : s2[1:0];
lut_data = dataa ? s1[1] : s1[0];
end
-
endfunction
-initial begin
- /*if (sum_lutc_input == "datac")*/ lut_type = 0;
- /*else
- if (sum_lutc_input == "cin") lut_type = 1;
- else begin
- $error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
- $finish();
- end*/
-end
-
always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
- if (lut_type == 0) begin // logic function
- combout_rt = lut_data(lut_function, dataa_w, datab_w,
- datac_w, datad_w);
- end
- else if (lut_type == 1) begin // arithmetic function
- combout_rt = lut_data(lut_function, dataa_w, datab_w,
- cin_w, datad_w);
- end
- cout_rt = lut_data(lut_function, dataa_w, datab_w, cin_w, 'b0);
+ combout_rt = lut_data(lut_function, dataa_w, datab_w,
+ datac_w, datad_w);
end
-
assign dout = combout_rt & 1'b1;
-//assign cout = cout_rt & 1'b1;
-
-endmodule // fiftyfivenm_lcell_comb
-
-/* Altera MAX10 D Flip-Flop Primitive */
-// TODO: Implement advanced simulation functions
-module dffeas ( output q,
- input d, clk, clrn, prn, ena,
- input asdata, aload, sclr, sload );
-
-parameter power_up="dontcare";
-parameter is_wysiwyg="false";
- reg q;
-
- always @(posedge clk)
- q <= d;
-
+endmodule
+
+module DFF (output q,
+ input d, ck);
+ reg q;
+ always @(posedge ck)
+ q <= d;
+
endmodule
--- /dev/null
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthAchronixPass : public ScriptPass {
+ SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { }
+
+ virtual void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" synth_achronix [options]\n");
+ log("\n");
+ log("This command runs synthesis for Achronix Speedster eFPGAs. This work is still experimental.\n");
+ log("\n");
+ log(" -top <module>\n");
+ log(" use the specified module as top module (default='top')\n");
+ log("\n");
+ log(" -vout <file>\n");
+ log(" write the design to the specified Verilog netlist file. writing of an\n");
+ log(" output file is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -run <from_label>:<to_label>\n");
+ log(" only run the commands between the labels (see below). an empty\n");
+ log(" from label is synonymous to 'begin', and empty to label is\n");
+ log(" synonymous to the end of the command list.\n");
+ log("\n");
+ log(" -noflatten\n");
+ log(" do not flatten design before synthesis\n");
+ log("\n");
+ log(" -retime\n");
+ log(" run 'abc' with -dff option\n");
+ log("\n");
+ log("\n");
+ log("The following commands are executed by this synthesis command:\n");
+ help_script();
+ log("\n");
+ }
+
+ string top_opt, family_opt, vout_file;
+ bool retime, flatten;
+
+ virtual void clear_flags() YS_OVERRIDE
+ {
+ top_opt = "-auto-top";
+ vout_file = "";
+ retime = false;
+ flatten = true;
+ }
+
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ string run_from, run_to;
+ clear_flags();
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-top" && argidx+1 < args.size()) {
+ top_opt = "-top " + args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-vout" && argidx+1 < args.size()) {
+ vout_file = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-run" && argidx+1 < args.size()) {
+ size_t pos = args[argidx+1].find(':');
+ if (pos == std::string::npos)
+ break;
+ run_from = args[++argidx].substr(0, pos);
+ run_to = args[argidx].substr(pos+1);
+ continue;
+ }
+ if (args[argidx] == "-flatten") {
+ flatten = true;
+ continue;
+ }
+ if (args[argidx] == "-retime") {
+ retime = true;
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ if (!design->full_selection())
+ log_cmd_error("This comannd only operates on fully selected designs!\n");
+
+ log_header(design, "Executing SYNTH_ACHRONIX pass.\n");
+ log_push();
+
+ run_script(design, run_from, run_to);
+
+ log_pop();
+ }
+
+ virtual void script() YS_OVERRIDE
+ {
+ if (check_label("begin"))
+ {
+ run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v");
+ run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+ }
+
+ if (flatten && check_label("flatten", "(unless -noflatten)"))
+ {
+ run("proc");
+ run("flatten");
+ run("tribuf -logic");
+ run("deminout");
+ }
+
+ if (check_label("coarse"))
+ {
+ run("synth -run coarse");
+ }
+
+ if (check_label("fine"))
+ {
+ run("opt -fast -mux_undef -undriven -fine -full");
+ run("memory_map");
+ run("opt -undriven -fine");
+ run("dffsr2dff");
+ run("dff2dffe -direct-match $_DFF_*");
+ run("opt -fine");
+ run("techmap -map +/techmap.v");
+ run("opt -full");
+ run("clean -purge");
+ run("setundef -undriven -zero");
+ if (retime || help_mode)
+ run("abc -markgroups -dff", "(only if -retime)");
+ }
+
+ if (check_label("map_luts"))
+ {
+ run("abc -lut 4" + string(retime ? " -dff" : ""));
+ run("clean");
+ }
+
+ if (check_label("map_cells"))
+ {
+ run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I");
+ run("techmap -map +/achronix/speedster22i/cells_map.v");
+ // VT: not done yet run("dffinit -highlow -ff DFF q power_up");
+ run("clean -purge");
+ }
+
+ if (check_label("check"))
+ {
+ run("hierarchy -check");
+ run("stat");
+ run("check -noinit");
+ }
+
+ if (check_label("vout"))
+ {
+ if (!vout_file.empty() || help_mode)
+ run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix syn_ %s",
+ help_mode ? "<file-name>" : vout_file.c_str()));
+ }
+ }
+} SynthAchronixPass;
+
+PRIVATE_NAMESPACE_END
+++ /dev/null
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "kernel/register.h"
-#include "kernel/celltypes.h"
-#include "kernel/rtlil.h"
-#include "kernel/log.h"
-
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
-
-struct SynthIntelPass : public ScriptPass {
- SynthIntelPass() : ScriptPass("synth_speedster", "synthesis for Acrhonix Speedster22i FPGAs.") { }
-
- virtual void help() YS_OVERRIDE
- {
- // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
- log("\n");
- log(" synth_speedster [options]\n");
- log("\n");
- log("This command runs synthesis for Achronix Speedster eFPGAs. This work is still experimental.\n");
- log("\n");
- log(" -top <module>\n");
- log(" use the specified module as top module (default='top')\n");
- log("\n");
- log(" -vout <file>\n");
- log(" write the design to the specified Verilog netlist file. writing of an\n");
- log(" output file is omitted if this parameter is not specified.\n");
- log("\n");
- log(" -run <from_label>:<to_label>\n");
- log(" only run the commands between the labels (see below). an empty\n");
- log(" from label is synonymous to 'begin', and empty to label is\n");
- log(" synonymous to the end of the command list.\n");
- log("\n");
- log(" -noflatten\n");
- log(" do not flatten design before synthesis\n");
- log("\n");
- log(" -retime\n");
- log(" run 'abc' with -dff option\n");
- log("\n");
- log("\n");
- log("The following commands are executed by this synthesis command:\n");
- help_script();
- log("\n");
- }
-
- string top_opt, family_opt, vout_file;
- bool retime, flatten;
-
- virtual void clear_flags() YS_OVERRIDE
- {
- top_opt = "-auto-top";
- vout_file = "";
- retime = false;
- flatten = true;
- }
-
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
- {
- string run_from, run_to;
- clear_flags();
-
- size_t argidx;
- for (argidx = 1; argidx < args.size(); argidx++)
- {
- if (args[argidx] == "-top" && argidx+1 < args.size()) {
- top_opt = "-top " + args[++argidx];
- continue;
- }
- if (args[argidx] == "-vout" && argidx+1 < args.size()) {
- vout_file = args[++argidx];
- continue;
- }
- if (args[argidx] == "-run" && argidx+1 < args.size()) {
- size_t pos = args[argidx+1].find(':');
- if (pos == std::string::npos)
- break;
- run_from = args[++argidx].substr(0, pos);
- run_to = args[argidx].substr(pos+1);
- continue;
- }
- if (args[argidx] == "-flatten") {
- flatten = true;
- continue;
- }
- if (args[argidx] == "-retime") {
- retime = true;
- continue;
- }
- break;
- }
- extra_args(args, argidx, design);
-
- if (!design->full_selection())
- log_cmd_error("This comannd only operates on fully selected designs!\n");
-
- log_header(design, "Executing SYNTH_SPEEDSTER pass.\n");
- log_push();
-
- run_script(design, run_from, run_to);
-
- log_pop();
- }
-
- virtual void script() YS_OVERRIDE
- {
- if (check_label("begin"))
- {
- run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v");
- run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
- }
-
- if (flatten && check_label("flatten", "(unless -noflatten)"))
- {
- run("proc");
- run("flatten");
- run("tribuf -logic");
- run("deminout");
- }
-
- if (check_label("coarse"))
- {
- run("synth -run coarse");
- }
-
- if (check_label("fine"))
- {
- run("opt -fast -mux_undef -undriven -fine -full");
- run("memory_map");
- run("opt -undriven -fine");
- run("dffsr2dff");
- run("dff2dffe -direct-match $_DFF_*");
- run("opt -full");
- run("techmap -map +/techmap.v");
- run("opt -fast");
- run("clean -purge");
- run("setundef -undriven -zero");
- if (retime || help_mode)
- run("abc -markgroups -dff", "(only if -retime)");
- }
-
- if (check_label("map_luts"))
- {
- run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
- run("clean");
- }
-
- if (check_label("map_cells"))
- {
- run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I");
- run("techmap -map +/achronix/speedster22i/cells_map.v");
- run("dffinit -ff dffeas Q INIT");
- run("clean -purge");
- }
-
- if (check_label("check"))
- {
- run("hierarchy -check");
- run("stat");
- run("check -noinit");
- }
-
- if (check_label("vout"))
- {
- if (!vout_file.empty() || help_mode)
- run(stringf("write_verilog -nodec -attr2comment -defparam -nohex -renameprefix yosys_ %s",
- help_mode ? "<file-name>" : vout_file.c_str()));
- }
- }
-} SynthIntelPass;
-
-PRIVATE_NAMESPACE_END
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
+// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
+// > Intel FPGA technology mapping. User must first simulate the generated \
+// > netlist before going to test it on board.
+// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed.
+
// Normal mode DFF negedge clk, negedge reset
module \$_DFF_N_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ parameter power_up=1'bx;
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Normal mode DFF
module \$_DFF_P_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ parameter power_up=1'bx;
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active Low Reset DFF
module \$_DFF_PN0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ parameter power_up=1'bx;
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active High Reset DFF
module \$_DFF_PP0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
+ parameter power_up=1'bx;
wire R_i = ~ R;
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
+ parameter power_up=1'bx;
wire E_i = ~ E;
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
endmodule
// Input buffer map
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
+// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
+// > Intel FPGA technology mapping. User must first simulate the generated \
+// > netlist before going to test it on board.
+// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed.
+
// Normal mode DFF negedge clk, negedge reset
module \$_DFF_N_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ parameter power_up=1'bx;
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Normal mode DFF
module \$_DFF_P_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ parameter power_up=1'bx;
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active Low Reset DFF
module \$_DFF_PN0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ parameter power_up=1'bx;
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active High Reset DFF
module \$_DFF_PP0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
+ parameter power_up=1'bx;
wire R_i = ~ R;
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
+ parameter power_up=1'bx;
wire E_i = ~ E;
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
endmodule
// Input buffer map
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
+/* TODO: Describe the following mode */
+module fa
+ (input a_c,
+ input b_c,
+ input cin_c,
+ output cout_t,
+ output sum_x);
+
+ wire a_c;
+ wire b_c;
+ wire cout_t;
+ wire cin_c;
+ wire sum_x;
+ wire VCC;
+
+ assign VCC = 1'b1;
+
+ cycloneiv_lcell_comb gen_sum_0 (.combout(sum_x),
+ .dataa(a_c),
+ .datab(b_c),
+ .datac(cin_c),
+ .datad(VCC));
+ defparam syn__05_.lut_mask = 16'b1001011010010110;
+ defparam syn__05_.sum_lutc_input = "datac";
+
+ cycloneiv_lcell_comb gen_cout_0 (.combout(cout_t),
+ .dataa(cin_c),
+ .datab(b_c),
+ .datac(a_c),
+ .datad(VCC));
+ defparam syn__06_.lut_mask = 16'b1110000011100000;
+ defparam syn__06_.sum_lutc_input = "datac";
+
+endmodule // fa
+
+module f_stage();
+
+endmodule // f_stage
+
+module f_end();
+
+endmodule // f_end
module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] C = {CO, CI};
- cycloneive_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
- genvar i;
+ fa f0 (.a_c(AA[0]),
+ .b_c(BB[0]),
+ .cin_c(C[0]),
+ .cout_t(C0[1]),
+ .sum_x(Y[0]));
+
+ genvar i;
generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
cycloneive_lcell_comb #(.lut_mask(16'b0101_1010_0101_0000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(CO[i]), .dataa(BB[i]), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[i]));
end endgenerate
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
+// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
+// > Intel FPGA technology mapping. User must first simulate the generated \
+// > netlist before going to test it on board.
+// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed.
+
// Normal mode DFF negedge clk, negedge reset
module \$_DFF_N_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ parameter power_up=1'bx;
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Normal mode DFF
module \$_DFF_P_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ parameter power_up=1'bx;
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
+
// Async Active Low Reset DFF
module \$_DFF_PN0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ parameter power_up=1'bx;
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active High Reset DFF
module \$_DFF_PP0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
+ parameter power_up=1'bx;
wire R_i = ~ R;
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
+ parameter power_up=1'bx;
wire E_i = ~ E;
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
endmodule
// Input buffer map
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
+// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
+// > Intel FPGA technology mapping. User must first simulate the generated \
+// > netlist before going to test it on board.
+// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed.
+// 2) Cyclone V 7-input LUT function was wrong implemented. Removed abc option to map this function \
+// and added the explanation in this file instead. Such function needs to be implemented.
+
// Normal mode DFF negedge clk, negedge reset
module \$_DFF_N_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ parameter power_up=1'bx;
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Normal mode DFF
module \$_DFF_P_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ parameter power_up=1'bx;
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active Low Reset DFF
module \$_DFF_PN0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ parameter power_up=1'bx;
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active High Reset DFF
module \$_DFF_PP0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
+ parameter power_up=1'bx;
wire R_i = ~ R;
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
+ parameter power_up=1'bx;
wire E_i = ~ E;
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
endmodule
// Input buffer map
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
+ wire VCC;
+ wire GND;
+ assign {VCC,GND} = {1'b1,1'b0};
+
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
(.combout(Y),
.dataa(A[0]),
.datab(A[1]),
- .datac(1'b1),
- .datad(1'b1),
- .datae(1'b1),
- .dataf(1'b1),
- .datag(1'b1));
+ .datac(VCC),
+ .datad(VCC),
+ .datae(VCC),
+ .dataf(VCC),
+ .datag(VCC));
end
else
if(WIDTH == 3) begin
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
- .datad(1'b1),
- .datae(1'b1),
- .dataf(1'b1),
- .datag(1'b1));
+ .datad(VCC),
+ .datae(VCC),
+ .dataf(VCC),
+ .datag(VCC));
end
else
if(WIDTH == 4) begin
.datab(A[1]),
.datac(A[2]),
.datad(A[3]),
- .datae(1'b1),
- .dataf(1'b1),
- .datag(1'b1));
+ .datae(VCC),
+ .dataf(VCC),
+ .datag(VCC));
end
else
if(WIDTH == 5) begin
.datac(A[2]),
.datad(A[3]),
.datae(A[4]),
- .dataf(1'b1),
- .datag(1'b1));
+ .dataf(VCC),
+ .datag(VCC));
end
else
if(WIDTH == 6) begin
.datad(A[3]),
.datae(A[4]),
.dataf(A[5]),
- .datag(1'b1));
+ .datag(VCC));
end
- else
+ /*else
if(WIDTH == 7) begin
- cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off"))
- _TECHMAP_REPLACE_
- (.combout(Y),
- .dataa(A[0]),
- .datab(A[1]),
- .datac(A[2]),
- .datad(A[3]),
- .datae(A[4]),
- .dataf(A[5]),
- .datag(A[6]));
- end
+ TODO: There's not a just 7-input function on Cyclone V, see the following note:
+ **Extended LUT Mode**
+ Use extended LUT mode to implement a specific set of 7-input functions. The set must
+ be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs.
+ [source](Device Interfaces and Integration Basics for Cyclone V Devices).
+ end*/
else
wire _TECHMAP_FAIL_ = 1;
endgenerate
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
+// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
+// > Intel FPGA technology mapping. User must first simulate the generated \
+// > netlist before going to test it on board.
+// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed.
+
// Normal mode DFF negedge clk, negedge reset
module \$_DFF_N_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ parameter power_up=1'bx;
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Normal mode DFF
module \$_DFF_P_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ parameter power_up=1'bx;
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active Low Reset DFF
module \$_DFF_PN0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ parameter power_up=1'bx;
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active High Reset DFF
module \$_DFF_PP0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
+ parameter power_up=1'bx;
wire R_i = ~ R;
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
+ parameter power_up=1'bx;
wire E_i = ~ E;
- dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
+ dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
endmodule
// Input buffer map
module \$__inpad (input I, output O);
- fiftyfivenm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
+ fiftyfivenm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
- fiftyfivenm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
+ fiftyfivenm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
log("\n");
log("This command runs synthesis for Intel FPGAs.\n");
log("\n");
- log(" -family < max10 | a10gx | cyclonev | cycloneiv | cycloneive>\n");
+ log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n");
log(" generate the synthesis netlist for the specified family.\n");
log(" MAX10 is the default target if not family argument specified.\n");
log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
log(" output file is omitted if this parameter is not specified.\n");
log("\n");
+ log(" -vpr <file>\n");
+ log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n");
+ log(" compatible with the Quartus flow. Writing of an\n");
+ log(" output file is omitted if this parameter is not specified.\n");
+ log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). an empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n");
log("\n");
}
- string top_opt, family_opt, vout_file;
+ string top_opt, family_opt, vout_file, blif_file;
bool retime, flatten, nobram;
virtual void clear_flags() YS_OVERRIDE
top_opt = "-auto-top";
family_opt = "max10";
vout_file = "";
+ blif_file = "";
retime = false;
flatten = true;
nobram = false;
vout_file = args[++argidx];
continue;
}
+ if (args[argidx] == "-vpr" && argidx+1 < args.size()) {
+ blif_file = args[++argidx];
+ continue;
+ }
if (args[argidx] == "-run" && argidx+1 < args.size()) {
size_t pos = args[argidx+1].find(':');
if (pos == std::string::npos)
if (check_label("map_luts"))
{
if(family_opt=="a10gx" || family_opt=="cyclonev")
- run("abc -luts 2:2,3,6:5,10" + string(retime ? " -dff" : ""));
+ run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
else
run("abc -lut 4" + string(retime ? " -dff" : ""));
run("clean");
run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s",
help_mode ? "<file-name>" : vout_file.c_str()));
}
- }
+
+ if (check_label("vpr"))
+ {
+ if (!blif_file.empty() || help_mode)
+ {
+ run(stringf("opt_clean -purge"));
+ run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()));
+ }
+ }
+ }
} SynthIntelPass;
PRIVATE_NAMESPACE_END
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