r600g: evergreen fix for new design

Signed-off-by: Jerome Glisse <jglisse@redhat.com>

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 7ac505c525e861e141b88df559532f916f4e8b97..ed0daab25a12cf0b89addba197aea4437d387094 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -256,11 +256,11 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
        r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
+       r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
+       r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
+       r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
+       r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
+       r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
        return rstate;
 }
 
@@ -895,22 +895,22 @@ static void evergreen_set_constant_buffer(struct pipe_context *ctx, uint shader,
        switch (shader) {
        case PIPE_SHADER_VERTEX:
                rctx->vs_const_buffer.nregs = 0;
-               r600_pipe_state_add_reg(&rctx->vs_const_buffer, R600_GROUP_ALU_CONST,
+               r600_pipe_state_add_reg(&rctx->vs_const_buffer, EVERGREEN_GROUP_CONTEXT,
                                        R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
                                        ALIGN_DIVUP(buffer->width0 >> 4, 16),
                                        0xFFFFFFFF, NULL);
-               r600_pipe_state_add_reg(&rctx->vs_const_buffer, R600_GROUP_ALU_CONST,
+               r600_pipe_state_add_reg(&rctx->vs_const_buffer, EVERGREEN_GROUP_CONTEXT,
                                        R_028980_ALU_CONST_CACHE_VS_0,
                                        0, 0xFFFFFFFF, rbuffer->bo);
                r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
                break;
        case PIPE_SHADER_FRAGMENT:
                rctx->ps_const_buffer.nregs = 0;
-               r600_pipe_state_add_reg(&rctx->ps_const_buffer, R600_GROUP_ALU_CONST,
+               r600_pipe_state_add_reg(&rctx->ps_const_buffer, EVERGREEN_GROUP_CONTEXT,
                                        R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
                                        ALIGN_DIVUP(buffer->width0 >> 4, 16),
                                        0xFFFFFFFF, NULL);
-               r600_pipe_state_add_reg(&rctx->ps_const_buffer, R600_GROUP_ALU_CONST,
+               r600_pipe_state_add_reg(&rctx->ps_const_buffer, EVERGREEN_GROUP_CONTEXT,
                                        R_028940_ALU_CONST_CACHE_PS_0,
                                        0, 0xFFFFFFFF, rbuffer->bo);
                r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);

diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
index 9bd74348664466a18874c9a710a327d78d3dbfec..db9b5656df1113dd7ffe23441bef3a8d8c777355 100644 (file)
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -32,7 +32,7 @@
 #define EVERGREEN_CONTEXT_REG_OFFSET                0X00028000
 #define EVERGREEN_CONTEXT_REG_END                   0X00029000
 #define EVERGREEN_RESOURCE_OFFSET                   0x00030000
-#define EVERGREEN_RESOURCE_END                      0x00030400
+#define EVERGREEN_RESOURCE_END                      0x00034000
 #define EVERGREEN_LOOP_CONST_OFFSET                 0x0003A200
 #define EVERGREEN_LOOP_CONST_END                    0x0003A26C
 #define EVERGREEN_BOOL_CONST_OFFSET                 0x0003A500
@@ -746,29 +746,6 @@
 #define   S_02880C_DUAL_EXPORT_ENABLE(x)               (((x) & 0x1) << 9)
 #define   G_02880C_DUAL_EXPORT_ENABLE(x)               (((x) >> 9) & 0x1)
 #define   C_02880C_DUAL_EXPORT_ENABLE                  0xFFFFFDFF
-#define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x028DF8
-#define   S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) & 0xFF) << 0)
-#define   G_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) >> 0) & 0xFF)
-#define   C_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS         0xFFFFFF00
-#define   S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) & 0x1) << 8)
-#define   G_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) >> 8) & 0x1)
-#define   C_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT         0xFFFFFEFF
-#define R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE       0x028E00
-#define   S_028E00_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
-#define   G_028E00_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
-#define   C_028E00_SCALE                               0x00000000
-#define R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET      0x028E04
-#define   S_028E04_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
-#define   G_028E04_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
-#define   C_028E04_OFFSET                              0x00000000
-#define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE        0x028E08
-#define   S_028E08_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
-#define   G_028E08_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
-#define   C_028E08_SCALE                               0x00000000
-#define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET       0x028E0C
-#define   S_028E0C_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
-#define   G_028E0C_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
-#define   C_028E0C_OFFSET                              0x00000000
 #define R_028A00_PA_SU_POINT_SIZE                    0x028A00
 #define   S_028A00_HEIGHT(x)                           (((x) & 0xFFFF) << 0)
 #define   G_028A00_HEIGHT(x)                           (((x) >> 0) & 0xFFFF)
@@ -1689,11 +1666,29 @@
 #define R_028B54_VGT_SHADER_STAGES_EN                0x00028B54
 #define R_028B70_DB_ALPHA_TO_MASK                    0x00028B70
 #define R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x00028B78
+#define   S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) & 0xFF) << 0)
+#define   G_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) >> 0) & 0xFF)
+#define   C_028B78_POLY_OFFSET_NEG_NUM_DB_BITS         0xFFFFFF00
+#define   S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) & 0x1) << 8)
+#define   G_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) >> 8) & 0x1)
+#define   C_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT         0xFFFFFEFF
 #define R_028B7C_PA_SU_POLY_OFFSET_CLAMP             0x00028B7C
 #define R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE       0x00028B80
+#define   S_028B80_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_028B80_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028B80_SCALE                               0x00000000
 #define R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET      0x00028B84
+#define   S_028B84_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
+#define   G_028B84_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028B84_OFFSET                              0x00000000
 #define R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE        0x00028B88
+#define   S_028B88_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_028B88_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028B88_SCALE                               0x00000000
 #define R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET       0x00028B8C
+#define   S_028B8C_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
+#define   G_028B8C_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028B8C_OFFSET                              0x00000000
 #define R_028B94_VGT_STRMOUT_CONFIG                  0x00028B94
 #define R_028B98_VGT_STRMOUT_BUFFER_CONFIG           0x00028B98
 #define R_028C00_PA_SC_LINE_CNTL                     0x00028C00

diff --git a/src/gallium/drivers/r600/r600_state2.c b/src/gallium/drivers/r600/r600_state2.c
index 6ce82648c15a60f7546d62ef640164d36c51c02c..075b5f03190c25c9dd9f0a3799466e5317fe9846 100644 (file)
--- a/src/gallium/drivers/r600/r600_state2.c
+++ b/src/gallium/drivers/r600/r600_state2.c
@@ -564,7 +564,7 @@ static void r600_flush2(struct pipe_context *ctx, unsigned flags,
                        struct pipe_fence_handle **fence)
 {
        struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-#if 0
+#if 1
        static int dc = 0;
        char dname[256];
 #endif
@@ -572,7 +572,7 @@ static void r600_flush2(struct pipe_context *ctx, unsigned flags,
        if (!rctx->ctx.pm4_cdwords)
                return;
 
-#if 0
+#if 1
        sprintf(dname, "gallium-%08d.bof", dc);
        if (dc < 20) {
                r600_context_dump_bof(&rctx->ctx, dname);
@@ -2050,12 +2050,6 @@ static struct pipe_context *r600_create_context2(struct pipe_screen *screen, voi
        r600_init_query_functions2(rctx);
        r600_init_context_resource_functions2(rctx);
 
-       rctx->blitter = util_blitter_create(&rctx->context);
-       if (rctx->blitter == NULL) {
-               FREE(rctx);
-               return NULL;
-       }
-
        switch (r600_get_family(rctx->radeon)) {
        case CHIP_R600:
        case CHIP_RV610:
@@ -2096,6 +2090,12 @@ static struct pipe_context *r600_create_context2(struct pipe_screen *screen, voi
                return NULL;
        }
 
+       rctx->blitter = util_blitter_create(&rctx->context);
+       if (rctx->blitter == NULL) {
+               FREE(rctx);
+               return NULL;
+       }
+
        return &rctx->context;
 }
 

diff --git a/src/gallium/winsys/r600/drm/evergreen_state.c b/src/gallium/winsys/r600/drm/evergreen_state.c
index d383194211354a76fea984423ec23da983247a66..5781d448ededaa2d29c2ecb2753b5fd003d4e8c4 100644 (file)
--- a/src/gallium/winsys/r600/drm/evergreen_state.c
+++ b/src/gallium/winsys/r600/drm/evergreen_state.c
@@ -329,7 +329,7 @@ static const struct r600_reg evergreen_reg_list[] = {
        {0, 0, R_028C64_CB_COLOR0_PITCH},
        {0, 0, R_028C68_CB_COLOR0_SLICE},
        {0, 0, R_028C6C_CB_COLOR0_VIEW},
-       {1, 0, R_028C70_CB_COLOR0_INFO},
+       {0, 0, R_028C70_CB_COLOR0_INFO},
        {0, 0, R_028C74_CB_COLOR0_ATTRIB},
        {0, 0, R_028C78_CB_COLOR0_DIM},
        {0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -337,7 +337,7 @@ static const struct r600_reg evergreen_reg_list[] = {
        {0, 0, R_028CA0_CB_COLOR1_PITCH},
        {0, 0, R_028CA4_CB_COLOR1_SLICE},
        {0, 0, R_028CA8_CB_COLOR1_VIEW},
-       {1, 0, R_028CAC_CB_COLOR1_INFO},
+       {0, 0, R_028CAC_CB_COLOR1_INFO},
        {0, 0, R_028CB0_CB_COLOR1_ATTRIB},
        {0, 0, R_028CB8_CB_COLOR1_DIM},
        {0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -345,7 +345,7 @@ static const struct r600_reg evergreen_reg_list[] = {
        {0, 0, R_028CDC_CB_COLOR2_PITCH},
        {0, 0, R_028CE0_CB_COLOR2_SLICE},
        {0, 0, R_028CE4_CB_COLOR2_VIEW},
-       {1, 0, R_028CE8_CB_COLOR2_INFO},
+       {0, 0, R_028CE8_CB_COLOR2_INFO},
        {0, 0, R_028CEC_CB_COLOR2_ATTRIB},
        {0, 0, R_028CF0_CB_COLOR2_DIM},
        {0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -353,7 +353,7 @@ static const struct r600_reg evergreen_reg_list[] = {
        {0, 0, R_028D18_CB_COLOR3_PITCH},
        {0, 0, R_028D1C_CB_COLOR3_SLICE},
        {0, 0, R_028D20_CB_COLOR3_VIEW},
-       {1, 0, R_028D24_CB_COLOR3_INFO},
+       {0, 0, R_028D24_CB_COLOR3_INFO},
        {0, 0, R_028D28_CB_COLOR3_ATTRIB},
        {0, 0, R_028D2C_CB_COLOR3_DIM},
        {0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -361,7 +361,7 @@ static const struct r600_reg evergreen_reg_list[] = {
        {0, 0, R_028D54_CB_COLOR4_PITCH},
        {0, 0, R_028D58_CB_COLOR4_SLICE},
        {0, 0, R_028D5C_CB_COLOR4_VIEW},
-       {1, 0, R_028D60_CB_COLOR4_INFO},
+       {0, 0, R_028D60_CB_COLOR4_INFO},
        {0, 0, R_028D64_CB_COLOR4_ATTRIB},
        {0, 0, R_028D68_CB_COLOR4_DIM},
        {0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -369,7 +369,7 @@ static const struct r600_reg evergreen_reg_list[] = {
        {0, 0, R_028D90_CB_COLOR5_PITCH},
        {0, 0, R_028D94_CB_COLOR5_SLICE},
        {0, 0, R_028D98_CB_COLOR5_VIEW},
-       {1, 0, R_028D9C_CB_COLOR5_INFO},
+       {0, 0, R_028D9C_CB_COLOR5_INFO},
        {0, 0, R_028DA0_CB_COLOR5_ATTRIB},
        {0, 0, R_028DA4_CB_COLOR5_DIM},
        {0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -377,7 +377,7 @@ static const struct r600_reg evergreen_reg_list[] = {
        {0, 0, R_028DCC_CB_COLOR6_PITCH},
        {0, 0, R_028DD0_CB_COLOR6_SLICE},
        {0, 0, R_028DD4_CB_COLOR6_VIEW},
-       {1, 0, R_028DD8_CB_COLOR6_INFO},
+       {0, 0, R_028DD8_CB_COLOR6_INFO},
        {0, 0, R_028DDC_CB_COLOR6_ATTRIB},
        {0, 0, R_028DE0_CB_COLOR6_DIM},
        {0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -385,7 +385,7 @@ static const struct r600_reg evergreen_reg_list[] = {
        {0, 0, R_028E08_CB_COLOR7_PITCH},
        {0, 0, R_028E0C_CB_COLOR7_SLICE},
        {0, 0, R_028E10_CB_COLOR7_VIEW},
-       {1, 0, R_028E14_CB_COLOR7_INFO},
+       {0, 0, R_028E14_CB_COLOR7_INFO},
        {0, 0, R_028E18_CB_COLOR7_ATTRIB},
        {0, 0, R_028E1C_CB_COLOR7_DIM},
        {0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -393,7 +393,7 @@ static const struct r600_reg evergreen_reg_list[] = {
        {0, 0, R_028E44_CB_COLOR8_PITCH},
        {0, 0, R_028E48_CB_COLOR8_SLICE},
        {0, 0, R_028E4C_CB_COLOR8_VIEW},
-       {1, 0, R_028E50_CB_COLOR8_INFO},
+       {0, 0, R_028E50_CB_COLOR8_INFO},
        {0, 0, R_028E54_CB_COLOR8_ATTRIB},
        {0, 0, R_028E58_CB_COLOR8_DIM},
        {0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -401,7 +401,7 @@ static const struct r600_reg evergreen_reg_list[] = {
        {0, 0, R_028E60_CB_COLOR9_PITCH},
        {0, 0, R_028E64_CB_COLOR9_SLICE},
        {0, 0, R_028E68_CB_COLOR9_VIEW},
-       {1, 0, R_028E6C_CB_COLOR9_INFO},
+       {0, 0, R_028E6C_CB_COLOR9_INFO},
        {0, 0, R_028E70_CB_COLOR9_ATTRIB},
        {0, 0, R_028E74_CB_COLOR9_DIM},
        {0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -409,7 +409,7 @@ static const struct r600_reg evergreen_reg_list[] = {
        {0, 0, R_028E7C_CB_COLOR10_PITCH},
        {0, 0, R_028E80_CB_COLOR10_SLICE},
        {0, 0, R_028E84_CB_COLOR10_VIEW},
-       {1, 0, R_028E88_CB_COLOR10_INFO},
+       {0, 0, R_028E88_CB_COLOR10_INFO},
        {0, 0, R_028E8C_CB_COLOR10_ATTRIB},
        {0, 0, R_028E90_CB_COLOR10_DIM},
        {0, 0, GROUP_FORCE_NEW_BLOCK},
@@ -417,7 +417,7 @@ static const struct r600_reg evergreen_reg_list[] = {
        {0, 0, R_028E98_CB_COLOR11_PITCH},
        {0, 0, R_028E9C_CB_COLOR11_SLICE},
        {0, 0, R_028EA0_CB_COLOR11_VIEW},
-       {1, 0, R_028EA4_CB_COLOR11_INFO},
+       {0, 0, R_028EA4_CB_COLOR11_INFO},
        {0, 0, R_028EA8_CB_COLOR11_ATTRIB},
        {0, 0, R_028EAC_CB_COLOR11_DIM},
 };
@@ -464,6 +464,7 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
        int r;
 
        memset(ctx, 0, sizeof(struct r600_context));
+       radeon->use_mem_constant = TRUE;
        ctx->radeon = radeon;
        LIST_INITHEAD(&ctx->query_list);
        /* initialize groups */
@@ -511,13 +512,13 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
                        goto out_err;
        }
        /* PS RESOURCE */
-       for (int j = 0, offset = 0; j < 176; j++, offset += 0x1C) {
+       for (int j = 0, offset = 0; j < 176; j++, offset += 0x20) {
                r = evergreen_state_resource_init(ctx, offset);
                if (r)
                        goto out_err;
        }
        /* VS RESOURCE */
-       for (int j = 0, offset = 0x1600; j < 176; j++, offset += 0x1C) {
+       for (int j = 0, offset = 0x1600; j < 176; j++, offset += 0x20) {
                r = evergreen_state_resource_init(ctx, offset);
                if (r)
                        goto out_err;

diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h
index 6023f215bb672c2c9abc22130469314a8ffb7fea..92b2eb1dff11cf298c05e5bfca597b46e4981ec3 100644 (file)
--- a/src/gallium/winsys/r600/drm/r600_priv.h
+++ b/src/gallium/winsys/r600/drm/r600_priv.h
@@ -39,6 +39,7 @@ struct radeon {
        unsigned                        device;
        unsigned                        family;
        enum chip_class                 chip_class;
+       boolean                         use_mem_constant; /* true for evergreen */
 };
 
 struct radeon *r600_new(int fd, unsigned device);

diff --git a/src/gallium/winsys/r600/drm/r600_state2.c b/src/gallium/winsys/r600/drm/r600_state2.c
index 16950bd72d047c5b919a3e034a7e6b48cec70ccf..c29616c9cbc03d5b8ec8373ed0bc330448409d82 100644 (file)
--- a/src/gallium/winsys/r600/drm/r600_state2.c
+++ b/src/gallium/winsys/r600/drm/r600_state2.c
@@ -65,31 +65,12 @@ unsigned radeon_ws_bo_get_handle(struct radeon_ws_bo *pb_bo);
 static void r600_context_queries_suspend(struct r600_context *ctx);
 static void r600_context_queries_resume(struct r600_context *ctx);
 
-static int r600_group_id_register_offset(unsigned offset)
+static int r600_group_id_register_offset(struct r600_context *ctx, unsigned offset)
 {
-       if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) {
-               return R600_GROUP_CONFIG;
-       }
-       if (offset >= R600_CONTEXT_REG_OFFSET && offset < R600_CONTEXT_REG_END) {
-               return R600_GROUP_CONTEXT;
-       }
-       if (offset >= R600_ALU_CONST_OFFSET && offset < R600_ALU_CONST_END) {
-               return R600_GROUP_ALU_CONST;
-       }
-       if (offset >= R600_RESOURCE_OFFSET && offset < R600_RESOURCE_END) {
-               return R600_GROUP_RESOURCE;
-       }
-       if (offset >= R600_SAMPLER_OFFSET && offset < R600_SAMPLER_END) {
-               return R600_GROUP_SAMPLER;
-       }
-       if (offset >= R600_CTL_CONST_OFFSET && offset < R600_CTL_CONST_END) {
-               return R600_GROUP_CTL_CONST;
-       }
-       if (offset >= R600_LOOP_CONST_OFFSET && offset < R600_LOOP_CONST_END) {
-               return R600_GROUP_LOOP_CONST;
-       }
-       if (offset >= R600_BOOL_CONST_OFFSET && offset < R600_BOOL_CONST_END) {
-               return R600_GROUP_BOOL_CONST;
+       for (int i = 0; i < ctx->ngroups; i++) {
+               if (offset >= ctx->groups[i].start_offset && offset <= ctx->groups[i].end_offset) {
+                       return i;
+               }
        }
        return -1;
 }
@@ -119,7 +100,7 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg,
                        continue;
 
                /* find into which group this block is */
-               group_id = r600_group_id_register_offset(reg[i].offset);
+               group_id = r600_group_id_register_offset(ctx, reg[i].offset);
                assert(group_id >= 0);
                group = &ctx->groups[group_id];
 
@@ -1005,7 +986,7 @@ void r600_context_flush(struct r600_context *ctx)
        /* suspend queries */
        r600_context_queries_suspend(ctx);
 
-#if 1
+#if 0
        /* emit cs */
        drmib.num_chunks = 2;
        drmib.chunks = (uint64_t)(uintptr_t)chunk_array;