+2004-04-29 Kazu Hirata <kazu@cs.umass.edu>
+
+ * config/mips/mips.md, config/mips/sb1.md,
+ config/rs6000/rs6000.c: Fix comment typos.
+
2004-04-29 Kazu Hirata <kazu@cs.umass.edu>
* builtins.c, cgraph.c, cgraphunit.c, final.c, fold-const.c:
;; The HI and LO registers are not truly independent. If we move an mthi
;; instruction before an mflo instruction, it will make the result of the
-;; mflo unpredicatable. The same goes for mtlo and mfhi.
+;; mflo unpredictable. The same goes for mtlo and mfhi.
;;
;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
;; Operand 1 is the register we want, operand 2 is the other one.
;; ??? A simple alu insn issued on an LS unit has 0 cycle latency to an EX
;; insn, to a store (for data), and to an xfer insn. It has 1 cycle latency to
;; another LS insn (excluding store data). A simple alu insn issued on an EX
-;; unit has a latency of 5 cycles when the results goes to a LS unit (exluding
+;; unit has a latency of 5 cycles when the results goes to a LS unit (excluding
;; store data), otherwise a latency of 1 cycle.
;; ??? We can not handle latencies properly for simple alu instructions
abort ();
}
-/* Returns the constant for the splat instrunction, if exists. */
+/* Returns the constant for the splat instruction, if exists. */
static int
easy_vector_splat_const (int cst, enum machine_mode mode)