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+From: bugzilla-daemon@libre-soc.org
+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Sun, 07 Jun 2020 22:31:59 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: new
+X-Bugzilla-Watch-Reason: None
+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Formal Verification
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords:
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: colepoirier@gmail.com
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution:
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: lkcl@lkcl.net
+X-Bugzilla-Flags:
+X-Bugzilla-Changed-Fields: bug_id short_desc product version rep_platform
+ op_sys bug_status bug_severity priority component assigned_to reporter cc
+ cf_nlnet_milestone
+Message-ID: <bug-368-13@https.bugs.libre-soc.org/>
+X-Bugzilla-URL: https://bugs.libre-soc.org/
+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 368] New: Need one example unit test of how
+ to run some assembly code "qemu vs simulator" rather than "qemu vs
+ hardware"
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