back.rtlil: do not translate empty fragments.

The resulting Verilog confuses some frontends.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 817f9b2135b0060adad4f7e6ce53315e9895deb4..d4a011c51de026f339455808f771254428b4f30d 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -627,6 +627,9 @@ def convert_fragment(builder, fragment, name, top):
         # name) names.
         memories = OrderedDict()
         for subfragment, sub_name in fragment.subfragments:
+            if not subfragment.ports:
+                continue
+
             sub_params = OrderedDict()
             if hasattr(subfragment, "parameters"):
                 for param_name, param_value in subfragment.parameters.items():