"""
from nmigen import Signal, Record
from nmutil.iocontrol import RecordObject
-from soc.decoder.power_enums import (MicrOp, CryIn, Function,
+from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
SPRfull, SPRreduced, LDSTMode)
-from soc.consts import TT
-from soc.experiment.mem_types import LDSTException
+from openpower.consts import TT
+from openpower.exceptions import LDSTException
class Data(Record):
from nmigen.asserts import Assert, AnyConst, Assume
from nmutil.formaltest import FHDLTestCase
-from soc.decoder.power_decoder import create_pdecode, PowerOp
-from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel,
+from openpower.decoder.power_decoder import create_pdecode, PowerOp
+from openpower.decoder.power_enums import (In1Sel, In2Sel, In3Sel,
OutSel, RC, Form, Function,
LdstLen, CryIn,
MicrOp, SPR, get_csv)
-from soc.decoder.power_decoder2 import (PowerDecode2,
+from openpower.decoder.power_decoder2 import (PowerDecode2,
Decode2ToExecute1Type)
import unittest
import pdb
from nmigen.asserts import Assert, AnyConst
from nmutil.formaltest import FHDLTestCase
-from soc.decoder.power_decoder import create_pdecode, PowerOp
-from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel,
+from openpower.decoder.power_decoder import create_pdecode, PowerOp
+from openpower.decoder.power_enums import (In1Sel, In2Sel, In3Sel,
OutSel, RC, Form,
MicrOp, SPR)
-from soc.decoder.power_decoder2 import (PowerDecode2,
+from openpower.decoder.power_decoder2 import (PowerDecode2,
Decode2ToExecute1Type)
import unittest
import unittest
-from soc.decoder.selectable_int import SelectableInt, onebit
+from openpower.decoder.selectable_int import SelectableInt, onebit
from nmutil.divmod import trunc_divs, trunc_rems
from operator import floordiv, mod
-from soc.decoder.selectable_int import selectltu as ltu
-from soc.decoder.selectable_int import selectgtu as gtu
-from soc.decoder.selectable_int import check_extsign
+from openpower.decoder.selectable_int import selectltu as ltu
+from openpower.decoder.selectable_int import selectgtu as gtu
+from openpower.decoder.selectable_int import check_extsign
trunc_div = floordiv
trunc_rem = mod
def EXTS(value):
""" extends sign bit out from current MSB to all 256 bits
"""
+ print ("EXTS", value, type(value))
assert isinstance(value, SelectableInt)
return SelectableInt(exts(value.value, value.bits) & ((1 << 256)-1), 256)
from nmigen.back.pysim import Settle
from functools import wraps
from copy import copy
-from soc.decoder.orderedset import OrderedSet
-from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
+from openpower.decoder.orderedset import OrderedSet
+from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
selectconcat)
-from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
+from openpower.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
insns, MicrOp, In1Sel, In2Sel, In3Sel,
OutSel, CROutSel,
SVP64RMMode, SVP64PredMode,
SVP64PredInt, SVP64PredCR)
-from soc.decoder.power_enums import SVPtype
+from openpower.decoder.power_enums import SVPtype
-from soc.decoder.helpers import exts, gtu, ltu, undefined
-from soc.consts import PIb, MSRb # big-endian (PowerISA versions)
-from soc.consts import SVP64CROffs
-from soc.decoder.power_svp64 import SVP64RM, decode_extra
+from openpower.decoder.helpers import exts, gtu, ltu, undefined
+from openpower.consts import PIb, MSRb # big-endian (PowerISA versions)
+from openpower.consts import SVP64CROffs
+from openpower.decoder.power_svp64 import SVP64RM, decode_extra
-from soc.decoder.isa.radixmmu import RADIX
-from soc.decoder.isa.mem import Mem, swap_order
+from openpower.decoder.isa.radixmmu import RADIX
+from openpower.decoder.isa.mem import Mem, swap_order
from collections import namedtuple
import math
"""
from copy import copy
-from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
+from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
selectconcat)
-from soc.decoder.helpers import exts, gtu, ltu, undefined
+from openpower.decoder.helpers import exts, gtu, ltu, undefined
import math
import sys
#from nmigen.back.pysim import Settle
from copy import copy
-from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
+from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
selectconcat)
-from soc.decoder.helpers import exts, gtu, ltu, undefined
-from soc.decoder.isa.mem import Mem
-from soc.consts import MSRb # big-endian (PowerISA versions)
+from openpower.decoder.helpers import exts, gtu, ltu, undefined
+from openpower.decoder.isa.mem import Mem
+from openpower.consts import MSRb # big-endian (PowerISA versions)
import math
import sys
from nmigen.back.pysim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
-from soc.decoder.isa.caller import ISACaller
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.decoder.isa.caller import ISACaller, inject
-from soc.decoder.selectable_int import SelectableInt
-from soc.decoder.orderedset import OrderedSet
-from soc.decoder.isa.all import ISA
+from openpower.decoder.isa.caller import ISACaller
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.decoder.isa.caller import ISACaller, inject
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.orderedset import OrderedSet
+from openpower.decoder.isa.all import ISA
class Register:
#from nmigen.back.pysim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
-from soc.decoder.isa.caller import ISACaller
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.decoder.isa.caller import ISACaller, inject, RADIX
-from soc.decoder.selectable_int import SelectableInt
-from soc.decoder.orderedset import OrderedSet
-from soc.decoder.isa.all import ISA
-from soc.decoder.isa.test_caller import run_tst
+from openpower.decoder.isa.caller import ISACaller
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.decoder.isa.caller import ISACaller, inject, RADIX
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.orderedset import OrderedSet
+from openpower.decoder.isa.all import ISA
+from openpower.decoder.isa.test_caller import run_tst
from copy import deepcopy
from nmigen.back.pysim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
-from soc.decoder.isa.caller import ISACaller
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.decoder.isa.caller import ISACaller, SVP64State
-from soc.decoder.selectable_int import SelectableInt
-from soc.decoder.orderedset import OrderedSet
-from soc.decoder.isa.all import ISA
-from soc.decoder.isa.test_caller import Register, run_tst
-from soc.sv.trans.svp64 import SVP64Asm
-from soc.consts import SVP64CROffs
+from openpower.decoder.isa.caller import ISACaller
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.decoder.isa.caller import ISACaller, SVP64State
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.orderedset import OrderedSet
+from openpower.decoder.isa.all import ISA
+from openpower.decoder.isa.test_caller import Register, run_tst
+from openpower.sv.trans.svp64 import SVP64Asm
+from openpower.consts import SVP64CROffs
from copy import deepcopy
class DecoderTestCase(FHDLTestCase):
from nmigen.back.pysim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
-from soc.decoder.isa.caller import ISACaller
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.decoder.isa.caller import ISACaller, SVP64State
-from soc.decoder.selectable_int import SelectableInt
-from soc.decoder.orderedset import OrderedSet
-from soc.decoder.isa.all import ISA
-from soc.decoder.isa.test_caller import Register, run_tst
-from soc.sv.trans.svp64 import SVP64Asm
-from soc.consts import SVP64CROffs
+from openpower.decoder.isa.caller import ISACaller
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.decoder.isa.caller import ISACaller, SVP64State
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.orderedset import OrderedSet
+from openpower.decoder.isa.all import ISA
+from openpower.decoder.isa.test_caller import Register, run_tst
+from openpower.sv.trans.svp64 import SVP64Asm
+from openpower.consts import SVP64CROffs
from copy import deepcopy
class DecoderTestCase(FHDLTestCase):
from nmigen.back.pysim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
-from soc.decoder.isa.caller import ISACaller
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.decoder.isa.caller import ISACaller, SVP64State
-from soc.decoder.selectable_int import SelectableInt
-from soc.decoder.orderedset import OrderedSet
-from soc.decoder.isa.all import ISA
-from soc.decoder.isa.test_caller import Register, run_tst
-from soc.sv.trans.svp64 import SVP64Asm
-from soc.consts import SVP64CROffs
+from openpower.decoder.isa.caller import ISACaller
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.decoder.isa.caller import ISACaller, SVP64State
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.orderedset import OrderedSet
+from openpower.decoder.isa.all import ISA
+from openpower.decoder.isa.test_caller import Register, run_tst
+from openpower.sv.trans.svp64 import SVP64Asm
+from openpower.consts import SVP64CROffs
from copy import deepcopy
class DecoderTestCase(FHDLTestCase):
from collections import namedtuple
from nmigen import Module, Elaboratable, Signal, Cat, Mux
from nmigen.cli import rtlil
-from soc.decoder.power_enums import (Function, Form, MicrOp,
+from openpower.decoder.power_enums import (Function, Form, MicrOp,
In1Sel, In2Sel, In3Sel, OutSel,
SVEXTRA, SVEtype, SVPtype, # Simple-V
RC, LdstLen, LDSTMode, CryIn,
single_bit_flags, CRInSel,
CROutSel, get_signal_name,
default_values, insns, asmidx)
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SigDecode, SignalBitRange
-from soc.decoder.power_svp64 import SVP64RM
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SigDecode, SignalBitRange
+from openpower.decoder.power_svp64 import SVP64RM
# key data structure in which the POWER decoder is specified,
# in a hierarchical fashion
from nmigen.cli import rtlil
from nmutil.util import sel
-from soc.regfile.regfiles import XERRegs
-
from nmutil.picker import PriorityPicker
from nmutil.iocontrol import RecordObject
from nmutil.extend import exts
-from soc.experiment.mem_types import LDSTException
+from openpower.exceptions import LDSTException
-from soc.decoder.power_svp64_prefix import SVP64PrefixDecoder
-from soc.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra
-from soc.decoder.power_svp64_rm import SVP64RMModeDecode
-from soc.decoder.power_regspec_map import regspec_decode_read
-from soc.decoder.power_regspec_map import regspec_decode_write
-from soc.decoder.power_decoder import create_pdecode
-from soc.decoder.power_enums import (MicrOp, CryIn, Function,
+from openpower.decoder.power_svp64_prefix import SVP64PrefixDecoder
+from openpower.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra
+from openpower.decoder.power_svp64_rm import SVP64RMModeDecode
+from openpower.decoder.power_regspec_map import regspec_decode_read
+from openpower.decoder.power_regspec_map import regspec_decode_write
+from openpower.decoder.power_decoder import create_pdecode
+from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
CRInSel, CROutSel,
LdstLen, In1Sel, In2Sel, In3Sel,
OutSel, SPRfull, SPRreduced,
RC, LDSTMode,
SVEXTRA, SVEtype, SVPtype)
-from soc.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
+from openpower.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
Decode2ToOperand)
-from soc.sv.svp64 import SVP64Rec
-from soc.consts import (MSR, SPEC, EXTRA2, EXTRA3, SVP64P, field,
+from openpower.sv.svp64 import SVP64Rec
+from openpower.consts import (MSR, SPEC, EXTRA2, EXTRA3, SVP64P, field,
SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs)
from soc.regfile.regfiles import FastRegs
-from soc.consts import TT
-from soc.config.state import CoreState
+from openpower.consts import TT
+from openpower.state import CoreState
from soc.regfile.util import spr_to_fast
+from soc.regfile.regfiles import XERRegs
+
def decode_spr_num(spr):
from collections import OrderedDict, namedtuple
-from soc.decoder.power_enums import find_wiki_file
+from openpower.decoder.power_enums import find_wiki_file
class BitRange(OrderedDict):
from collections import OrderedDict
-from soc.decoder.power_fields import DecodeFields, BitRange
+from openpower.decoder.power_fields import DecodeFields, BitRange
from nmigen import Module, Elaboratable, Signal, Cat
from nmigen.cli import rtlil
from copy import deepcopy
import astor
import ast
-from soc.decoder.power_decoder import create_pdecode
+from openpower.decoder.power_decoder import create_pdecode
from nmigen.back.pysim import Simulator, Delay
from nmigen import Module, Signal
-from soc.decoder.pseudo.parser import GardenSnakeCompiler
-from soc.decoder.selectable_int import SelectableInt, selectconcat
-from soc.decoder.isa.caller import GPR, Mem
+from openpower.decoder.pseudo.parser import GardenSnakeCompiler
+from openpower.decoder.selectable_int import SelectableInt, selectconcat
+from openpower.decoder.isa.caller import GPR, Mem
####### Test code #######
print("args", args)
print("-->", " ".join(map(str, args)))
- from soc.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK,
+ from openpower.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK,
trunc_div, trunc_rem)
d = {}
"""
from nmigen import Const
from soc.regfile.regfiles import XERRegs, FastRegs, StateRegs
-from soc.decoder.power_enums import CryIn
+from openpower.decoder.power_enums import CryIn
def regspec_decode_read(e, regfile, name):
# Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
# Funded by NLnet http://nlnet.nl
-from soc.decoder.power_enums import get_csv, find_wiki_dir
+from openpower.decoder.power_enums import get_csv, find_wiki_dir
import os
# identifies register by type
from nmutil.util import sel
-from soc.decoder.power_enums import (SVEXTRA, SVEtype)
-from soc.consts import (SPEC, EXTRA2, EXTRA3, SVP64P, field,
+from openpower.decoder.power_enums import (SVEXTRA, SVEtype)
+from openpower.consts import (SPEC, EXTRA2, EXTRA3, SVP64P, field,
SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs)
from nmigen.cli import rtlil
from nmutil.util import sel
-from soc.consts import SVP64P
+from openpower.consts import SVP64P
# SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
# identifies if an instruction is a SVP64-encoded prefix, and extracts
"""
from nmigen import Elaboratable, Module, Signal, Const
-from soc.decoder.power_enums import (SVP64RMMode, Function, SVPtype,
+from openpower.decoder.power_enums import (SVP64RMMode, Function, SVPtype,
SVP64PredMode, SVP64sat)
-from soc.consts import EXTRA3, SVP64MODE
-from soc.sv.svp64 import SVP64Rec
+from openpower.consts import EXTRA3, SVP64MODE
+from openpower.sv.svp64 import SVP64Rec
from nmutil.util import sel
# Modifications for inclusion in PLY distribution
from copy import copy
from ply import lex
-from soc.decoder.selectable_int import SelectableInt
+from openpower.decoder.selectable_int import SelectableInt
# I implemented INDENT / DEDENT generation as a post-processing filter
import astor
from copy import deepcopy
-from soc.decoder.power_decoder import create_pdecode
-from soc.decoder.pseudo.lexer import IndentLexer
-from soc.decoder.orderedset import OrderedSet
+from openpower.decoder.power_decoder import create_pdecode
+from openpower.decoder.pseudo.lexer import IndentLexer
+from openpower.decoder.orderedset import OrderedSet
# I use the Python AST
#from compiler import ast
import unittest
from copy import copy
-from soc.decoder.power_fields import BitRange
+from openpower.decoder.power_fields import BitRange
from operator import (add, sub, mul, floordiv, truediv, mod, or_, and_, xor,
neg, inv, lshift, rshift)
from nmutil.formaltest import FHDLTestCase
import unittest
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, MicrOp,
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
get_signal_name, get_csv)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.gas import get_assembled_instruction
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.gas import get_assembled_instruction
import random
from nmigen.cli import rtlil
import os
import unittest
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, MicrOp,
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
CRInSel, CROutSel,
OutSel, RC, LdstLen, CryIn,
--- /dev/null
+global bigendian
+bigendian = 0
+
+def set_endian_mode(mode):
+ bigendian = mode
import sys
from io import BytesIO
-from soc.simulator.envcmds import cmds
+from openpower.simulator.envcmds import cmds
filedir = os.path.dirname(os.path.realpath(__file__))
memmap = os.path.join(filedir, "memmap")
from nmigen.back.pysim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, MicrOp,
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
get_signal_name, get_csv)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.simulator.qemu import run_program
-from soc.decoder.isa.all import ISA
-from soc.fu.test.common import TestCase
-from soc.simulator.test_sim import DecoderBase
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.simulator.qemu import run_program
+from openpower.decoder.isa.all import ISA
+from openpower.test.common import TestCase
+from openpower.simulator.test_sim import DecoderBase
from nmigen.back.pysim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, MicrOp,
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
get_signal_name, get_csv)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.simulator.qemu import run_program
-from soc.decoder.isa.all import ISA
-from soc.fu.test.common import TestCase
-from soc.simulator.test_sim import DecoderBase
-from soc.config.endian import bigendian
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.simulator.qemu import run_program
+from openpower.decoder.isa.all import ISA
+from openpower.test.common import TestCase
+from openpower.simulator.test_sim import DecoderBase
+from openpower.endian import bigendian
class HelloTestCases(FHDLTestCase):
from nmigen.back.pysim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, MicrOp,
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
get_signal_name, get_csv)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.simulator.qemu import run_program
-from soc.decoder.isa.all import ISA
-from soc.fu.test.common import TestCase
-from soc.simulator.test_sim import DecoderBase
-from soc.config.endian import bigendian
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.simulator.qemu import run_program
+from openpower.decoder.isa.all import ISA
+from openpower.test.common import TestCase
+from openpower.simulator.test_sim import DecoderBase
+from openpower.endian import bigendian
from nmigen.back.pysim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, MicrOp,
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
get_signal_name, get_csv)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.simulator.qemu import run_program
-from soc.decoder.isa.all import ISA
-from soc.fu.test.common import TestCase
-from soc.simulator.test_sim import DecoderBase
-from soc.config.endian import bigendian
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.simulator.qemu import run_program
+from openpower.decoder.isa.all import ISA
+from openpower.test.common import TestCase
+from openpower.simulator.test_sim import DecoderBase
+from openpower.endian import bigendian
from nmigen.back.pysim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, MicrOp,
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form,
get_signal_name, get_csv)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.simulator.qemu import run_program
-from soc.decoder.isa.all import ISA
-from soc.fu.test.common import TestCase
-from soc.config.endian import bigendian
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.simulator.qemu import run_program
+from openpower.decoder.isa.all import ISA
+from openpower.test.common import TestCase
+from openpower.endian import bigendian
class AttnTestCase(FHDLTestCase):
from nmigen.back.pysim import Simulator, Delay, Settle
from nmutil.formaltest import FHDLTestCase
import unittest
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, MicrOp,
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
get_signal_name, get_csv)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.simulator.qemu import run_program
-from soc.decoder.isa.all import ISA
-from soc.fu.test.common import TestCase
-from soc.simulator.test_sim import DecoderBase
-from soc.config.endian import bigendian
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
+from openpower.simulator.qemu import run_program
+from openpower.decoder.isa.all import ISA
+from openpower.test.common import TestCase
+from openpower.simulator.test_sim import DecoderBase
+from openpower.endian import bigendian #XXX HACK!
class TrapSimTestCases(FHDLTestCase):
from nmutil.iocontrol import RecordObject
from nmigen import Signal
-from soc.sv.svstate import SVSTATERec
+from openpower.sv.svstate import SVSTATERec
class CoreState(RecordObject):
import os, sys
from collections import OrderedDict
-from soc.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
+from openpower.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
SV64P_PID_SIZE, SVP64RMFields,
SVP64RM_EXTRA2_SPEC_SIZE,
SVP64RM_EXTRA3_SPEC_SIZE,
SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE,
SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE,
SVP64RM_ELWIDTH_SIZE)
-from soc.decoder.pseudo.pagereader import ISA
-from soc.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
-from soc.decoder.selectable_int import SelectableInt
-from soc.consts import SVP64MODE
+from openpower.decoder.pseudo.pagereader import ISA
+from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.consts import SVP64MODE
# decode GPR into sv extra
--- /dev/null
+"""
+Bugreports:
+* https://bugs.libre-soc.org/show_bug.cgi?id=361
+"""
+
+import inspect
+import functools
+import types
+
+
+# TODO: make this a util routine (somewhere)
+def mask_extend(x, nbits, repeat):
+ res = 0
+ extended = (1<<repeat)-1
+ for i in range(nbits):
+ if x & (1<<i):
+ res |= extended << (i*repeat)
+ return res
+
+
+class SkipCase(Exception):
+ """Raise this exception to skip a test case.
+
+ Usually you'd use one of the skip_case* decorators.
+
+ For use with TestAccumulatorBase
+ """
+
+
+def _id(obj):
+ """identity function"""
+ return obj
+
+
+def skip_case(reason):
+ """
+ Unconditionally skip a test case.
+
+ Use like:
+ @skip_case("my reason for skipping")
+ def case_abc(self):
+ ...
+ or:
+ @skip_case
+ def case_def(self):
+ ...
+
+ For use with TestAccumulatorBase
+ """
+ def decorator(item):
+ assert not isinstance(item, type), \
+ "can't use skip_case to decorate types"
+
+ @functools.wraps(item)
+ def wrapper(*args, **kwargs):
+ raise SkipCase(reason)
+ return wrapper
+ if isinstance(reason, types.FunctionType):
+ item = reason
+ reason = ""
+ return decorator(item)
+ return decorator
+
+
+def skip_case_if(condition, reason):
+ """
+ Conditionally skip a test case.
+
+ Use like:
+ @skip_case_if(should_i_skip(), "my reason for skipping")
+ def case_abc(self):
+ ...
+
+ For use with TestAccumulatorBase
+ """
+ if condition:
+ return skip_case(reason)
+ return _id
+
+
+class TestAccumulatorBase:
+
+ def __init__(self):
+ self.test_data = []
+ # automatically identifies anything starting with "case_" and
+ # runs it. very similar to unittest auto-identification except
+ # we need a different system
+ for n, v in self.__class__.__dict__.items():
+ if n.startswith("case_") and callable(v):
+ try:
+ v(self)
+ except SkipCase as e:
+ # TODO(programmerjake): translate to final test sending
+ # skip signal to unittest. for now, just print the skipped
+ # reason and ignore
+ print(f"SKIPPED({n}):", str(e))
+
+ def add_case(self, prog, initial_regs=None, initial_sprs=None,
+ initial_cr=0, initial_msr=0,
+ initial_mem=None,
+ initial_svstate=0):
+
+ test_name = inspect.stack()[1][3] # name of caller of this function
+ tc = TestCase(prog, test_name,
+ regs=initial_regs, sprs=initial_sprs, cr=initial_cr,
+ msr=initial_msr,
+ mem=initial_mem,
+ svstate=initial_svstate)
+
+ self.test_data.append(tc)
+
+
+class TestCase:
+ def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
+ msr=0,
+ do_sim=True,
+ extra_break_addr=None,
+ svstate=0):
+
+ self.program = program
+ self.name = name
+
+ if regs is None:
+ regs = [0] * 32
+ if sprs is None:
+ sprs = {}
+ if mem is None:
+ mem = {}
+ self.regs = regs
+ self.sprs = sprs
+ self.cr = cr
+ self.mem = mem
+ self.msr = msr
+ self.do_sim = do_sim
+ self.extra_break_addr = extra_break_addr
+ self.svstate = svstate
+
+
projects / openpower-isa.git / commitdiff