radv: add support for VK_EXT_depth_range_unrestricted

This extension removes the restrictions on minDepth/maxDepth,
minDepthBounds/maxDepthBounds and VkClearDepthStencilValue::depth.

The following CTS tests now pass:

dEQP-VK.glsl.builtin_var.fragdepth.line_list_d32_sfloat_large_depth
dEQP-VK.glsl.builtin_var.fragdepth.point_list_d32_sfloat_large_depth
dEQP-VK.glsl.builtin_var.fragdepth.triangle_list_d32_sfloat_large_depth
dEQP-VK.draw.inverted_depth_ranges.nodepthclamp_depth_range_unrestricted
dEQP-VK.draw.inverted_depth_ranges.depthclamp_depth_range_unrestricted

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_extensions.py b/src/amd/vulkan/radv_extensions.py
index bfee1f76fae93fd6cb617a0bc37ec1f33c5fd905..896cc624592b78e04765be9175ace38beaf93225 100644 (file)
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -86,6 +86,7 @@ EXTENSIONS = [
     Extension('VK_KHR_xlib_surface',                      6, 'VK_USE_PLATFORM_XLIB_KHR'),
     Extension('VK_KHR_multiview',                         1, True),
     Extension('VK_EXT_debug_report',                      9, True),
+    Extension('VK_EXT_depth_range_unrestricted',          1, True),
     Extension('VK_EXT_discard_rectangles',                1, True),
     Extension('VK_EXT_external_memory_dma_buf',           1, True),
     Extension('VK_EXT_external_memory_host',              1, 'device->rad_info.has_userptr'),

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 89c5e69941401a338e43e57463f991ed240eb451..dd5baec117355596f3b419d8e2c67564407b902c 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2198,9 +2198,11 @@ radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
        const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
        RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
        struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
+       struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
        struct radv_render_pass_attachment *attachment = NULL;
        uint32_t db_depth_control = 0, db_stencil_control = 0;
        uint32_t db_render_control = 0, db_render_override2 = 0;
+       uint32_t db_render_override = 0;
 
        if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
                attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
@@ -2242,10 +2244,30 @@ radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
                db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
        }
 
+       db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
+                             S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
+
+       if (pipeline->device->enabled_extensions.EXT_depth_range_unrestricted &&
+           !pCreateInfo->pRasterizationState->depthClampEnable &&
+           ps->info.info.ps.writes_z) {
+               /* From VK_EXT_depth_range_unrestricted spec:
+                *
+                * "The behavior described in Primitive Clipping still applies.
+                *  If depth clamping is disabled the depth values are still
+                *  clipped to 0 ≤ zc ≤ wc before the viewport transform. If
+                *  depth clamping is enabled the above equation is ignored and
+                *  the depth values are instead clamped to the VkViewport
+                *  minDepth and maxDepth values, which in the case of this
+                *  extension can be outside of the 0.0 to 1.0 range."
+                */
+               db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
+       }
+
        radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
        radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
 
        radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
+       radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
        radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
 }