In ARC assembler, we accept case insensitive mnemonics, but this was
not the case for extension instruction, fix it and add a test.
gas/
Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (tokenize_extinsn): Convert to lower case the
name of extension instructions.
* testsuite/gas/arc/textinsn_case.d: New file.
* testsuite/gas/arc/textinsn_case.s: Likewise.
+2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/tc-arc.c (tokenize_extinsn): Convert to lower case the
+ name of extension instructions.
+ * testsuite/gas/arc/textinsn_case.d: New file.
+ * testsuite/gas/arc/textinsn_case.s: Likewise.
+
2018-07-22 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_vex_prefix): Determine vector
insn_name = xstrdup (p);
restore_line_pointer (c);
+ /* Convert to lower case. */
+ for (p = insn_name; *p; ++p)
+ *p = TOLOWER (*p);
+
/* 2nd: get major opcode. */
if (*input_line_pointer != ',')
{
--- /dev/null
+#objdump: -d
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <test>:
+\s+[0-9a-f]+:\s+3a25 00c1\s+aes_qroundf\s+r1,r2,r3
--- /dev/null
+ .cpu em
+ .extInstruction aes_qRoundF, 7, 0x25, SUFFIX_COND, SYNTAX_3OP
+
+ .text
+test:
+ aes_qRoundF r1,r2,r3