cpu: Fix Checker register index use
authorAndreas Hansson <andreas.hansson@arm.com>
Fri, 15 Nov 2013 08:47:10 +0000 (03:47 -0500)
committerAndreas Hansson <andreas.hansson@arm.com>
Fri, 15 Nov 2013 08:47:10 +0000 (03:47 -0500)
This patch fixes an issue in the checker CPU register indexing. The
code will not even compile using LTO as deep inlining causes the used
index to be outside the array bounds.

src/cpu/checker/cpu_impl.hh

index 73bacdc05f44e038a728adb93d97c47226eedd95..23e9c103e2885c99b89c511bf3028ff1de4a1b01 100644 (file)
@@ -607,10 +607,10 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
             thread->setIntReg(idx, mismatch_val);
             break;
           case FloatRegClass:
-            thread->setFloatRegBits(idx, mismatch_val);
+            thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, mismatch_val);
             break;
           case CCRegClass:
-            thread->setCCReg(idx, mismatch_val);
+            thread->setCCReg(idx - TheISA::CC_Reg_Base, mismatch_val);
             break;
           case MiscRegClass:
             thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
@@ -628,10 +628,10 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
             thread->setIntReg(idx, res);
             break;
           case FloatRegClass:
-            thread->setFloatRegBits(idx, res);
+            thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, res);
             break;
           case CCRegClass:
-            thread->setCCReg(idx, res);
+            thread->setCCReg(idx - TheISA::CC_Reg_Base, res);
             break;
           case MiscRegClass:
             // Try to get the proper misc register index for ARM here...