fastmodel: add interface to update system counter freq

This CL set the cntfrq and system counter frequency at once from python
script. This aligns the fastmodel implementation to other part of gem5
CPU.

Change-Id: I78c9a7be801112844c03d2669a94d57015136d16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40278
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index 1decdf97ca57fee74ea1bf503578d4757722f3f8..11e8c985c1392c636b46c1140a64b01e9463ade7 100644 (file)
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -41,6 +41,8 @@ CortexA76::initState()
 {
     for (auto *tc : threadContexts)
         tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0, params().cntfrq);
+
+    evs_base_cpu->setSysCounterFrq(cluster->params().cntfrq);
 }
 
 void

diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc b/src/arch/arm/fastmodel/CortexA76/evs.cc
index 29d8877f6757f60743571aae6008b415d873b04a..02ccaaba3d42f3ca92cfb648b6380ef5c837e4ff 100644 (file)
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -44,6 +44,13 @@ ScxEvsCortexA76<Types>::setClkPeriod(Tick clk_period)
     clockRateControl->set_mul_div(SimClock::Int::s, clk_period);
 }
 
+template <class Types>
+void
+ScxEvsCortexA76<Types>::setSysCounterFrq(uint64_t sys_counter_frq)
+{
+    periphClockRateControl->set_mul_div(sys_counter_frq, 1);
+}
+
 template <class Types>
 void
 ScxEvsCortexA76<Types>::setCluster(SimObject *cluster)
@@ -86,6 +93,7 @@ ScxEvsCortexA76<Types>::ScxEvsCortexA76(
     }
 
     clockRateControl.bind(this->clock_rate_s);
+    periphClockRateControl.bind(this->periph_clock_rate_s);
 }
 
 template <class Types>

diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh b/src/arch/arm/fastmodel/CortexA76/evs.hh
index fa12ff82175d6a2906b50f441793a213e98cccd1..4aa43b6b2552c1395008f7c82252a5530160e915 100644 (file)
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -63,6 +63,7 @@ class ScxEvsCortexA76 : public Types::Base, public Iris::BaseCpuEvs
     SC_HAS_PROCESS(ScxEvsCortexA76);
 
     ClockRateControlInitiatorSocket clockRateControl;
+    ClockRateControlInitiatorSocket periphClockRateControl;
 
     typedef sc_gem5::TlmTargetBaseWrapper<
         64, svp_gicv3_comms::gicv3_comms_fw_if,
@@ -105,6 +106,8 @@ class ScxEvsCortexA76 : public Types::Base, public Iris::BaseCpuEvs
 
     void setClkPeriod(Tick clk_period) override;
 
+    void setSysCounterFrq(uint64_t sys_counter_frq) override;
+
     void setCluster(SimObject *cluster) override;
 };
 

diff --git a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
index 1968931becbf34cde71f801e4ad81ac326d7d1bb..04dae413100bceaa1cb87a812569375acb630038 100644 (file)
--- a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
@@ -35,7 +35,7 @@ component CortexA76x1
         // Clocks.
         clock1Hz : MasterClock();
         clockDiv : ClockDivider();
-        clockDivPeriph : ClockDivider(mul=0x01800000);
+        clockDivPeriph : ClockDivider();
     }
 
     connection
@@ -77,6 +77,13 @@ component CortexA76x1
             clockDiv.rate.set64(mul, div);
         }
     }
+    slave port<ExportedClockRateControl> periph_clock_rate_s
+    {
+        behavior set_mul_div(uint64_t mul, uint64_t div)
+        {
+            clockDivPeriph.rate.set64(mul, div);
+        }
+    }
     slave port<GICv3Comms> redistributor[1];
 
     // External ports for CPU-to-GIC signals

diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
index e0f7a933036ba4ec5a72fde9d6ba7d2ba4dcb9bd..0279140552deac1bea9eb2785dbf0dcae82a4555 100644 (file)
--- a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
@@ -35,7 +35,7 @@ component CortexA76x2
         // Clocks.
         clock1Hz : MasterClock();
         clockDiv : ClockDivider();
-        clockDivPeriph : ClockDivider(mul=0x01800000);
+        clockDivPeriph : ClockDivider();
     }
 
     connection
@@ -77,6 +77,13 @@ component CortexA76x2
             clockDiv.rate.set64(mul, div);
         }
     }
+    slave port<ExportedClockRateControl> periph_clock_rate_s
+    {
+        behavior set_mul_div(uint64_t mul, uint64_t div)
+        {
+            clockDivPeriph.rate.set64(mul, div);
+        }
+    }
     slave port<GICv3Comms> redistributor[2];
 
     // External ports for CPU-to-GIC signals

diff --git a/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa b/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
index 9ce9027e45e86d724ede6dabe9dbcfeeb2cc91e3..b18b10239c1ab81a570b5faf86dfc11a12b96678 100644 (file)
--- a/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
@@ -35,7 +35,7 @@ component CortexA76x3
         // Clocks.
         clock1Hz : MasterClock();
         clockDiv : ClockDivider();
-        clockDivPeriph : ClockDivider(mul=0x01800000);
+        clockDivPeriph : ClockDivider();
     }
 
     connection
@@ -77,6 +77,13 @@ component CortexA76x3
             clockDiv.rate.set64(mul, div);
         }
     }
+    slave port<ExportedClockRateControl> periph_clock_rate_s
+    {
+        behavior set_mul_div(uint64_t mul, uint64_t div)
+        {
+            clockDivPeriph.rate.set64(mul, div);
+        }
+    }
     slave port<GICv3Comms> redistributor[3];
 
     // External ports for CPU-to-GIC signals

diff --git a/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa b/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
index e4b79ce1b37af72326106d45003ce20745128f3c..c7f1cb2ecd44782c35825054c61fecdf488dc332 100644 (file)
--- a/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
@@ -35,7 +35,7 @@ component CortexA76x4
         // Clocks.
         clock1Hz : MasterClock();
         clockDiv : ClockDivider();
-        clockDivPeriph : ClockDivider(mul=0x01800000);
+        clockDivPeriph : ClockDivider();
     }
 
     connection
@@ -77,6 +77,13 @@ component CortexA76x4
             clockDiv.rate.set64(mul, div);
         }
     }
+    slave port<ExportedClockRateControl> periph_clock_rate_s
+    {
+        behavior set_mul_div(uint64_t mul, uint64_t div)
+        {
+            clockDivPeriph.rate.set64(mul, div);
+        }
+    }
     slave port<GICv3Comms> redistributor[4];
 
     // External ports for CPU-to-GIC signals

diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc b/src/arch/arm/fastmodel/CortexR52/evs.cc
index cd84aa62e796ec3df435e487e5d2576d93f93a7f..f4ce61e30849469de7b458cea0904efc431d3843 100644 (file)
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -43,6 +43,13 @@ ScxEvsCortexR52<Types>::setClkPeriod(Tick clk_period)
     clockRateControl->set_mul_div(SimClock::Int::s, clk_period);
 }
 
+template <class Types>
+void
+ScxEvsCortexR52<Types>::setSysCounterFrq(uint64_t sys_counter_frq)
+{
+    panic("Not implemented for R52.");
+}
+
 template <class Types>
 void
 ScxEvsCortexR52<Types>::setCluster(SimObject *cluster)

diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh b/src/arch/arm/fastmodel/CortexR52/evs.hh
index e03a32200be14523afb48800218609251177a867..3fa5980a84d5d92b862d1dc63c0e929c56e06d91 100644 (file)
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -140,6 +140,8 @@ class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs
 
     void setClkPeriod(Tick clk_period) override;
 
+    void setSysCounterFrq(uint64_t sys_counter_frq) override;
+
     void setCluster(SimObject *cluster) override;
 };
 

diff --git a/src/arch/arm/fastmodel/iris/cpu.hh b/src/arch/arm/fastmodel/iris/cpu.hh
index c5dd19f24312a8ea2ebcc49c764cc7590e325ffd..369f0d8da87164e624a85527cfefc5e3e8937b50 100644 (file)
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -44,6 +44,7 @@ class BaseCpuEvs
   public:
     virtual void sendFunc(PacketPtr pkt) = 0;
     virtual void setClkPeriod(Tick clk_period) = 0;
+    virtual void setSysCounterFrq(uint64_t sys_counter_frq) = 0;
     virtual void setCluster(SimObject *cluster) = 0;
 };