Fixed upto handling in verilog back-end

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index caa668c33a624fa63b4716099a98403da67603af..705d74aa1bd69e980328f389ea5838a1557275cc 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -141,6 +141,9 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
        if (sig.size() != chunk.wire->width) {
                if (sig.size() == 1)
                        reg_name += stringf("[%d]", chunk.wire->start_offset +  chunk.offset);
+               else if (chunk.wire->upto)
+                       reg_name += stringf("[%d:%d]", (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset,
+                                       (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset);
                else
                        reg_name += stringf("[%d:%d]", chunk.wire->start_offset +  chunk.offset + chunk.width - 1,
                                        chunk.wire->start_offset +  chunk.offset);