all_isa_list = [ ]
Export('all_isa_list')
-# Define the universe of supported CPU models
-all_cpu_list = [ ]
-default_cpus = [ ]
-Export('all_cpu_list', 'default_cpus')
+class CpuModel(object):
+ '''The CpuModel class encapsulates everything the ISA parser needs to
+ know about a particular CPU model.'''
+
+ # Dict of available CPU model objects. Accessible as CpuModel.dict.
+ dict = {}
+ list = []
+ defaults = []
+
+ # Constructor. Automatically adds models to CpuModel.dict.
+ def __init__(self, name, filename, includes, strings, default=False):
+ self.name = name # name of model
+ self.filename = filename # filename for output exec code
+ self.includes = includes # include files needed in exec file
+ # The 'strings' dict holds all the per-CPU symbols we can
+ # substitute into templates etc.
+ self.strings = strings
+
+ # This cpu is enabled by default
+ self.default = default
+
+ # Add self to dict
+ if name in CpuModel.dict:
+ raise AttributeError, "CpuModel '%s' already registered" % name
+ CpuModel.dict[name] = self
+ CpuModel.list.append(name)
+
+Export('CpuModel')
# Sticky variables get saved in the variables file so they persist from
# one invocation to the next (unless overridden, in which case the new
SConscript(joinpath(root, 'SConsopts'))
all_isa_list.sort()
-all_cpu_list.sort()
-default_cpus.sort()
sticky_vars.AddVariables(
EnumVariable('TARGET_ISA', 'Target ISA', 'alpha', all_isa_list),
BoolVariable('FULL_SYSTEM', 'Full-system support', False),
- ListVariable('CPU_MODELS', 'CPU models', default_cpus, all_cpu_list),
+ ListVariable('CPU_MODELS', 'CPU models',
+ sorted(n for n,m in CpuModel.dict.iteritems() if m.default),
+ sorted(CpuModel.list)),
BoolVariable('NO_FAST_ALLOC', 'Disable fast object allocator', False),
BoolVariable('FAST_ALLOC_DEBUG', 'Enable fast object allocator debugging',
False),
# output from the ISA description (*.isa) files.
#
-#
-# Grab the CPU Model information
-#
-
-# Convert to File node to fix path
-cpu_models_file = File('../cpu/cpu_models.py')
-
-# This sucks in the defintions of the CpuModel objects.
-execfile(cpu_models_file.srcnode().abspath)
-
# The emitter patches up the sources & targets to include the
# autogenerated files as targets and isa parser itself as a source.
def isa_desc_emitter(target, source, env):
#
#################################################################
-# CPU model-specific data is contained in cpu_models.py
-# Convert to SCons File node to get path handling
-models_db = File('cpu_models.py')
-# slurp in contents of file
-execfile(models_db.srcnode().abspath)
-
# Template for execute() signature.
exec_sig_template = '''
virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
+ ', '.join(temp_cpu_list)
# Add command to generate header to environment.
-env.Command('static_inst_exec_sigs.hh', models_db,
+env.Command('static_inst_exec_sigs.hh', (),
Action(gen_cpu_exec_signatures, gen_sigs_string,
varlist = temp_cpu_list))
--- /dev/null
+# -*- mode:python -*-
+
+# Copyright (c) 2003-2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+Import('*')
+
+CpuModel('CheckerCPU', 'checker_cpu_exec.cc',
+ '#include "cpu/checker/cpu.hh"',
+ { 'CPU_exec_context': 'CheckerCPU' })
+++ /dev/null
-# Copyright (c) 2003-2006 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt
-
-import os
-import os.path
-import sys
-
-################
-# CpuModel class
-#
-# The CpuModel class encapsulates everything the ISA parser needs to
-# know about a particular CPU model.
-
-class CpuModel:
- # Dict of available CPU model objects. Accessible as CpuModel.dict.
- dict = {}
-
- # Constructor. Automatically adds models to CpuModel.dict.
- def __init__(self, name, filename, includes, strings):
- self.name = name
- self.filename = filename # filename for output exec code
- self.includes = includes # include files needed in exec file
- # The 'strings' dict holds all the per-CPU symbols we can
- # substitute into templates etc.
- self.strings = strings
- # Add self to dict
- CpuModel.dict[name] = self
-
-#
-# Define CPU models.
-#
-# Parameters are:
-# - name of model
-# - filename for generated ISA execution file
-# - includes needed for generated ISA execution file
-# - substitution strings for ISA description templates
-#
-
-CpuModel('AtomicSimpleCPU', 'atomic_simple_cpu_exec.cc',
- '#include "cpu/simple/atomic.hh"',
- { 'CPU_exec_context': 'AtomicSimpleCPU' })
-CpuModel('TimingSimpleCPU', 'timing_simple_cpu_exec.cc',
- '#include "cpu/simple/timing.hh"',
- { 'CPU_exec_context': 'TimingSimpleCPU' })
-CpuModel('FullCPU', 'full_cpu_exec.cc',
- '#include "encumbered/cpu/full/dyn_inst.hh"',
- { 'CPU_exec_context': 'DynInst' })
-CpuModel('OzoneSimpleCPU', 'ozone_simple_exec.cc',
- '#include "cpu/ozone/dyn_inst.hh"',
- { 'CPU_exec_context': 'OzoneDynInst<SimpleImpl>' })
-CpuModel('OzoneCPU', 'ozone_exec.cc',
- '#include "cpu/ozone/dyn_inst.hh"',
- { 'CPU_exec_context': 'OzoneDynInst<OzoneImpl>' })
-CpuModel('CheckerCPU', 'checker_cpu_exec.cc',
- '#include "cpu/checker/cpu.hh"',
- { 'CPU_exec_context': 'CheckerCPU' })
-CpuModel('O3CPU', 'o3_cpu_exec.cc',
- '#include "cpu/o3/isa_specific.hh"',
- { 'CPU_exec_context': 'O3DynInst' })
-CpuModel('InOrderCPU', 'inorder_cpu_exec.cc',
- '#include "cpu/inorder/inorder_dyn_inst.hh"',
- { 'CPU_exec_context': 'InOrderDynInst' })
Import('*')
-all_cpu_list.append('InOrderCPU')
-default_cpus.append('InOrderCPU')
+CpuModel('InOrderCPU', 'inorder_cpu_exec.cc',
+ '#include "cpu/inorder/inorder_dyn_inst.hh"',
+ { 'CPU_exec_context': 'InOrderDynInst' },
+ default=True)
Import('*')
-all_cpu_list.append('O3CPU')
-default_cpus.append('O3CPU')
+CpuModel('O3CPU', 'o3_cpu_exec.cc',
+ '#include "cpu/o3/isa_specific.hh"',
+ { 'CPU_exec_context': 'O3DynInst' },
+ default=True)
Import('*')
-all_cpu_list.append('OzoneCPU')
+CpuModel('OzoneSimpleCPU', 'ozone_simple_exec.cc',
+ '#include "cpu/ozone/dyn_inst.hh"',
+ { 'CPU_exec_context': 'OzoneDynInst<SimpleImpl>' })
+CpuModel('OzoneCPU', 'ozone_exec.cc',
+ '#include "cpu/ozone/dyn_inst.hh"',
+ { 'CPU_exec_context': 'OzoneDynInst<OzoneImpl>' })
+
Import('*')
-all_cpu_list.extend(('AtomicSimpleCPU', 'TimingSimpleCPU'))
-default_cpus.extend(('AtomicSimpleCPU', 'TimingSimpleCPU'))
+CpuModel('AtomicSimpleCPU', 'atomic_simple_cpu_exec.cc',
+ '#include "cpu/simple/atomic.hh"',
+ { 'CPU_exec_context': 'AtomicSimpleCPU' },
+ default=True)
+CpuModel('TimingSimpleCPU', 'timing_simple_cpu_exec.cc',
+ '#include "cpu/simple/timing.hh"',
+ { 'CPU_exec_context': 'TimingSimpleCPU' },
+ default=True)
projects / gem5.git / commitdiff