ppc/svp64: support svstep instructions

https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/isa/simplev/

diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index cd4dd658ce5fef5321358432967564cb9b780efa..d4d06d587e53f8ff4b573949a4e5586933fcf99d 100644 (file)
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -155,3 +155,4 @@ run_dump_test "pr27676"
 run_dump_test "raw"
 
 run_dump_test "setvl"
+run_dump_test "svstep"

diff --git a/gas/testsuite/gas/ppc/svstep.d b/gas/testsuite/gas/ppc/svstep.d
new file mode 100644 (file)
index 0000000..5ce2c25
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svstep.d
@@ -0,0 +1,13 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*:    (27 00 00 58|58 00 00 27)       svstep. r0,1,0
+.*:    (26 00 00 58|58 00 00 26)       svstep  r0,1,0
+.*:    (26 00 e0 5b|5b e0 00 26)       svstep  r31,1,0
+.*:    (26 7e 00 58|58 00 7e 26)       svstep  r0,64,0
+.*:    (66 00 00 58|58 00 00 66)       svstep  r0,1,1

diff --git a/gas/testsuite/gas/ppc/svstep.s b/gas/testsuite/gas/ppc/svstep.s
new file mode 100644 (file)
index 0000000..b073b2e
--- /dev/null
+++ b/gas/testsuite/gas/ppc/svstep.s
@@ -0,0 +1,5 @@
+svstep. 0,1,0
+svstep 0,1,0
+svstep 31,1,0
+svstep 0,64,0
+svstep 0,1,1

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 90f813a280739ef8e04cdd6bbe2989d7f9accdad..60a038aa4089fb33474a76213a99905e24bd9155 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -6783,6 +6783,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"rlmi",       M(22,0),        M_MASK,      M601,      PPCVLE,         {RA, RS, RB, MBE, ME}},
 {"rlmi.",      M(22,1),        M_MASK,      M601,      PPCVLE,         {RA, RS, RB, MBE, ME}},
 
+{"svstep",     SVL(22,19,0),   SVL_MASK,       SVP64,  PPCVLE, {RT, SVi, vf}},
+{"svstep.",    SVL(22,19,1),   SVL_MASK,       SVP64,  PPCVLE, {RT, SVi, vf}},
+
 {"setvl",      SVL(22,27,0),   SVL_MASK,       SVP64,  PPCVLE, {RT, RA, SVi, vf, vs, ms}},
 {"setvl.",     SVL(22,27,1),   SVL_MASK,       SVP64,  PPCVLE, {RT, RA, SVi, vf, vs, ms}},