(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index a93d29390a24980a1b3e82ce81e69708446333c1..f27479779180ec88f4b79c67f9892f7f3623b583 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -257,7 +257,11 @@ Vector instructions in RISC-V as there are in the RV64GC Scalar base.
 The question then becomes: with all the duplication of arithmetic
 operations just to make the registers scalar or vector, why not
 leverage the *existing* Scalar ISA with some sort of "context"
-or prefix that augments its behaviour?  Then, the Instruction Decode
+or prefix that augments its behaviour? Make "Scalar instruction"
+synonymous with "Scalar instruction" and through contextual
+augmentation the Scalar ISA *becomes* the Vector ISA.
+Then, by not having to have any Vector instructions at all,
+the Instruction Decode
 phase is greatly simplified, reducing design complexity and leaving
 plenty of headroom for further expansion.