Merge remote-tracking branch 'origin/read_aiger' into xaig

diff --cc backends/verilog/verilog_backend.cc
Simple merge

diff --cc frontends/aiger/aigerparse.cc
index cc4abe184010e305e7e21e60a199edb022197c43,7df28fe87487964420db48d2453c73267a40835b..56bffcf3829920a2ae499c07a57551b6f0793985
--- 1/frontends/aiger/aigerparse.cc
--- 2/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@@ -414,19 -229,12 +412,14 @@@ void AigerReader::parse_aiger_ascii(boo
              log_error("Line %u cannot be interpreted as an AND!\n", line_count);
  
          log_debug("%d %d %d is an AND\n", l1, l2, l3);
 -        log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
 -        RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
 -        RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
 -        RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
 -        module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
 +        if (create_and) {
 +            log_assert(!(l1 & 1));
 +            RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
 +            RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
 +            RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
- 
-             RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
-             and_cell->setPort("\\A", i1_wire);
-             and_cell->setPort("\\B", i2_wire);
-             and_cell->setPort("\\Y", o_wire);
++            module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
 +        }
      }
-     std::getline(f, line); // Ignore up to start of next line
  }
  
  static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)