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freedreno/a3xx: fix SP_FS_MRT_REG.HALF_PRECISION
authorRob Clark <robdclark@chromium.org>
Fri, 25 Oct 2019 20:56:30 +0000 (13:56 -0700)
committerRob Clark <robdclark@gmail.com>
Sat, 9 Nov 2019 02:49:15 +0000 (02:49 +0000)
We should really be setting this based on the actual output register
type.

Signed-off-by: Rob Clark <robdclark@chromium.org>
src/gallium/drivers/freedreno/a3xx/fd3_program.c patch | blob | history

diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_program.c b/src/gallium/drivers/freedreno/a3xx/fd3_program.c
index a9d4fd0784f594d5886d6f3956351243a8747f2d..893518935c8abc21f565c2b07993ebd9065bf4ac 100644 (file)
--- a/src/gallium/drivers/freedreno/a3xx/fd3_program.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_program.c
@@ -321,7 +321,7 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
        OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
        for (i = 0; i < 4; i++) {
                uint32_t mrt_reg = A3XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
-                       COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
+                       COND(color_regid[i] & HALF_REG_ID, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
 
                if (i < nr) {
                        enum pipe_format fmt = pipe_surface_format(bufs[i]);