Merge python and x86 changes with cache branch

--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233

diff --cc src/arch/sparc/tlb.cc
Simple merge

diff --cc src/cpu/base.cc
Simple merge

diff --cc src/cpu/memtest/memtest.cc
Simple merge

diff --cc src/cpu/o3/cpu.cc
Simple merge

diff --cc src/cpu/o3/inst_queue_impl.hh
Simple merge

diff --cc src/cpu/simple/atomic.cc
Simple merge

diff --cc src/cpu/simple/timing.cc
Simple merge

diff --cc src/cpu/trace/opt_cpu.cc
Simple merge

diff --cc src/cpu/trace/trace_cpu.cc
index 32ed6c7d7bd3ca77d359e1aff1a2fad30a37d3e5,a3164221b4d2f58ca027af8d841c88e553b1c385..e5739b2ce4238ba5b24abff5651751d94b422ce5
--- 1/src/cpu/trace/trace_cpu.cc
--- 2/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@@ -148,30 -148,13 +148,13 @@@ TraceCPU::TickEvent::process(
  const char *
  TraceCPU::TickEvent::description()
  {
 -    return "TraceCPU tick event";
 +    return "TraceCPU tick";
  }
  
- 
- 
- BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
- 
-     SimObjectParam<BaseMem *> icache;
-     SimObjectParam<BaseMem *> dcache;
-     SimObjectParam<MemTraceReader *> data_trace;
- 
- END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
- 
- BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU)
- 
-     INIT_PARAM_DFLT(icache, "instruction cache", NULL),
-     INIT_PARAM_DFLT(dcache, "data cache", NULL),
-     INIT_PARAM_DFLT(data_trace, "data trace", NULL)
- 
- END_INIT_SIM_OBJECT_PARAMS(TraceCPU)
- 
- CREATE_SIM_OBJECT(TraceCPU)
+ TraceCPU *
+ TraceCPUParams::create()
  {
-     return new TraceCPU(getInstanceName(),
+     return new TraceCPU(name,
                          (icache) ? icache->getInterface() : NULL,
                          (dcache) ? dcache->getInterface() : NULL,
                          data_trace);

diff --cc src/dev/alpha/console.cc
Simple merge

diff --cc src/dev/alpha/tsunami_cchip.cc
Simple merge

diff --cc src/dev/alpha/tsunami_io.cc
Simple merge

diff --cc src/dev/alpha/tsunami_pchip.cc
Simple merge

diff --cc src/dev/i8254xGBe.cc
Simple merge

diff --cc src/dev/ide_ctrl.cc
Simple merge

diff --cc src/dev/io_device.cc
Simple merge

diff --cc src/dev/isa_fake.cc
index 5cd0afb368785288fa97ba99f8de39f08c1c0dbc,8e11e607bf6e2e9385df31d46a93330392cc4dab..9d62aecbaa6bca3222d7ea33694938bde108442f
--- 1/src/dev/isa_fake.cc
--- 2/src/dev/isa_fake.cc
+++ b/src/dev/isa_fake.cc
@@@ -56,14 -55,15 +55,14 @@@ IsaFake::IsaFake(Params *p
  Tick
  IsaFake::read(PacketPtr pkt)
  {
 -    assert(pkt->result == Packet::Unknown);
  
-     if (params()->warnAccess != "")
+     if (params()->warn_access != "")
          warn("Device %s accessed by read to address %#x size=%d\n",
                  name(), pkt->getAddr(), pkt->getSize());
-     if (params()->retBadAddr) {
+     if (params()->ret_bad_addr) {
          DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
                  pkt->getAddr(), pkt->getSize());
 -        pkt->result = Packet::BadAddress;
 +        pkt->setBadAddress();
      } else {
          assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
          DPRINTF(Tsunami, "read  va=%#x size=%d\n",
@@@ -113,10 -113,10 +112,10 @@@ IsaFake::write(PacketPtr pkt
          warn("Device %s accessed by write to address %#x size=%d data=%#x\n",
                  name(), pkt->getAddr(), pkt->getSize(), data);
      }
-     if (params()->retBadAddr) {
+     if (params()->ret_bad_addr) {
          DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
                  pkt->getAddr(), pkt->getSize());
 -        pkt->result = Packet::BadAddress;
 +        pkt->setBadAddress();
      } else {
          DPRINTF(Tsunami, "write - va=%#x size=%d \n",
                  pkt->getAddr(), pkt->getSize());

diff --cc src/dev/ns_gige.cc
Simple merge

diff --cc src/dev/pciconfigall.cc
Simple merge

diff --cc src/dev/pcidev.cc
Simple merge

diff --cc src/dev/sparc/dtod.cc
Simple merge

diff --cc src/dev/sparc/iob.cc
Simple merge

diff --cc src/dev/sparc/mm_disk.cc
Simple merge

diff --cc src/dev/uart8250.cc
Simple merge

diff --cc src/mem/bridge.cc
index d6adb05d13eb71fd2c31393b184b3d5f2f110bf1,f4e3dc8b3988fcd0dc601939c2aed46018e21892..6cfa5a2ac3a2de7f84fc10720896f9e7fc69af1c
--- 1/src/mem/bridge.cc
--- 2/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@@ -355,54 -365,10 +355,12 @@@ Bridge::BridgePort::getDeviceAddressRan
                                             bool &snoop)
  {
      otherPort->getPeerAddressRanges(resp, snoop);
 +    // we don't allow snooping across bridges
 +    snoop = false;
  }
  
- BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bridge)
- 
-    Param<int> req_size_a;
-    Param<int> req_size_b;
-    Param<int> resp_size_a;
-    Param<int> resp_size_b;
-    Param<Tick> delay;
-    Param<Tick> nack_delay;
-    Param<bool> write_ack;
-    Param<bool> fix_partial_write_a;
-    Param<bool> fix_partial_write_b;
- 
- END_DECLARE_SIM_OBJECT_PARAMS(Bridge)
- 
- BEGIN_INIT_SIM_OBJECT_PARAMS(Bridge)
- 
-     INIT_PARAM(req_size_a, "The size of the queue for requests coming into side a"),
-     INIT_PARAM(req_size_b, "The size of the queue for requests coming into side b"),
-     INIT_PARAM(resp_size_a, "The size of the queue for responses coming into side a"),
-     INIT_PARAM(resp_size_b, "The size of the queue for responses coming into side b"),
-     INIT_PARAM(delay, "The miminum delay to cross this bridge"),
-     INIT_PARAM(nack_delay, "The minimum delay to nack a packet"),
-     INIT_PARAM(write_ack, "Acknowledge any writes that are received."),
-     INIT_PARAM(fix_partial_write_a, "Fixup any partial block writes that are received"),
-     INIT_PARAM(fix_partial_write_b, "Fixup any partial block writes that are received")
- 
- END_INIT_SIM_OBJECT_PARAMS(Bridge)
- 
- CREATE_SIM_OBJECT(Bridge)
+ Bridge *
+ BridgeParams::create()
  {
-     Bridge::Params *p = new Bridge::Params;
-     p->name = getInstanceName();
-     p->req_size_a = req_size_a;
-     p->req_size_b = req_size_b;
-     p->resp_size_a = resp_size_a;
-     p->resp_size_b = resp_size_b;
-     p->delay = delay;
-     p->nack_delay = nack_delay;
-     p->write_ack = write_ack;
-     p->fix_partial_write_a = fix_partial_write_a;
-     p->fix_partial_write_b = fix_partial_write_b;
-     return new Bridge(p);
+     return new Bridge(this);
  }
- 
- REGISTER_SIM_OBJECT("Bridge", Bridge)
- 
- 

diff --cc src/mem/bridge.hh
Simple merge

diff --cc src/mem/bus.cc
Simple merge

diff --cc src/mem/cache/cache_builder.cc
index 65418b68d9994a37fba18053de03ceab98431821,d4b1787e0c062e536bcf378ff862cab1a17ff0e6..4c9592a1ba23e3c53c00ebe07c9d50238cd6a78a
--- 1/src/mem/cache/cache_builder.cc
--- 2/src/mem/cache/cache_builder.cc
+++ b/src/mem/cache/cache_builder.cc
@@@ -41,8 -42,8 +42,7 @@@
  #include "mem/cache/base_cache.hh"
  #include "mem/cache/cache.hh"
  #include "mem/bus.hh"
- #include "sim/builder.hh"
 -#include "mem/cache/coherence/coherence_protocol.hh"
+ #include "params/BaseCache.hh"
  
  // Tag Templates
  #if defined(USE_CACHE_LRU)
@@@ -80,111 -93,31 +80,27 @@@
  using namespace std;
  using namespace TheISA;
  
- #ifndef DOXYGEN_SHOULD_SKIP_THIS
- 
- BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
- 
-     Param<int> size;
-     Param<int> assoc;
-     Param<int> block_size;
-     Param<int> latency;
-     Param<int> mshrs;
-     Param<int> tgts_per_mshr;
-     Param<int> write_buffers;
-     Param<bool> prioritizeRequests;
-     Param<Addr> trace_addr;
-     Param<int> hash_delay;
- #if defined(USE_CACHE_IIC)
-     SimObjectParam<Repl *> repl;
- #endif
-     Param<int> subblock_size;
-     Param<Counter> max_miss_count;
-     VectorParam<Range<Addr> > addr_range;
- //    SimObjectParam<MemTraceWriter *> mem_trace;
-     Param<bool> split;
-     Param<int> split_size;
-     Param<bool> lifo;
-     Param<bool> two_queue;
-     Param<bool> prefetch_miss;
-     Param<bool> prefetch_access;
-     Param<int> prefetcher_size;
-     Param<bool> prefetch_past_page;
-     Param<bool> prefetch_serial_squash;
-     Param<Tick> prefetch_latency;
-     Param<int> prefetch_degree;
-     Param<string> prefetch_policy;
-     Param<bool> prefetch_cache_check_push;
-     Param<bool> prefetch_use_cpu_id;
-     Param<bool> prefetch_data_accesses_only;
- 
- END_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
- 
- 
- BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
- 
-     INIT_PARAM(size, "capacity in bytes"),
-     INIT_PARAM(assoc, "associativity"),
-     INIT_PARAM(block_size, "block size in bytes"),
-     INIT_PARAM(latency, "hit latency in CPU cycles"),
-     INIT_PARAM(mshrs, "number of MSHRs (max outstanding requests)"),
-     INIT_PARAM(tgts_per_mshr, "max number of accesses per MSHR"),
-     INIT_PARAM_DFLT(write_buffers, "number of write buffers", 8),
-     INIT_PARAM_DFLT(prioritizeRequests, "always service demand misses first",
-                     false),
-     INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
- 
-     INIT_PARAM_DFLT(hash_delay, "time in cycles of hash access",1),
- #if defined(USE_CACHE_IIC)
-     INIT_PARAM_DFLT(repl, "replacement policy",NULL),
- #endif
-     INIT_PARAM_DFLT(subblock_size,
-                     "Size of subblock in IIC used for compression",
-                     0),
-     INIT_PARAM_DFLT(max_miss_count,
-                     "The number of misses to handle before calling exit",
-                     0),
-     INIT_PARAM_DFLT(addr_range, "The address range in bytes",
-                     vector<Range<Addr> >(1,RangeIn((Addr)0, MaxAddr))),
- //    INIT_PARAM_DFLT(mem_trace, "Memory trace to write accesses to", NULL),
-     INIT_PARAM_DFLT(split, "Whether this is a partitioned cache", false),
-     INIT_PARAM_DFLT(split_size, "the number of \"ways\" belonging to the LRU partition", 0),
-     INIT_PARAM_DFLT(lifo, "whether you are using a LIFO repl. policy", false),
-     INIT_PARAM_DFLT(two_queue, "whether the lifo should have two queue replacement", false),
-     INIT_PARAM_DFLT(prefetch_miss, "wheter you are using the hardware prefetcher from Miss stream", false),
-     INIT_PARAM_DFLT(prefetch_access, "wheter you are using the hardware prefetcher from Access stream", false),
-     INIT_PARAM_DFLT(prefetcher_size, "Number of entries in the harware prefetch queue", 100),
-     INIT_PARAM_DFLT(prefetch_past_page, "Allow prefetches to cross virtual page boundaries", false),
-     INIT_PARAM_DFLT(prefetch_serial_squash, "Squash prefetches with a later time on a subsequent miss", false),
-     INIT_PARAM_DFLT(prefetch_latency, "Latency of the prefetcher", 10),
-     INIT_PARAM_DFLT(prefetch_degree, "Degree of the prefetch depth", 1),
-     INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"),
-     INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true),
-     INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true),
-     INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false)
- END_INIT_SIM_OBJECT_PARAMS(BaseCache)
- 
- 
 -#define BUILD_CACHE(TAGS, tags, c)                                      \
 +#define BUILD_CACHE(TAGS, tags)                                      \
      do {                                                                \
-         BasePrefetcher *pf;                                           \
-         if (pf_policy == "tagged") {                                    \
+         BasePrefetcher *pf;                                             \
+         if (prefetch_policy == Enums::tagged) {                         \
              BUILD_TAGGED_PREFETCHER(TAGS);                              \
          }                                                               \
-         else if (pf_policy == "stride") {                               \
+         else if (prefetch_policy == Enums::stride) {                    \
              BUILD_STRIDED_PREFETCHER(TAGS);                             \
          }                                                               \
-         else if (pf_policy == "ghb") {                                  \
+         else if (prefetch_policy == Enums::ghb) {                       \
              BUILD_GHB_PREFETCHER(TAGS);                                 \
          }                                                               \
          else {                                                          \
              BUILD_NULL_PREFETCHER(TAGS);                                \
          }                                                               \
 -        Cache<TAGS, c>::Params params(tags, mq, coh, base_params,       \
 -                                      pf, prefetch_access, latency,     \
 -                                      true,                             \
 -                                      store_compressed,                 \
 -                                      adaptive_compression,             \
 -                                      compressed_bus,                   \
 -                                      compAlg, compression_latency,     \
 -                                      prefetch_miss);                   \
 -        Cache<TAGS, c> *retval =                                        \
 -            new Cache<TAGS, c>(name, params);                           \
 +        Cache<TAGS>::Params params(tags, base_params,       \
 +                                   pf, prefetch_access, latency,        \
 +                                   true,                                \
 +                                   prefetch_miss);                      \
 +        Cache<TAGS> *retval =                                        \
-             new Cache<TAGS>(getInstanceName(), params);              \
++            new Cache<TAGS>(name, params);                              \
          return retval;                                                  \
      } while (0)
  
@@@ -324,29 -274,25 +239,26 @@@ BaseCacheParams::create(
      }
  
      // Build BaseCache param object
 -    BaseCache::Params base_params(addr_range, latency,
 -                                  block_size, max_miss_count);
 +    BaseCache::Params base_params(latency, block_size,
 +                                  mshrs, tgts_per_mshr, write_buffers,
 +                                  max_miss_count);
  
      //Warnings about prefetcher policy
-     if (pf_policy == "none" && (prefetch_miss || prefetch_access)) {
-         panic("With no prefetcher, you shouldn't prefetch from"
-               " either miss or access stream\n");
+     if (prefetch_policy == Enums::none) {
+         if (prefetch_miss || prefetch_access)
+             panic("With no prefetcher, you shouldn't prefetch from"
+                   " either miss or access stream\n");
      }
-     if ((pf_policy == "tagged" || pf_policy == "stride" ||
-          pf_policy == "ghb") && !(prefetch_miss || prefetch_access)) {
-         warn("With this prefetcher you should chose a prefetch"
-              " stream (miss or access)\nNo Prefetching will occur\n");
-     }
-     if ((pf_policy == "tagged" || pf_policy == "stride" ||
-          pf_policy == "ghb") && prefetch_miss && prefetch_access) {
-         panic("Can't do prefetches from both miss and access"
-               " stream\n");
-     }
-     if (pf_policy != "tagged" && pf_policy != "stride" &&
-         pf_policy != "ghb"    && pf_policy != "none") {
-         panic("Unrecognized form of a prefetcher: %s, try using"
-               "['none','stride','tagged','ghb']\n", pf_policy);
+ 
+     if (prefetch_policy == Enums::tagged || prefetch_policy == Enums::stride ||
+         prefetch_policy == Enums::ghb) {
+ 
+         if (!prefetch_miss && !prefetch_access)
+             warn("With this prefetcher you should chose a prefetch"
+                  " stream (miss or access)\nNo Prefetching will occur\n");
+ 
+         if (prefetch_miss && prefetch_access)
+             panic("Can't do prefetches from both miss and access stream");
      }
  
  #if defined(USE_CACHE_IIC)
@@@ -364,11 -310,13 +276,6 @@@
      const void *repl = NULL;
  #endif
  
 -    if (mshrs == 1 /*|| out_bus->doEvents() == false*/) {
 -        BlockingBuffer *mq = new BlockingBuffer(true);
 -        BUILD_COHERENCE(BlockingBuffer);
 -    } else {
 -        MissQueue *mq = new MissQueue(mshrs, tgts_per_mshr, write_buffers,
 -                                      true, prefetch_miss);
 -        BUILD_COHERENCE(MissQueue);
 -    }
 +    BUILD_CACHES;
      return NULL;
  }
- 
- REGISTER_SIM_OBJECT("BaseCache", BaseCache)
- 
- 
- #endif //DOXYGEN_SHOULD_SKIP_THIS

diff --cc src/mem/physical.cc
index 2742eca51a5c54b4c726dcae4c6d35ea90e73f9f,82a24e8337a0b81b076536aca8223b79ea5ffe62..b96fb8a5609b38567e1cea815889665464e48bbf
--- 1/src/mem/physical.cc
--- 2/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@@ -58,9 -57,8 +57,8 @@@ PhysicalMemory::PhysicalMemory(const Pa
          panic("Memory Size not divisible by page size\n");
  
      int map_flags = MAP_ANON | MAP_PRIVATE;
-     pmemAddr =
-         (uint8_t *)mmap(NULL, params()->addrRange.size(),
-                         PROT_READ | PROT_WRITE, map_flags, -1, 0);
 -    pmemAddr = (uint8_t *)mmap(NULL, params()->range.size(), PROT_READ | PROT_WRITE,
 -            map_flags, -1, 0);
++    pmemAddr = (uint8_t *)mmap(NULL, params()->range.size(),
++                               PROT_READ | PROT_WRITE, map_flags, -1, 0);
  
      if (pmemAddr == (void *)MAP_FAILED) {
          perror("mmap");

diff --cc src/mem/physical.hh
Simple merge