const Addr MaxAddr = (Addr)-1;
+#if !FULL_SYSTEM
static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
{
// check for error condition. Alpha syscall convention is to
regs->intRegFile[ReturnValueReg] = -return_value.value();
}
}
+#endif
};
static inline AlphaISA::ExtMachInst
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "kern/linux/linux.hh"
-#include "mem/functional/functional.hh"
#include "sim/process.hh"
#include "sim/syscall_emul.hh"
strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
strcpy(name->machine, "alpha");
- name.copyOut(xc->getMemPtr());
+ name.copyOut(xc->port);
return 0;
}
TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
// I don't think this exactly matches the HW FPCR
*fpcr = 0;
- fpcr.copyOut(xc->getMemPtr());
+ fpcr.copyOut(xc->port);
return 0;
}
case 14: { // SSI_IEEE_FP_CONTROL
TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
// I don't think this exactly matches the HW FPCR
- fpcr.copyIn(xc->getMemPtr());
+ fpcr.copyIn(xc->port);
DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): "
" setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr));
return 0;
AlphaLinuxProcess::AlphaLinuxProcess(const std::string &name,
ObjectFile *objFile,
+ System *system,
int stdin_fd,
int stdout_fd,
int stderr_fd,
std::vector<std::string> &argv,
std::vector<std::string> &envp)
- : LiveProcess(name, objFile, stdin_fd, stdout_fd, stderr_fd, argv, envp),
+ : LiveProcess(name, objFile, system, stdin_fd, stdout_fd,
+ stderr_fd, argv, envp),
Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc))
{
- init_regs->intRegFile[0] = 0;
+ //init_regs->intRegFile[0] = 0;
}
{
LiveProcess *
-createProcess(const std::string &nm, ObjectFile * objFile,
+createProcess(const std::string &nm, ObjectFile * objFile, System *system,
int stdin_fd, int stdout_fd, int stderr_fd,
std::vector<std::string> &argv, std::vector<std::string> &envp)
{
fatal("Object file does not match architecture.");
switch (objFile->getOpSys()) {
case ObjectFile::Tru64:
- process = new AlphaTru64Process(nm, objFile,
+ process = new AlphaTru64Process(nm, objFile, system,
stdin_fd, stdout_fd, stderr_fd,
argv, envp);
break;
case ObjectFile::Linux:
- process = new AlphaLinuxProcess(nm, objFile,
+ process = new AlphaLinuxProcess(nm, objFile, system,
stdin_fd, stdout_fd, stderr_fd,
argv, envp);
break;
{
LiveProcess *
-createProcess(const std::string &nm, ObjectFile * objFile,
+createProcess(const std::string &nm, ObjectFile * objFile, System * system,
int stdin_fd, int stdout_fd, int stderr_fd,
std::vector<std::string> &argv, std::vector<std::string> &envp);
#include "arch/alpha/tru64/process.hh"
#include "cpu/exec_context.hh"
#include "kern/tru64/tru64.hh"
-#include "mem/functional/functional.hh"
#include "sim/fake_syscall.hh"
#include "sim/process.hh"
#include "sim/syscall_emul.hh"
strcpy(name->version, "732");
strcpy(name->machine, "alpha");
- name.copyOut(xc->getMemPtr());
+ name.copyOut(xc->port);
return 0;
}
case Tru64::GSI_MAX_CPU: {
TypedBufferArg<uint32_t> max_cpu(xc->getSyscallArg(1));
*max_cpu = htog((uint32_t)process->numCpus());
- max_cpu.copyOut(xc->getMemPtr());
+ max_cpu.copyOut(xc->port);
return 1;
}
case Tru64::GSI_CPUS_IN_BOX: {
TypedBufferArg<uint32_t> cpus_in_box(xc->getSyscallArg(1));
*cpus_in_box = htog((uint32_t)process->numCpus());
- cpus_in_box.copyOut(xc->getMemPtr());
+ cpus_in_box.copyOut(xc->port);
return 1;
}
case Tru64::GSI_PHYSMEM: {
TypedBufferArg<uint64_t> physmem(xc->getSyscallArg(1));
*physmem = htog((uint64_t)1024 * 1024); // physical memory in KB
- physmem.copyOut(xc->getMemPtr());
+ physmem.copyOut(xc->port);
return 1;
}
infop->cpu_ex_binding = htog(0);
infop->mhz = htog(667);
- infop.copyOut(xc->getMemPtr());
+ infop.copyOut(xc->port);
return 1;
}
case Tru64::GSI_PROC_TYPE: {
TypedBufferArg<uint64_t> proc_type(xc->getSyscallArg(1));
*proc_type = htog((uint64_t)11);
- proc_type.copyOut(xc->getMemPtr());
+ proc_type.copyOut(xc->port);
return 1;
}
strncpy((char *)bufArg.bufferPtr(),
"COMPAQ Professional Workstation XP1000",
nbytes);
- bufArg.copyOut(xc->getMemPtr());
+ bufArg.copyOut(xc->port);
return 1;
}
case Tru64::GSI_CLK_TCK: {
TypedBufferArg<uint64_t> clk_hz(xc->getSyscallArg(1));
*clk_hz = htog((uint64_t)1024);
- clk_hz.copyOut(xc->getMemPtr());
+ clk_hz.copyOut(xc->port);
return 1;
}
AlphaTru64Process::AlphaTru64Process(const std::string &name,
ObjectFile *objFile,
+ System *system,
int stdin_fd,
int stdout_fd,
int stderr_fd,
std::vector<std::string> &argv,
std::vector<std::string> &envp)
- : LiveProcess(name, objFile, stdin_fd, stdout_fd, stderr_fd, argv, envp),
+ : LiveProcess(name, objFile, system, stdin_fd, stdout_fd,
+ stderr_fd, argv, envp),
Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)),
Num_Mach_Syscall_Descs(sizeof(machSyscallDescs) / sizeof(SyscallDesc))
{
#include <algorithm>
#include "base/intmath.hh"
-#include "targetarch/isa_traits.hh" // for Addr
+#include "arch/isa_traits.hh" // for Addr
/**
* This class takes an arbitrary memory region (address/length pair)
#include "base/trace.hh" // for DPRINTF
+#include "sim/byteswap.hh"
+
using namespace std;
}
CPUExecContext::CPUExecContext(RegFile *regFile)
- : cpu(NULL), thread_num(-1), process(NULL), mem(NULL), asid(-1),
+ : cpu(NULL), thread_num(-1), process(NULL), asid(-1),
func_exe_inst(0), storeCondFailures(0)
{
regs = *regFile;
{
panic("instRead not implemented");
// return funcPhysMem->read(req, inst);
- return No_Fault;
+ return NoFault;
}
void setCpuId(int id) { cpu_id = id; }
int readCpuId() { return cpu_id; }
- FunctionalMemory *getMemPtr() { return mem; }
-
void copyArchRegs(ExecContext *xc);
//
#define __CPU_EXEC_CONTEXT_HH__
#include "config/full_system.hh"
-#include "mem/mem_req.hh"
+#include "mem/request.hh"
#include "sim/faults.hh"
#include "sim/host.hh"
#include "sim/serialize.hh"
class AlphaITB;
class BaseCPU;
class Event;
-class FunctionalMemory;
class PhysicalMemory;
+class TranslatingPort;
class Process;
class System;
Halted
};
+ TranslatingPort * port;
+
virtual ~ExecContext() { };
virtual BaseCPU *getCpuPtr() = 0;
virtual int readCpuId() = 0;
- virtual FunctionalMemory *getMemPtr() = 0;
-
#if FULL_SYSTEM
virtual System *getSystemPtr() = 0;
virtual int getInstAsid() = 0;
virtual int getDataAsid() = 0;
- virtual Fault translateInstReq(MemReqPtr &req) = 0;
+ virtual Fault translateInstReq(CpuRequestPtr &req) = 0;
- virtual Fault translateDataReadReq(MemReqPtr &req) = 0;
+ virtual Fault translateDataReadReq(CpuRequestPtr &req) = 0;
- virtual Fault translateDataWriteReq(MemReqPtr &req) = 0;
+ virtual Fault translateDataWriteReq(CpuRequestPtr &req) = 0;
// Also somewhat obnoxious. Really only used for the TLB fault.
// However, may be quite useful in SPARC.
int readCpuId() { return actualXC->readCpuId(); }
- FunctionalMemory *getMemPtr() { return actualXC->getMemPtr(); }
-
#if FULL_SYSTEM
System *getSystemPtr() { return actualXC->getSystemPtr(); }
int getInstAsid() { return actualXC->getInstAsid(); }
int getDataAsid() { return actualXC->getDataAsid(); }
- Fault translateInstReq(MemReqPtr &req)
+ Fault translateInstReq(CpuRequestPtr &req)
{ return actualXC->translateInstReq(req); }
- Fault translateDataReadReq(MemReqPtr &req)
+ Fault translateDataReadReq(CpuRequestPtr &req)
{ return actualXC->translateDataReadReq(req); }
- Fault translateDataWriteReq(MemReqPtr &req)
+ Fault translateDataWriteReq(CpuRequestPtr &req)
{ return actualXC->translateDataWriteReq(req); }
// @todo: Do I need this?
}
return fault;
#else
- return No_Fault;
+ return NoFault;
#endif
}
return fault;
#else
panic("copy not implemented");
- return No_Fault;
+ return NoFault;
#endif
}
}
// @todo: Figure out a way to create a Fault from the packet result.
- return No_Fault;
+ return NoFault;
}
// memReq->reset(addr, sizeof(T), flags);
Fault fault = cpuXC->translateDataReadReq(data_read_req);
// Now do the access.
- if (fault == No_Fault) {
+ if (fault == NoFault) {
#if SIMPLE_CPU_MEM_TIMING
data_read_pkt = new Packet;
data_read_pkt->cmd = Read;
}
// @todo: Figure out a way to create a Fault from the packet result.
- return No_Fault;
+ return NoFault;
#endif
}
/*
// translate to physical address
Fault fault = cpuXC->translateDataWriteReq(data_write_req);
// Now do the access.
- if (fault == No_Fault) {
+ if (fault == NoFault) {
#if SIMPLE_CPU_MEM_TIMING
data_write_pkt = new Packet;
data_write_pkt->cmd = Write;
IFETCH_FLAGS(xc->regs.pc));
*/
- fault = xc->translateInstReq(ifetch_req);
+ fault = cpuXC->translateInstReq(ifetch_req);
if (fault == NoFault) {
#if SIMPLE_CPU_MEM_TIMING
#include "sim/syscall_emul.hh"
+class TranslatingPort;
+
///
/// This class encapsulates the types, structures, constants,
/// functions, and syscall-number mappings specific to the Alpha Linux
/// memory space. Used by stat(), fstat(), and lstat().
#if !BSD_HOST
static void
- copyOutStatBuf(FunctionalMemory *mem, Addr addr, hst_stat *host)
+ copyOutStatBuf(TranslatingPort *mem, Addr addr, hst_stat *host)
{
TypedBufferArg<Linux::tgt_stat> tgt(addr);
// Third version for bsd systems which no longer have any support for
// the old stat() call and stat() is actually a stat64()
static void
- copyOutStatBuf(FunctionalMemory *mem, Addr addr, hst_stat64 *host)
+ copyOutStatBuf(TranslatingPort *mem, Addr addr, hst_stat64 *host)
{
TypedBufferArg<Linux::tgt_stat> tgt(addr);
// Same for stat64
static void
- copyOutStat64Buf(FunctionalMemory *mem, int fd, Addr addr, hst_stat64 *host)
+ copyOutStat64Buf(TranslatingPort *mem, int fd, Addr addr, hst_stat64 *host)
{
TypedBufferArg<Linux::tgt_stat64> tgt(addr);
typedef struct statfs global_statfs;
typedef struct dirent global_dirent;
+class TranslatingPort;
+
///
/// This class encapsulates the types, structures, constants,
/// functions, and syscall-number mappings specific to the Alpha Tru64
/// memory space. Used by stat(), fstat(), and lstat().
template <class T>
static void
- copyOutStatBuf(FunctionalMemory *mem, Addr addr, global_stat *host)
+ copyOutStatBuf(TranslatingPort *mem, Addr addr, global_stat *host)
{
TypedBufferArg<T> tgt(addr);
/// memory space. Used by statfs() and fstatfs().
template <class T>
static void
- copyOutStatfsBuf(FunctionalMemory *mem, Addr addr, global_statfs *host)
+ copyOutStatfsBuf(TranslatingPort *mem, Addr addr, global_statfs *host)
{
TypedBufferArg<T> tgt(addr);
class F64 {
public:
- static void copyOutStatBuf(FunctionalMemory *mem, Addr addr,
+ static void copyOutStatBuf(TranslatingPort *mem, Addr addr,
global_stat *host)
{
Tru64::copyOutStatBuf<Tru64::F64_stat>(mem, addr, host);
}
- static void copyOutStatfsBuf(FunctionalMemory *mem, Addr addr,
+ static void copyOutStatfsBuf(TranslatingPort *mem, Addr addr,
global_statfs *host)
{
Tru64::copyOutStatfsBuf<Tru64::F64_statfs>(mem, addr, host);
class PreF64 {
public:
- static void copyOutStatBuf(FunctionalMemory *mem, Addr addr,
+ static void copyOutStatBuf(TranslatingPort *mem, Addr addr,
global_stat *host)
{
Tru64::copyOutStatBuf<Tru64::pre_F64_stat>(mem, addr, host);
}
- static void copyOutStatfsBuf(FunctionalMemory *mem, Addr addr,
+ static void copyOutStatfsBuf(TranslatingPort *mem, Addr addr,
global_statfs *host)
{
Tru64::copyOutStatfsBuf<Tru64::pre_F64_statfs>(mem, addr, host);
/// the simulated memory space. Used by pre_F64_stat(),
/// pre_F64_fstat(), and pre_F64_lstat().
static void
- copyOutPreF64StatBuf(FunctionalMemory *mem, Addr addr, struct stat *host)
+ copyOutPreF64StatBuf(TranslatingPort *mem, Addr addr, struct stat *host)
{
TypedBufferArg<Tru64::pre_F64_stat> tgt(addr);
// just pass basep through uninterpreted.
TypedBufferArg<int64_t> basep(tgt_basep);
- basep.copyIn(xc->getMemPtr());
+ basep.copyIn(xc->port);
long host_basep = (off_t)htog((int64_t)*basep);
int host_result = getdirentries(fd, host_buf, tgt_nbytes, &host_basep);
tgt_dp->d_reclen = tgt_bufsize;
tgt_dp->d_namlen = namelen;
strcpy(tgt_dp->d_name, host_dp->d_name);
- tgt_dp.copyOut(xc->getMemPtr());
+ tgt_dp.copyOut(xc->port);
tgt_buf_ptr += tgt_bufsize;
host_buf_ptr += host_dp->d_reclen;
delete [] host_buf;
*basep = htog((int64_t)host_basep);
- basep.copyOut(xc->getMemPtr());
+ basep.copyOut(xc->port);
return tgt_buf_ptr - tgt_buf;
#endif
using TheISA::RegFile;
TypedBufferArg<Tru64::sigcontext> sc(xc->getSyscallArg(0));
- sc.copyIn(xc->getMemPtr());
+ sc.copyIn(xc->port);
// Restore state from sigcontext structure.
// Note that we'll advance PC <- NPC before the end of the cycle,
elp->si_phz = htog(clk_hz);
elp->si_boottime = htog(seconds_since_epoch); // seconds since epoch?
elp->si_max_procs = htog(process->numCpus());
- elp.copyOut(xc->getMemPtr());
+ elp.copyOut(xc->port);
return 0;
}
{
TypedBufferArg<Tru64::vm_stack> argp(xc->getSyscallArg(0));
- argp.copyIn(xc->getMemPtr());
+ argp.copyIn(xc->port);
// if the user chose an address, just let them have it. Otherwise
// pick one for them.
int stack_size = (htog(argp->rsize) + htog(argp->ysize) +
htog(argp->gsize));
process->next_thread_stack_base -= stack_size;
- argp.copyOut(xc->getMemPtr());
+ argp.copyOut(xc->port);
}
return 0;
TypedBufferArg<Tru64::nxm_task_attr> attrp(xc->getSyscallArg(0));
TypedBufferArg<Addr> configptr_ptr(xc->getSyscallArg(1));
- attrp.copyIn(xc->getMemPtr());
+ attrp.copyIn(xc->port);
if (gtoh(attrp->nxm_version) != NXM_LIB_VERSION) {
cerr << "nxm_task_init: thread library version mismatch! "
config->nxm_slot_state = htog(slot_state_addr);
config->nxm_rad[0] = htog(rad_state_addr);
- config.copyOut(xc->getMemPtr());
+ config.copyOut(xc->port);
// initialize the slot_state array and copy it out
TypedBufferArg<Tru64::nxm_slot_state_t> slot_state(slot_state_addr,
(i == 0) ? Tru64::NXM_SLOT_BOUND : Tru64::NXM_SLOT_AVAIL;
}
- slot_state.copyOut(xc->getMemPtr());
+ slot_state.copyOut(xc->port);
// same for the per-RAD "shared" struct. Note that we need to
// allocate extra bytes for the per-VP array which is embedded at
}
}
- rad_state.copyOut(xc->getMemPtr());
+ rad_state.copyOut(xc->port);
//
// copy pointer to shared config area out to user
//
*configptr_ptr = htog(config_addr);
- configptr_ptr.copyOut(xc->getMemPtr());
+ configptr_ptr.copyOut(xc->port);
// Register this as a valid address range with the process
process->nxm_start = base_addr;
int thread_index = xc->getSyscallArg(2);
// get attribute args
- attrp.copyIn(xc->getMemPtr());
+ attrp.copyIn(xc->port);
if (gtoh(attrp->version) != NXM_LIB_VERSION) {
cerr << "nxm_thread_create: thread library version mismatch! "
TypedBufferArg<Tru64::nxm_shared> rad_state(0x14000,
rad_state_size);
- rad_state.copyIn(xc->getMemPtr());
+ rad_state.copyIn(xc->port);
uint64_t uniq_val = gtoh(attrp->pthid) - gtoh(rad_state->nxm_uniq_offset);
// This is supposed to be a port number. Make something up.
*kidp = htog(99);
- kidp.copyOut(xc->getMemPtr());
+ kidp.copyOut(xc->port);
return 0;
} else if (gtoh(attrp->type) == Tru64::NXM_TYPE_VP) {
ssp->nxm_u.pth_id = attrp->pthid;
ssp->nxm_u.nxm_active = htog(uniq_val | 1);
- rad_state.copyOut(xc->getMemPtr());
+ rad_state.copyOut(xc->port);
Addr slot_state_addr = 0x12000 + sizeof(Tru64::nxm_config_info);
int slot_state_size =
slot_state(slot_state_addr,
slot_state_size);
- slot_state.copyIn(xc->getMemPtr());
+ slot_state.copyIn(xc->port);
if (slot_state[thread_index] != Tru64::NXM_SLOT_AVAIL) {
cerr << "nxm_thread_createFunc: requested VP slot "
// doesn't work anyway
slot_state[thread_index] = Tru64::NXM_SLOT_BOUND;
- slot_state.copyOut(xc->getMemPtr());
+ slot_state.copyOut(xc->port);
// Find a free simulator execution context.
for (int i = 0; i < process->numCpus(); ++i) {
// and get away with just sticking the thread index
// here.
*kidp = htog(thread_index);
- kidp.copyOut(xc->getMemPtr());
+ kidp.copyOut(xc->port);
return 0;
}
{
TypedBufferArg<uint64_t> lockp(uaddr);
- lockp.copyIn(xc->getMemPtr());
+ lockp.copyIn(xc->port);
if (gtoh(*lockp) == 0) {
// lock is free: grab it
*lockp = htog(1);
- lockp.copyOut(xc->getMemPtr());
+ lockp.copyOut(xc->port);
} else {
// lock is busy: disable until free
process->waitList.push_back(Process::WaitRec(uaddr, xc));
{
TypedBufferArg<uint64_t> lockp(uaddr);
- lockp.copyIn(xc->getMemPtr());
+ lockp.copyIn(xc->port);
assert(*lockp != 0);
// Check for a process waiting on the lock.
// clear lock field if no waiting context is taking over the lock
if (num_waiting == 0) {
*lockp = 0;
- lockp.copyOut(xc->getMemPtr());
+ lockp.copyOut(xc->port);
}
}
Addr uaddr = xc->getSyscallArg(0);
TypedBufferArg<uint64_t> lockp(uaddr);
- lockp.copyIn(xc->getMemPtr());
+ lockp.copyIn(xc->port);
if (gtoh(*lockp) == 0) {
// lock is free: grab it
*lockp = htog(1);
- lockp.copyOut(xc->getMemPtr());
+ lockp.copyOut(xc->port);
return 0;
} else {
return 1;
TypedBufferArg<uint64_t> lockp(lock_addr);
// user is supposed to acquire lock before entering
- lockp.copyIn(xc->getMemPtr());
+ lockp.copyIn(xc->port);
assert(gtoh(*lockp) != 0);
m5_unlock_mutex(lock_addr, process, xc);
#define __MEM_PACKET_HH__
#include "mem/request.hh"
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "sim/root.hh"
struct Packet;
#include <map>
#include <fstream>
+#include "arch/faults.hh"
#include "base/bitfield.hh"
#include "base/intmath.hh"
#include "base/trace.hh"
#include "sim/system.hh"
using namespace std;
+using namespace TheISA;
PageTable::PageTable(System *_system, Addr _pageSize)
: pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
if (size < sizeof(uint64_t)) {
if (!isPowerOf2(size)) {
panic("Invalid request size!\n");
- return Machine_Check_Fault;
+ return genMachineCheckFault();
}
if ((size - 1) & addr)
- return Alignment_Fault;
+ return genAlignmentFault();
}
else {
if ((addr & (VMPageSize - 1)) + size > VMPageSize) {
panic("Invalid request size!\n");
- return Machine_Check_Fault;
+ return genMachineCheckFault();
}
if ((sizeof(uint64_t) - 1) & addr)
- return Alignment_Fault;
+ return genAlignmentFault();
}
- return No_Fault;
+ return NoFault;
}
{
assert(pageAlign(req->vaddr + req->size - 1) == pageAlign(req->vaddr));
if (!translate(req->vaddr, req->paddr)) {
- return Machine_Check_Fault;
+ return genMachineCheckFault();
}
return page_check(req->paddr, req->size);
}
#include <string>
#include <map>
+#include "arch/isa_traits.hh"
#include "base/trace.hh"
#include "mem/request.hh"
#include "mem/packet.hh"
public:
- PageTable(System *_system, Addr _pageSize = VMPageSize);
+ PageTable(System *_system, Addr _pageSize = TheISA::VMPageSize);
~PageTable();
#include "sim/host.hh"
#include "sim/builder.hh"
#include "sim/eventq.hh"
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
using namespace std;
+using namespace TheISA;
PhysicalMemory::MemResponseEvent::MemResponseEvent(Packet &pkt, MemoryPort* _m)
: Event(&mainEventQueue, CPU_Tick_Pri), pkt(pkt), memoryPort(_m)
#ifndef __MEM_REQUEST_HH__
#define __MEM_REQUEST_HH__
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
class Request;
class CpuRequest;
*/
#include <string>
+#include "arch/faults.hh"
#include "base/chunk_generator.hh"
#include "mem/port.hh"
#include "mem/translating_port.hh"
#include "mem/page_table.hh"
+using namespace TheISA;
+
TranslatingPort::TranslatingPort(Port *_port, PageTable *p_table)
: port(_port), pTable(p_table)
{ }
for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
if (!pTable->translate(gen.addr(),paddr))
- return Machine_Check_Fault;
+ return genMachineCheckFault();
port->readBlobFunctional(paddr, p + prevSize, gen.size());
prevSize += gen.size();
}
- return No_Fault;
+ return NoFault;
}
Fault
VMPageSize);
pTable->translate(gen.addr(), paddr);
} else {
- return Machine_Check_Fault;
+ return genMachineCheckFault();
}
}
prevSize += gen.size();
}
- return No_Fault;
+ return NoFault;
}
VMPageSize);
pTable->translate(gen.addr(), paddr);
} else {
- return Machine_Check_Fault;
+ return genMachineCheckFault();
}
}
port->memsetBlobFunctional(paddr, val, gen.size());
}
- return No_Fault;
+ return NoFault;
}
do {
c = *str++;
if (!pTable->translate(vaddr++,paddr))
- return Machine_Check_Fault;
+ return genMachineCheckFault();
port->writeBlobFunctional(paddr, &c, 1);
} while (c);
- return No_Fault;
+ return NoFault;
}
Fault
do {
if (!pTable->translate(vaddr++,paddr))
- return Machine_Check_Fault;
+ return genMachineCheckFault();
port->readBlobFunctional(paddr, &c, 1);
str += c;
} while (c);
- return No_Fault;
+ return NoFault;
}
#include "mem/page_table.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
class CPUExecContext;
class ExecContext;
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "cpu/exec_context.hh"
-#include "arch/vtophys.hh"
#include "mem/memory.hh"
#include "sim/builder.hh"
#include "arch/isa_traits.hh"
#include "base/remote_gdb.hh"
#include "kern/kernel_stats.hh"
#include "mem/functional/memory_control.hh"
-#include "targetarch/vtophys.hh"
+#include "arch/vtophys.hh"
#endif
using namespace std;
DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry);
DPRINTF(Loader, "Kernel loaded...\n");
-#if FULL_SYSTEM
kernelBinning = new Kernel::Binning(this);
#endif // FULL_SYSTEM
projects / gem5.git / commitdiff