Move star imports to make `from nmigen import *` usable.

diff --git a/examples/alu.py b/examples/alu.py
index 456a75bacce68afc9c26f3766286f528bc4f48aa..4b051c6be245c04935d8503476205903364d1183 100644 (file)
--- a/examples/alu.py
+++ b/examples/alu.py
@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog
 
 

diff --git a/examples/alu_hier.py b/examples/alu_hier.py
index 6f862ca452fc8f3dacaea1ce07c3636546d47ef6..8551d38fea0160eca1696623b9033cbb87be2dec 100644 (file)
--- a/examples/alu_hier.py
+++ b/examples/alu_hier.py
@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog
 
 

diff --git a/examples/arst.py b/examples/arst.py
index c35640ed10a16029b0fa3f1e857789f4277b2a3b..e99fc8d0bb938c07b98a171618ef094110b210a3 100644 (file)
--- a/examples/arst.py
+++ b/examples/arst.py
@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog
 
 

diff --git a/examples/cdc.py b/examples/cdc.py
index 8bbdc11da6ae9fad45eb692d4eb23a5274187330..7d2486df347ef6ca51048b4c98ecaf5b00804db5 100644 (file)
--- a/examples/cdc.py
+++ b/examples/cdc.py
@@ -1,6 +1,5 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog
-from nmigen.genlib.cdc import *
 
 
 i, o = Signal(name="i"), Signal(name="o")

diff --git a/examples/clkdiv.py b/examples/clkdiv.py
index ce49eae4dd31e27c3a52c66431b2b1ebf521bae8..7be26b6368ecb016101b101e678ca63bdfe7671b 100644 (file)
--- a/examples/clkdiv.py
+++ b/examples/clkdiv.py
@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog, pysim
 
 

diff --git a/examples/ctrl.py b/examples/ctrl.py
index 64c3b5dbc580c2c905225b0f5078111183f4fcd2..fa9cf44990af146a2e010670682dde76c50546ff 100644 (file)
--- a/examples/ctrl.py
+++ b/examples/ctrl.py
@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog, pysim
 
 

diff --git a/examples/pmux.py b/examples/pmux.py
index cda54472edc9f79476a6f0d8eec819fe0b818b9c..27ec33fa2db163f8c287a312f2045a67ad811792 100644 (file)
--- a/examples/pmux.py
+++ b/examples/pmux.py
@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog
 
 

diff --git a/nmigen/__init__.py b/nmigen/__init__.py
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..36b1791cd8d51c3878f2520299467670e53df659 100644 (file)
--- a/nmigen/__init__.py
+++ b/nmigen/__init__.py
@@ -0,0 +1,7 @@
+from .fhdl.ast import Value, Const, Mux, Cat, Repl, Signal, ClockSignal, ResetSignal
+from .fhdl.dsl import Module
+from .fhdl.cd import ClockDomain
+from .fhdl.ir import Fragment
+from .fhdl.xfrm import ResetInserter, CEInserter
+
+from .genlib.cdc import MultiReg

diff --git a/nmigen/fhdl/__init__.py b/nmigen/fhdl/__init__.py
index cc83fb5821546a114c6144f2c556e5c8fcffe03c..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/nmigen/fhdl/__init__.py
+++ b/nmigen/fhdl/__init__.py
@@ -1,5 +0,0 @@
-from .cd import ClockDomain
-from .ast import Value, Const, Mux, Cat, Repl, Signal, ClockSignal, ResetSignal
-from .ir import Fragment
-from .dsl import Module
-from .xfrm import ResetInserter, CEInserter