O3: Update stats for LSQ changes.
authorAli Saidi <Ali.Saidi@ARM.com>
Fri, 19 Aug 2011 20:08:06 +0000 (15:08 -0500)
committerAli Saidi <Ali.Saidi@ARM.com>
Fri, 19 Aug 2011 20:08:06 +0000 (15:08 -0500)
71 files changed:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
tests/long/00.gzip/ref/x86/linux/o3-timing/simout
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
tests/long/10.mcf/ref/arm/linux/o3-timing/simout
tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
tests/long/10.mcf/ref/x86/linux/o3-timing/simout
tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
tests/long/20.parser/ref/arm/linux/o3-timing/simout
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
tests/long/20.parser/ref/x86/linux/o3-timing/simout
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
tests/long/30.eon/ref/arm/linux/o3-timing/simout
tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
tests/long/50.vortex/ref/arm/linux/o3-timing/simout
tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
tests/long/70.twolf/ref/arm/linux/o3-timing/simout
tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
tests/long/70.twolf/ref/x86/linux/o3-timing/simout
tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
tests/quick/00.hello/ref/arm/linux/o3-timing/simout
tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
tests/quick/00.hello/ref/mips/linux/o3-timing/simout
tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
tests/quick/00.hello/ref/power/linux/o3-timing/simout
tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
tests/quick/00.hello/ref/x86/linux/o3-timing/simout
tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

index ac32dbe3f67f79d9af5ef3df958106a64a398815..5c5a7a6e93638ee73adcdd8b3141390d59bdebb6 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:00:53
-gem5 started Jul  8 2011 16:09:24
+gem5 compiled Jul 15 2011 17:43:54
+gem5 started Jul 15 2011 18:05:21
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -39,4 +39,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 145300717500 because target called exit()
+Exiting @ tick 145175788500 because target called exit()
index 339674eddfbbd03600e131033778b83895ee907a..4f3a6d8f344a263d6835f461aa2b1cdad2d48142 100644 (file)
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.145301                       # Number of seconds simulated
-sim_ticks                                145300717500                       # Number of ticks simulated
+sim_seconds                                  0.145176                       # Number of seconds simulated
+sim_ticks                                145175788500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 109615                       # Simulator instruction rate (inst/s)
-host_tick_rate                               28162171                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 246532                       # Number of bytes of host memory used
-host_seconds                                  5159.43                       # Real time elapsed on the host
+host_inst_rate                                 116167                       # Simulator instruction rate (inst/s)
+host_tick_rate                               29819633                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 246468                       # Number of bytes of host memory used
+host_seconds                                  4868.46                       # Real time elapsed on the host
 sim_insts                                   565552443                       # Number of instructions simulated
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    125840781                       # DTB read hits
-system.cpu.dtb.read_misses                      26740                       # DTB read misses
+system.cpu.dtb.read_hits                    125726238                       # DTB read hits
+system.cpu.dtb.read_misses                      26702                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                125867521                       # DTB read accesses
-system.cpu.dtb.write_hits                    41455603                       # DTB write hits
-system.cpu.dtb.write_misses                     32148                       # DTB write misses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                41487751                       # DTB write accesses
-system.cpu.dtb.data_hits                    167296384                       # DTB hits
-system.cpu.dtb.data_misses                      58888                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                167355272                       # DTB accesses
-system.cpu.itb.fetch_hits                    71694847                       # ITB hits
+system.cpu.dtb.read_accesses                125752940                       # DTB read accesses
+system.cpu.dtb.write_hits                    41507366                       # DTB write hits
+system.cpu.dtb.write_misses                     32028                       # DTB write misses
+system.cpu.dtb.write_acv                            1                       # DTB write access violations
+system.cpu.dtb.write_accesses                41539394                       # DTB write accesses
+system.cpu.dtb.data_hits                    167233604                       # DTB hits
+system.cpu.dtb.data_misses                      58730                       # DTB misses
+system.cpu.dtb.data_acv                             1                       # DTB access violations
+system.cpu.dtb.data_accesses                167292334                       # DTB accesses
+system.cpu.itb.fetch_hits                    71588816                       # ITB hits
 system.cpu.itb.fetch_misses                        40                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                71694887                       # ITB accesses
+system.cpu.itb.fetch_accesses                71588856                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -41,246 +41,246 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                        290601436                       # number of cpu cycles simulated
+system.cpu.numCycles                        290351578                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 82480135                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           75938237                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            4123227                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              78114904                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 69862682                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 82068439                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           75472139                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            4139210                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              77758293                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 69764860                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  1959581                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                 207                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           74561330                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      742166836                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    82480135                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           71822263                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     139513131                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                17330809                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               63439148                       # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS                  1965418                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                 206                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           74381248                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      740847057                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    82068439                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           71730278                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     139388095                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                17359106                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               63481916                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                   31                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           978                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  71694847                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1192151                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          290532092                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.554509                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.199356                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles           957                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  71588816                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1228525                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          290282404                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.552160                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.199400                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                151018961     51.98%     51.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 11571435      3.98%     55.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 15893812      5.47%     61.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 16015901      5.51%     66.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 13154387      4.53%     71.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 15895840      5.47%     76.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  6797382      2.34%     79.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3595958      1.24%     80.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 56588416     19.48%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                150894309     51.98%     51.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 11757724      4.05%     56.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 15902063      5.48%     61.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 15874475      5.47%     66.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 13293221      4.58%     71.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 15622251      5.38%     76.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  6768599      2.33%     79.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3592047      1.24%     80.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 56577715     19.49%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            290532092                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.283826                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.553899                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 90749428                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              49730662                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 127248783                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9786563                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               13016656                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              4449520                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   868                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              730230726                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  3285                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               13016656                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 99035242                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                12652833                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            552                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 123482350                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              42344459                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              716220339                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   269                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               32893905                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               3996747                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           545787696                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             940589265                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        940587099                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              2166                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            290282404                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.282652                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.551552                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 90540829                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              49762589                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 127167334                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9782311                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               13029341                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4494723                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   873                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              729210837                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  3260                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               13029341                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 98854754                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                12652695                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            558                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 123369042                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              42376014                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              715226972                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   244                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               32893526                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4012041                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           545137745                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             939207717                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        939205613                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              2104                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             463854889                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 81932807                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                 81282856                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 36                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             35                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  82656426                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            131826399                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            43887979                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          16660025                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          7232836                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  645179442                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts                  82693608                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            131825687                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            43890067                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          17591169                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          7047053                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  644543109                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  29                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 621649928                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            372243                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        78544400                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     43423824                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                 621562613                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            380292                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        77712656                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     42125820                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             12                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     290532092                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.139695                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.881267                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples     290282404                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.141234                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.879500                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            71097940     24.47%     24.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            58395265     20.10%     44.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            55676712     19.16%     63.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            31603347     10.88%     74.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            33236000     11.44%     86.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            23958494      8.25%     94.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            12196902      4.20%     98.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3766140      1.30%     99.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              601292      0.21%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            70571105     24.31%     24.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            58751148     20.24%     44.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            55824387     19.23%     63.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            31456534     10.84%     74.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            33062190     11.39%     86.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            24005083      8.27%     94.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            12272709      4.23%     98.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3831324      1.32%     99.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              507924      0.17%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       290532092                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       290282404                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 4587811     88.39%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     54      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     88.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 424179      8.17%     96.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                178446      3.44%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 4555010     86.10%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     57      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     86.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 523123      9.89%     95.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                212105      4.01%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             451150539     72.57%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                 7830      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  33      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   6      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   5      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  5      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     72.57% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            128375845     20.65%     93.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            42115665      6.77%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             451240060     72.60%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                 7852      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  33      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   6      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   5      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  5      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     72.60% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            128169032     20.62%     93.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            42145620      6.78%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              621649928                       # Type of FU issued
-system.cpu.iq.rate                           2.139184                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     5190490                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.008350                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1539391263                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         723910400                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    609602063                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                3418                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               1948                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses         1597                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              626838696                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                    1722                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         11620337                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              621562613                       # Type of FU issued
+system.cpu.iq.rate                           2.140724                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     5290295                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.008511                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1539074805                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         722600568                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    609952454                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                3412                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               1900                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         1604                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              626851187                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    1721                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         11465807                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     17312357                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       134964                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       365628                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      4436658                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     17311645                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        67694                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       365195                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      4438746                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         5886                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         50751                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         5929                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         50756                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               13016656                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1515186                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                101274                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           690779591                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           2446688                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             131826399                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             43887979                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles               13029341                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1515549                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                101263                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           690142973                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           2399318                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             131825687                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             43890067                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 29                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  41001                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 13794                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         365628                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        4028203                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       602481                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              4630684                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             613929253                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             125867602                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           7720675                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                  41006                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 13792                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         365195                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4054325                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       604453                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              4658778                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             614025387                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             125753017                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           7537226                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      45600120                       # number of nop insts executed
-system.cpu.iew.exec_refs                    167374804                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 68499674                       # Number of branches executed
-system.cpu.iew.exec_stores                   41507202                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.112616                       # Inst execution rate
-system.cpu.iew.wb_sent                      611080780                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     609603660                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 419952220                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 531843575                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      45599835                       # number of nop insts executed
+system.cpu.iew.exec_refs                    167311882                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 68605174                       # Number of branches executed
+system.cpu.iew.exec_stores                   41558865                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.114765                       # Inst execution rate
+system.cpu.iew.wb_sent                      611451889                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     609954058                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 420339317                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 532241742                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.097731                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.789616                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.100743                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.789753                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      601856963                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        88769206                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        88132303                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           4122409                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    277515436                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.168733                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.607930                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           4138394                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    277253063                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.170786                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.607112                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     91720629     33.05%     33.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     75337959     27.15%     60.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     31629889     11.40%     71.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      9762168      3.52%     75.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     10089201      3.64%     78.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     21364718      7.70%     86.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      5897222      2.13%     88.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2300204      0.83%     89.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     29413446     10.60%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     91432186     32.98%     32.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     75471271     27.22%     60.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     31359713     11.31%     71.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      9812345      3.54%     75.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     10073105      3.63%     78.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     21591836      7.79%     86.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      5927353      2.14%     88.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2268519      0.82%     89.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     29316735     10.57%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    277515436                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    277253063                       # Number of insts commited each cycle
 system.cpu.commit.count                     601856963                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      153965363                       # Number of memory references committed
@@ -290,50 +290,50 @@ system.cpu.commit.branches                   62547159                       # Nu
 system.cpu.commit.fp_insts                       1520                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 563954763                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1197610                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              29413446                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              29316735                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    938663770                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1394275800                       # The number of ROB writes
-system.cpu.timesIdled                            2250                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           69344                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    937861205                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1393014626                       # The number of ROB writes
+system.cpu.timesIdled                            2237                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           69174                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   565552443                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             565552443                       # Number of Instructions Simulated
-system.cpu.cpi                               0.513836                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.513836                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.946145                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.946145                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                864545189                       # number of integer regfile reads
-system.cpu.int_regfile_writes               501712619                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       277                       # number of floating regfile reads
+system.cpu.cpi                               0.513395                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.513395                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.947819                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.947819                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                864633877                       # number of integer regfile reads
+system.cpu.int_regfile_writes               501928899                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       273                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                       57                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.icache.replacements                     36                       # number of replacements
-system.cpu.icache.tagsinuse                798.939045                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 71693570                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    940                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               76269.755319                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                799.817467                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 71587538                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    941                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               76076.023379                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            798.939045                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.390107                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               71693570                       # number of ReadReq hits
-system.cpu.icache.demand_hits                71693570                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               71693570                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1277                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1277                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1277                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       46025000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        46025000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       46025000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           71694847                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            71694847                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           71694847                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0            799.817467                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.390536                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               71587538                       # number of ReadReq hits
+system.cpu.icache.demand_hits                71587538                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               71587538                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1278                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1278                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1278                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       45985500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        45985500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       45985500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           71588816                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            71588816                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           71588816                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000018                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate           0.000018                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate          0.000018                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36041.503524                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36041.503524                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36041.503524                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 35982.394366                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35982.394366                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35982.394366                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -346,158 +346,158 @@ system.cpu.icache.writebacks                        0                       # nu
 system.cpu.icache.ReadReq_mshr_hits               337                       # number of ReadReq MSHR hits
 system.cpu.icache.demand_mshr_hits                337                       # number of demand (read+write) MSHR hits
 system.cpu.icache.overall_mshr_hits               337                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             940                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              940                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             940                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_misses             941                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              941                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             941                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     33513000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     33513000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     33513000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     33582500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     33582500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     33582500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000013                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000013                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate     0.000013                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35652.127660                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35652.127660                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35652.127660                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35688.097768                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35688.097768                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35688.097768                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 470805                       # number of replacements
-system.cpu.dcache.tagsinuse               4093.951768                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                151630549                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 474901                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 319.288755                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              126064000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4093.951768                       # Average occupied blocks per context
+system.cpu.dcache.replacements                 470793                       # number of replacements
+system.cpu.dcache.tagsinuse               4093.950327                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                151670470                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 474889                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 319.380887                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              126051000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4093.950327                       # Average occupied blocks per context
 system.cpu.dcache.occ_percent::0             0.999500                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              113482808                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              38147738                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits                3                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits               151630546                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              151630546                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               730789                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1303583                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               2034372                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2034372                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    11799719000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   19632109224                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     31431828224                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    31431828224                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          114213597                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits              113522942                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              38147524                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits                4                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits               151670466                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              151670466                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               730602                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1303797                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               2034399                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2034399                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    11799452000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   19635094216                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     31434546216                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    31434546216                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          114253544                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses          39451321                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses            3                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           153664918                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          153664918                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.006398                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.033043                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.013239                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.013239                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 16146.547088                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 15060.114488                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 15450.383816                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 15450.383816                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       917496                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses            4                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           153704865                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          153704865                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.006395                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.033048                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.013236                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.013236                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 16150.314398                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 15059.932042                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 15451.514780                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 15451.514780                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       884996                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets       236500                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               119                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               116                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              11                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  7710.050420                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  7629.275862                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets        21500                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   423137                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            511918                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1047553                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1559471                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1559471                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          218871                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         256030                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           474901                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          474901                       # number of overall MSHR misses
+system.cpu.dcache.writebacks                   423112                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            511747                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1047763                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1559510                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1559510                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          218855                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         256034                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           474889                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          474889                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1640511500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   3027783994                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   4668295494                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   4668295494                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   1640196500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   3028456494                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   4668652994                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   4668652994                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.001916                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.006490                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate      0.003090                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate     0.003090                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7495.335152                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11825.895379                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  9830.039301                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  9830.039301                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7494.443810                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11828.337229                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  9831.040504                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  9831.040504                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                 74456                       # number of replacements
-system.cpu.l2cache.tagsinuse             17669.602101                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  478138                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 90356                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  5.291713                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                 74461                       # number of replacements
+system.cpu.l2cache.tagsinuse             17667.693378                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  478022                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 90361                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.290136                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1747.606056                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15921.996045                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.053333                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.485901                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                186860                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              423137                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              196226                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 383086                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                383086                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               32951                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             59804                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                92755                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               92755                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1133426500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   2066052500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     3199479000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    3199479000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            219811                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          423137                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          256030                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             475841                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            475841                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.149906                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.233582                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.194929                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.194929                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34397.332403                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.062069                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34493.870950                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34493.870950                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs       468000                       # number of cycles access was blocked
+system.cpu.l2cache.occ_blocks::0          1746.744701                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15920.948677                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.053306                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.485869                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                186848                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              423112                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              196221                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 383069                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                383069                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               32948                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             59813                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                92761                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               92761                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1133336500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2066482500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     3199819000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    3199819000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            219796                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          423112                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          256034                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             475830                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            475830                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.149903                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.233614                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.194946                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.194946                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34397.732791                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34549.052881                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34495.305139                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34495.305139                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs       460000                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs               80                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs               71                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs         5850                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  6478.873239                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   59325                       # number of writebacks
+system.cpu.l2cache.writebacks                   59333                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          32951                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        59804                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           92755                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          92755                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses          32948                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        59813                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           92761                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          92761                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1022116000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1877697000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   2899813000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   2899813000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1022013500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1878097000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   2900110500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   2900110500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.149906                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.233582                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.194929                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.194929                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.271039                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31397.515216                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31263.144844                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31263.144844                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.149903                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.233614                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.194946                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.194946                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.984460                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31399.478374                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31264.329837                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31264.329837                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index f34e7fb17543c5122c910c7760c762eeb3db7668..eb566e6f8a0af8fc84c164778dcb18354c72ca31 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:18:43
-gem5 started Jul  9 2011 00:29:29
+gem5 compiled Jul 15 2011 18:02:03
+gem5 started Jul 16 2011 00:35:36
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -38,4 +38,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 182546630500 because target called exit()
+Exiting @ tick 181676511500 because target called exit()
index 79eb9dffa51f401b875473d14892eda8049f1c1f..212b723afa8a197baf94f455619be5626f74a72a 100644 (file)
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.182547                       # Number of seconds simulated
-sim_ticks                                182546630500                       # Number of ticks simulated
+sim_seconds                                  0.181677                       # Number of seconds simulated
+sim_ticks                                181676511500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  66837                       # Simulator instruction rate (inst/s)
-host_tick_rate                               20255145                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 257744                       # Number of bytes of host memory used
-host_seconds                                  9012.36                       # Real time elapsed on the host
-sim_insts                                   602359825                       # Number of instructions simulated
+host_inst_rate                                  82416                       # Simulator instruction rate (inst/s)
+host_tick_rate                               24857445                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257796                       # Number of bytes of host memory used
+host_seconds                                  7308.74                       # Real time elapsed on the host
+sim_insts                                   602359820                       # Number of instructions simulated
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -51,299 +51,299 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   48                       # Number of system calls
-system.cpu.numCycles                        365093262                       # number of cpu cycles simulated
+system.cpu.numCycles                        363353024                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 94055134                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           86414920                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            3979081                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              88956702                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 82512166                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 93642406                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           86055517                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            3937297                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              88612742                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 82226729                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  1838122                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                1832                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           80667890                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      724099412                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    94055134                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           84350288                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     163986224                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                21484785                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              102787887                       # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS                  1811116                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                1799                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           80077128                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      720176236                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    93642406                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           84037845                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     163199656                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                20933611                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              102893232                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                   28                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           614                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  78002853                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1602878                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          364227401                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.127111                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.977166                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles           623                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  77424762                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1579270                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          362477887                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.126441                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.976296                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                200241339     54.98%     54.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 25976483      7.13%     62.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 20067114      5.51%     67.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 25160816      6.91%     74.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 12370660      3.40%     77.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 13978922      3.84%     81.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  4846811      1.33%     83.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  7981089      2.19%     85.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 53604167     14.72%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                199278398     54.98%     54.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 25830413      7.13%     62.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 19932307      5.50%     67.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 25118126      6.93%     74.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 12539166      3.46%     77.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 13666852      3.77%     81.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  4829528      1.33%     83.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  7994396      2.21%     85.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 53288701     14.70%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            364227401                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.257619                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.983327                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                103328819                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              82990379                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 141956916                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              19169051                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               16782236                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              6955768                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  2559                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              762233872                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  7095                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               16782236                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                116716310                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                10162193                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         109463                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 147645122                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              72812077                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              747464015                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   176                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               58909213                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              10051058                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              590                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           771173910                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3477020106                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3477019978                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total            362477887                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.257717                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.982029                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                102756406                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              83077250                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 141158544                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              19181042                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               16304645                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              6938686                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  2613                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              758024516                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  7262                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               16304645                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                116075491                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                10185612                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         109358                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 146924183                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              72878598                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              743558817                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   188                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               58921601                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              10117687                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              591                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           767454765                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3458233737                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3458233609                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups               128                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             627417426                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                143756479                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               6432                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           6428                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 129949589                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            185066010                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            85818254                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          23013256                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         30486769                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  718960040                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                7404                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 670280843                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            854799                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       116155760                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    288576013                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1102                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     364227401                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.840281                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.715695                       # Number of insts issued each cycle
+system.cpu.rename.CommittedMaps             627417418                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                140037342                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               6399                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           6398                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 130096693                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            183828757                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            85345746                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          25811031                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         37497456                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  715547655                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                7366                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 667339389                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            840250                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       112563133                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    285197370                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1065                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     362477887                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.841049                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.675765                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            91766913     25.19%     25.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            93871528     25.77%     50.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            74118513     20.35%     71.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            44924126     12.33%     83.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            26194132      7.19%     90.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            19078510      5.24%     96.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             7890026      2.17%     98.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             5178547      1.42%     99.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1205106      0.33%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            89414922     24.67%     24.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            90190265     24.88%     49.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            79396670     21.90%     71.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            45359007     12.51%     83.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            28036434      7.73%     91.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            16328709      4.50%     96.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             8232346      2.27%     98.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             5060866      1.40%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              458668      0.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       364227401                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       362477887                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  168001      4.86%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2622016     75.82%     80.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                668303     19.32%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  175813      5.16%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2586346     75.94%     81.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                643459     18.89%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             415768758     62.03%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                 6559      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.03% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            175425484     26.17%     88.20% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            79080039     11.80%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             414934483     62.18%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                 6549      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.18% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            174108289     26.09%     88.27% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            78290065     11.73%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              670280843                       # Type of FU issued
-system.cpu.iq.rate                           1.835917                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     3458320                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.005160                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1709102170                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         835787693                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    655814402                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total              667339389                       # Type of FU issued
+system.cpu.iq.rate                           1.836614                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3405618                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.005103                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1701402497                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         828782976                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    653330026                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              673739143                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              670744987                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         28975081                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads         28288943                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     36113410                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       129451                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       665732                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     15597236                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     34876158                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       159827                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       665311                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     15124729                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        16028                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         12631                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        15440                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         12578                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               16782236                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  788804                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 51690                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           719036936                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           2011497                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             185066010                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             85818254                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               6071                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  13145                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  5072                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         665732                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        4120759                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       486329                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              4607088                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             662401467                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             171983852                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           7879376                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               16304645                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  784511                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 50454                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           715624477                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           2065189                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             183828757                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             85345746                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               6034                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  13250                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  5066                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         665311                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4094363                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       486296                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              4580659                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             659689382                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             170637671                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           7650007                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         69492                       # number of nop insts executed
-system.cpu.iew.exec_refs                    249361026                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 77022435                       # Number of branches executed
-system.cpu.iew.exec_stores                   77377174                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.814335                       # Inst execution rate
-system.cpu.iew.wb_sent                      657949131                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     655814418                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 425644511                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 661906658                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         69456                       # number of nop insts executed
+system.cpu.iew.exec_refs                    247330517                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 76920251                       # Number of branches executed
+system.cpu.iew.exec_stores                   76692846                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.815560                       # Inst execution rate
+system.cpu.iew.wb_sent                      655349780                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     653330042                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 425170180                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 661395893                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.796293                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.643058                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.798059                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.642838                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      602359876                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       116686609                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls            6302                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           4038424                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    347445166                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.733683                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.123903                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts      602359871                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       113270616                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls            6301                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           3996549                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    346173243                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.740053                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.116155                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    113764130     32.74%     32.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    109130175     31.41%     64.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     49680788     14.30%     78.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     10344875      2.98%     81.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     23361064      6.72%     88.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     14153772      4.07%     92.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8154815      2.35%     94.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1152882      0.33%     94.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     17702665      5.10%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    112054418     32.37%     32.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    109168598     31.54%     63.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     49782434     14.38%     78.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     10491888      3.03%     81.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     23443534      6.77%     88.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14637280      4.23%     92.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8029663      2.32%     94.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1511197      0.44%     95.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     17054231      4.93%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    347445166                       # Number of insts commited each cycle
-system.cpu.commit.count                     602359876                       # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total    346173243                       # Number of insts commited each cycle
+system.cpu.commit.count                     602359871                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      219173617                       # Number of memory references committed
-system.cpu.commit.loads                     148952599                       # Number of loads committed
+system.cpu.commit.refs                      219173615                       # Number of memory references committed
+system.cpu.commit.loads                     148952598                       # Number of loads committed
 system.cpu.commit.membars                        1328                       # Number of memory barriers committed
-system.cpu.commit.branches                   70828606                       # Number of branches committed
+system.cpu.commit.branches                   70828605                       # Number of branches committed
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 533522659                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 533522655                       # Number of committed integer instructions.
 system.cpu.commit.function_calls               997573                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              17702665                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              17054231                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1048788374                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1454922610                       # The number of ROB writes
-system.cpu.timesIdled                           36904                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          865861                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   602359825                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             602359825                       # Number of Instructions Simulated
-system.cpu.cpi                               0.606105                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.606105                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.649879                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.649879                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3307885763                       # number of integer regfile reads
-system.cpu.int_regfile_writes               680907350                       # number of integer regfile writes
+system.cpu.rob.rob_reads                   1044748887                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1447602374                       # The number of ROB writes
+system.cpu.timesIdled                           36933                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          875137                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   602359820                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             602359820                       # Number of Instructions Simulated
+system.cpu.cpi                               0.603216                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.603216                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.657781                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.657781                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3292742614                       # number of integer regfile reads
+system.cpu.int_regfile_writes               679039343                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               966917605                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                   2666                       # number of misc regfile writes
-system.cpu.icache.replacements                     48                       # number of replacements
-system.cpu.icache.tagsinuse                654.116997                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 78001834                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    767                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               101697.306389                       # Average number of references to valid blocks.
+system.cpu.misc_regfile_reads               961073357                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                   2664                       # number of misc regfile writes
+system.cpu.icache.replacements                     52                       # number of replacements
+system.cpu.icache.tagsinuse                658.859257                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 77423742                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    777                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               99644.455598                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            654.116997                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.319393                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               78001834                       # number of ReadReq hits
-system.cpu.icache.demand_hits                78001834                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               78001834                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1019                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1019                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1019                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       35576500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        35576500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       35576500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           78002853                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            78002853                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           78002853                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0            658.859257                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.321709                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               77423742                       # number of ReadReq hits
+system.cpu.icache.demand_hits                77423742                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               77423742                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1020                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1020                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1020                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       35800500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        35800500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       35800500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           77424762                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            77424762                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           77424762                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000013                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate           0.000013                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate          0.000013                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 34913.150147                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 34913.150147                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 34913.150147                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 35098.529412                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35098.529412                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35098.529412                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -353,67 +353,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               252                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                252                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               252                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             767                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              767                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             767                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits               243                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                243                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               243                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             777                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              777                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             777                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     26271000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     26271000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     26271000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     26636000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     26636000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     26636000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000010                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate     0.000010                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34251.629726                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34251.629726                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34251.629726                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34280.566281                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34280.566281                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34280.566281                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 440983                       # number of replacements
-system.cpu.dcache.tagsinuse               4094.790768                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                209375241                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 445079                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 470.422646                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               87857000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4094.790768                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999705                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              141476381                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              67896188                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits             1340                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits              1332                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits               209372569                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              209372569                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               248779                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1521343                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses             10                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses               1770122                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              1770122                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     3280245000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   26835404025                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency       198500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency     30115649025                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    30115649025                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          141725160                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                 440951                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.785016                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                208890975                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 445047                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 469.368348                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               87843000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4094.785016                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999703                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              140815101                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              68073201                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits             1342                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits              1331                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               208888302                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              208888302                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               248858                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1344330                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              9                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses               1593188                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1593188                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     3280375500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   26109782527                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency       194000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency     29390158027                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    29390158027                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          141063959                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses          69417531                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses         1350                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses          1332                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           211142691                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          211142691                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.001755                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.021916                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.007407                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.008384                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.008384                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 13185.377383                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 17639.285832                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency        19850                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 17013.318305                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 17013.318305                       # average overall miss latency
+system.cpu.dcache.LoadLockedReq_accesses         1351                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses          1331                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           210481490                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          210481490                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.001764                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.019366                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.006662                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.007569                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.007569                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 13181.716079                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 19422.152691                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 21555.555556                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 18447.388524                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 18447.388524                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs      9583027                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs              2185                       # number of cycles access was blocked
@@ -422,70 +422,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs  4385.824714
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   395060                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits             51069                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1273974                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits           10                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1325043                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1325043                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          197710                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         247369                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           445079                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          445079                       # number of overall MSHR misses
+system.cpu.dcache.writebacks                   395037                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits             51168                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1096973                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits            9                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1148141                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1148141                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          197690                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         247357                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           445047                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          445047                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1624301000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   2561171527                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   4185472527                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   4185472527                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   1624799500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   2561111027                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   4185910527                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   4185910527                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001395                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001401                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.003563                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.002108                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.002108                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8215.573314                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10353.647898                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  9403.886786                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  9403.886786                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate      0.002114                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.002114                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8218.926096                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10353.905598                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  9405.547115                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  9405.547115                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                 72980                       # number of replacements
-system.cpu.l2cache.tagsinuse             17828.973663                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  421802                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 88512                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  4.765478                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                 72983                       # number of replacements
+system.cpu.l2cache.tagsinuse             17823.829612                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  421659                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 88508                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  4.764078                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1911.988295                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15916.985368                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.058349                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.485748                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                165669                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              395060                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              188996                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 354665                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                354665                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               32802                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             58379                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                91181                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               91181                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1126009000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   2004629500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     3130638500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    3130638500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            198471                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          395060                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          247375                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             445846                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            445846                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.165274                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.235994                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.204512                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.204512                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34327.449546                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34338.195241                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34334.329520                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34334.329520                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::0          1903.131187                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15920.698425                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.058079                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.485861                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                165659                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              395037                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              188979                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 354638                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                354638                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               32805                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             58381                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                91186                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               91186                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1126836000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2004580000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     3131416000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    3131416000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            198464                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          395037                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          247360                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             445824                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            445824                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.165294                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.236016                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.204534                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.204534                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34349.519890                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34336.171015                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34340.973395                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34340.973395                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs      2057500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs              352                       # number of cycles access was blocked
@@ -494,28 +494,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs  5845.170455
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   58140                       # number of writebacks
+system.cpu.l2cache.writebacks                   58139                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits                9                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits                 9                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                9                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          32793                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        58379                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           91172                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          91172                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses          32796                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        58381                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           91177                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          91177                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1019413500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1823005500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   2842419000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   2842419000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1020208500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1822855000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   2843063500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   2843063500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165228                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235994                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.204492                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.204492                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31086.314152                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31227.076517                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31176.446716                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31176.446716                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165249                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.236016                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.204513                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.204513                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31107.711306                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31223.428855                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31181.805719                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31181.805719                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 589c8ec4cff540577f4058eb29e0270ef611405d..a3848a02310268cf0e8a8e6dc730e57543d77218 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:08:13
-gem5 started Jul  8 2011 18:26:23
+gem5 compiled Jul 18 2011 18:04:45
+gem5 started Jul 18 2011 18:04:49
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -38,4 +38,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 563588156500 because target called exit()
+Exiting @ tick 568878317500 because target called exit()
index d52982e265a01360ac69d3ace3dd34cba0d24a31..cb1a626e148cd8ad092793ba84c4cd51b933d446 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.563588                       # Number of seconds simulated
-sim_ticks                                563588156500                       # Number of ticks simulated
+sim_seconds                                  0.568878                       # Number of seconds simulated
+sim_ticks                                568878317500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  64765                       # Simulator instruction rate (inst/s)
-host_tick_rate                               25968064                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 251156                       # Number of bytes of host memory used
-host_seconds                                 21703.13                       # Real time elapsed on the host
+host_inst_rate                                 127390                       # Simulator instruction rate (inst/s)
+host_tick_rate                               51557660                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254284                       # Number of bytes of host memory used
+host_seconds                                 11033.83                       # Real time elapsed on the host
 sim_insts                                  1405604152                       # Number of instructions simulated
 system.cpu.workload.num_syscalls                   49                       # Number of system calls
-system.cpu.numCycles                       1127176314                       # number of cpu cycles simulated
+system.cpu.numCycles                       1137756636                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                108002078                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           96458356                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            5419443                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             104845979                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                103526655                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                106888514                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           95381218                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            5420176                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             103841112                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                102522993                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                     1233                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.usedRAS                     1230                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                 218                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          182291160                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1787208152                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   108002078                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          103527888                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     384452467                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                39306331                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              526780202                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   13                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1622                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 177554256                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1007248                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1126809005                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.590132                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.768689                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          180638334                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1773593568                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   106888514                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          102524223                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     381465937                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                37837382                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              543268181                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   17                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1639                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 176102907                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                948661                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1137451065                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.563275                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.753191                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                742356538     65.88%     65.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 85341479      7.57%     73.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 46929286      4.16%     77.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 24554385      2.18%     79.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 34670829      3.08%     82.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 34912206      3.10%     85.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 15372705      1.36%     87.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  7941055      0.70%     88.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                134730522     11.96%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                755985128     66.46%     66.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 84858619      7.46%     73.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 46317326      4.07%     78.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 24386522      2.14%     80.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 34286806      3.01%     83.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 34702861      3.05%     86.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 15288834      1.34%     87.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  7898837      0.69%     88.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                133726132     11.76%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1126809005                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.095816                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.585562                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                243483307                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             469211226                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 329903735                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              50927196                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               33283541                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             1773785354                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               33283541                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                303199519                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               121005551                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       66378557                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 319425533                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             283516304                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1755376544                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     1                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents              158155356                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              64460520                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents         40367810                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1464774447                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2963679380                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       2929648556                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          34030824                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1137451065                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.093947                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.558851                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                242051252                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             485212822                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 328784553                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              49325481                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               32076957                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             1761674668                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               32076957                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                305517434                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               121834770                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       66846353                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 312365178                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             298810373                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1743986914                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents              179337186                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              63010596                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents         40441846                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1455333902                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2943882462                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2909924571                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          33957891                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1244770452                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                220003995                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            3335169                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        3335909                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 507197291                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            473956598                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           190918944                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         402921595                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        162419763                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1626020867                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             3211854                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1494042135                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            206172                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       223169277                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    302404283                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         968183                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1126809005                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.325905                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.154571                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                210563450                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            3348344                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        3348760                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 542381303                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            470273369                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           190181130                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         405202372                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        165490113                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1617272450                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             3218242                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1489328778                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             68047                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       214120992                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    291680058                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         974571                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1137451065                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.309356                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.140672                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           292007700     25.91%     25.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           411780858     36.54%     62.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           263168713     23.36%     85.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           101528512      9.01%     94.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            43990451      3.90%     98.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            11374555      1.01%     99.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2356617      0.21%     99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              448758      0.04%     99.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              152841      0.01%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           308893636     27.16%     27.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           389103497     34.21%     61.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           284410316     25.00%     86.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           106768220      9.39%     95.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            33533421      2.95%     98.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            12093348      1.06%     99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2169743      0.19%     99.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              349965      0.03%     99.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              128919      0.01%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1126809005                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1137451065                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  276548      8.36%      8.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      8.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                151088      4.56%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     12.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2447279     73.94%     86.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                434986     13.14%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  267660      8.55%      8.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      8.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                151678      4.84%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     13.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2460340     78.58%     91.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                251345      8.03%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             893364457     59.80%     59.80% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     59.80% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     59.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             2623126      0.18%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            426278234     28.53%     88.50% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           171776318     11.50%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             892252171     59.91%     59.91% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     59.91% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     59.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2624686      0.18%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            423006461     28.40%     88.49% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           171445460     11.51%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1494042135                       # Type of FU issued
-system.cpu.iq.rate                           1.325473                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     3309901                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.002215                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4100596899                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1843738328                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1474876541                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            17812449                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            9274219                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      8514769                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1488163197                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 9188839                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        140932048                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1489328778                       # Type of FU issued
+system.cpu.iq.rate                           1.309005                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3131023                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.002102                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4101702594                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1825725243                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1471768719                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            17605097                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            9240911                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      8506597                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1483444207                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 9015594                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        136711373                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     71443754                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        20242                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       695476                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     24070802                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     67760525                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        20730                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       356316                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     23332988                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads          267                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         39866                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads           60                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         46765                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               33283541                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 2642816                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                166342                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1732819113                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           4184603                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             473956598                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            190918944                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            3110022                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  73740                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  9229                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         695476                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        5255230                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       461002                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              5716232                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1486789752                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             422968775                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           7252383                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               32076957                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2310683                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 98308                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1723301655                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           4186060                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             470273369                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            190181130                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            3115724                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  51873                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  4910                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         356316                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        5266619                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       459051                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              5725670                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1483096593                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             420520679                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           6232185                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     103586392                       # number of nop insts executed
-system.cpu.iew.exec_refs                    593427321                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 90250072                       # Number of branches executed
-system.cpu.iew.exec_stores                  170458546                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.319039                       # Inst execution rate
-system.cpu.iew.wb_sent                     1484841678                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1483391310                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1170940676                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1222219030                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     102810963                       # number of nop insts executed
+system.cpu.iew.exec_refs                    590732580                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 90117242                       # Number of branches executed
+system.cpu.iew.exec_stores                  170211901                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.303527                       # Inst execution rate
+system.cpu.iew.wb_sent                     1481375672                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1480275316                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1168908244                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1211941530                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.316024                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.958045                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.301047                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.964492                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts     1489523295                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       243200723                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       233686324                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         2243671                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           5419443                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1093526075                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.362129                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.820328                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           5420176                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1105374719                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.347528                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.786900                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    386645364     35.36%     35.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    450467032     41.19%     76.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     52266567      4.78%     81.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     95504499      8.73%     90.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     32424023      2.97%     93.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      8856558      0.81%     93.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     27482733      2.51%     96.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      9900040      0.91%     97.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     29979259      2.74%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    387659384     35.07%     35.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    461508986     41.75%     76.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     51139183      4.63%     81.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     98630108      8.92%     90.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     32299027      2.92%     93.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      8730687      0.79%     94.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     27864776      2.52%     96.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     10533124      0.95%     97.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     27009444      2.44%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1093526075                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1105374719                       # Number of insts commited each cycle
 system.cpu.commit.count                    1489523295                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      569360986                       # Number of memory references committed
@@ -256,50 +255,50 @@ system.cpu.commit.branches                   86248929                       # Nu
 system.cpu.commit.fp_insts                    8452036                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1319476388                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1206914                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              29979259                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              27009444                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2796205964                       # The number of ROB reads
-system.cpu.rob.rob_writes                  3498772696                       # The number of ROB writes
-system.cpu.timesIdled                           11331                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          367309                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   2801510024                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3478548339                       # The number of ROB writes
+system.cpu.timesIdled                           10892                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          305571                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1405604152                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1405604152                       # Number of Instructions Simulated
-system.cpu.cpi                               0.801916                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.801916                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.247014                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.247014                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2006108330                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1306606440                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  16974388                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 10441040                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               599300610                       # number of misc regfile reads
+system.cpu.cpi                               0.809443                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.809443                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.235417                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.235417                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2001717837                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1303407681                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  16935756                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 10440358                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               596613763                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                2258933                       # number of misc regfile writes
-system.cpu.icache.replacements                    162                       # number of replacements
-system.cpu.icache.tagsinuse               1043.489653                       # Cycle average of tags in use
-system.cpu.icache.total_refs                177552476                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   1297                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               136894.738628                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                    165                       # number of replacements
+system.cpu.icache.tagsinuse               1040.317886                       # Cycle average of tags in use
+system.cpu.icache.total_refs                176101137                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   1300                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               135462.413077                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1043.489653                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.509516                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              177552476                       # number of ReadReq hits
-system.cpu.icache.demand_hits               177552476                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              177552476                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1780                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1780                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1780                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       62084000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        62084000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       62084000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          177554256                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           177554256                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          177554256                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0           1040.317886                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.507968                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              176101137                       # number of ReadReq hits
+system.cpu.icache.demand_hits               176101137                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              176101137                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1770                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1770                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1770                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       61911500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        61911500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       61911500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          176102907                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           176102907                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          176102907                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000010                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate           0.000010                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate          0.000010                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 34878.651685                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 34878.651685                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 34878.651685                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 34978.248588                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 34978.248588                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 34978.248588                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -309,140 +308,140 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               482                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                482                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               482                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            1298                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             1298                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            1298                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits               469                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                469                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               469                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            1301                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             1301                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            1301                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     45208500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     45208500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     45208500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     45277500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     45277500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     45277500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000007                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000007                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate     0.000007                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34829.352851                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34829.352851                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34829.352851                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34802.075327                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34802.075327                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34802.075327                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 475456                       # number of replacements
-system.cpu.dcache.tagsinuse               4095.394464                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                446158150                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 479552                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 930.364486                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              131008000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4095.394464                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999852                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              281189388                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             164967443                       # number of WriteReq hits
+system.cpu.dcache.replacements                 475458                       # number of replacements
+system.cpu.dcache.tagsinuse               4095.400143                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                447983825                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 479554                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 934.167633                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              131001000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4095.400143                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999854                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              282962670                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             165019836                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits                   1319                       # number of SwapReq hits
-system.cpu.dcache.demand_hits               446156831                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              446156831                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               816269                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1879373                       # number of WriteReq misses
+system.cpu.dcache.demand_hits               447982506                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              447982506                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               815560                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1826980                       # number of WriteReq misses
 system.cpu.dcache.SwapReq_misses                    7                       # number of SwapReq misses
-system.cpu.dcache.demand_misses               2695642                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2695642                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    11972698500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   28858348258                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency         267000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency     40831046758                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    40831046758                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          282005657                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses               2642540                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2642540                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    10724956500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   26607670410                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency         266500                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency     37332626910                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    37332626910                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          283778230                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses         166846816                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses               1326                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           448852473                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          448852473                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.002895                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.011264                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses           450625046                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          450625046                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.002874                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.010950                       # miss rate for WriteReq accesses
 system.cpu.dcache.SwapReq_miss_rate          0.005279                       # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate           0.006006                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.006006                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 14667.589361                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 15355.306402                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency 38142.857143                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 15147.058385                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 15147.058385                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         4500                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate           0.005864                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.005864                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 13150.419957                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 14563.744765                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency 38071.428571                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 14127.554137                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 14127.554137                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         9500                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets         3000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs         2250                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs         2375                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets         3000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   426829                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            604140                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1611957                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            2216097                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           2216097                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          212129                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         267416                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks                   426814                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            603466                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1559527                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            2162993                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           2162993                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          212094                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         267453                       # number of WriteReq MSHR misses
 system.cpu.dcache.SwapReq_mshr_misses               7                       # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           479545                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          479545                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses           479547                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          479547                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1590330500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   3553768773                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency       246000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   5144099273                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   5144099273                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   1622799000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   3442234519                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency       245500                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   5065033519                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   5065033519                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000752                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000747                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.001603                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SwapReq_mshr_miss_rate     0.005279                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.001068                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.001068                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7496.997110                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13289.289994                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35142.857143                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 10727.041827                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 10727.041827                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate      0.001064                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.001064                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7651.319698                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12870.427772                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35071.428571                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 10562.121166                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 10562.121166                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                 75860                       # number of replacements
-system.cpu.l2cache.tagsinuse             17695.918496                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  464712                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 91372                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  5.085934                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                 75848                       # number of replacements
+system.cpu.l2cache.tagsinuse             17699.311990                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  464479                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 91359                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.084108                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1941.337449                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15754.581047                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.059245                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.480792                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                179775                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              426829                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              206986                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 386761                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                386761                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               33652                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             60437                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                94089                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               94089                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1145407000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   2080656500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     3226063500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    3226063500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            213427                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          426829                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          267423                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             480850                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            480850                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.157675                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.225998                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.195672                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.195672                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34036.818020                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34426.865993                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34287.360903                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34287.360903                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::0          1967.262312                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15732.049678                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.060036                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.480104                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                179745                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              426814                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              207036                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 386781                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                386781                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               33650                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             60424                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                94074                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               94074                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1149817000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2071878000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     3221695000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    3221695000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            213395                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          426814                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          267460                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             480855                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            480855                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.157689                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.225918                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.195639                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.195639                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34169.895988                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34288.991129                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34246.391139                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34246.391139                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -451,27 +450,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   59276                       # number of writebacks
+system.cpu.l2cache.writebacks                   59264                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          33652                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        60437                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           94089                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          94089                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses          33650                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        60424                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           94074                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          94074                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1043368500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1893759500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   2937128000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   2937128000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1044115000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1884920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   2929035000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   2929035000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.157675                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.225998                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.195672                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.195672                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.650541                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31334.439168                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31216.486518                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31216.486518                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.157689                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.225918                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.195639                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.195639                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31028.677563                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31194.889448                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31135.435933                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31135.435933                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 621f09656d15f1746a8f1c549274506cac7d94b4..a4b9477d127cb15a27113d415063a0844266508c 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:18:15
-gem5 started Jul  8 2011 19:12:13
+gem5 compiled Jul 15 2011 18:01:24
+gem5 started Jul 15 2011 20:50:21
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -1062,4 +1062,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 746999805000 because target called exit()
+Exiting @ tick 749294021000 because target called exit()
index b33faa13587dee667725c05a6fc5ad9dfea8ffe0..06ad1be7c56f2d869f609d0c7e0577a1e1898e20 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.747000                       # Number of seconds simulated
-sim_ticks                                746999805000                       # Number of ticks simulated
+sim_seconds                                  0.749294                       # Number of seconds simulated
+sim_ticks                                749294021000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  52755                       # Simulator instruction rate (inst/s)
-host_tick_rate                               24303440                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 253604                       # Number of bytes of host memory used
-host_seconds                                 30736.38                       # Real time elapsed on the host
+host_inst_rate                                  60097                       # Simulator instruction rate (inst/s)
+host_tick_rate                               27771108                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253640                       # Number of bytes of host memory used
+host_seconds                                 26981.06                       # Real time elapsed on the host
 sim_insts                                  1621493982                       # Number of instructions simulated
 system.cpu.workload.num_syscalls                   48                       # Number of system calls
-system.cpu.numCycles                       1493999611                       # number of cpu cycles simulated
+system.cpu.numCycles                       1498588043                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                183981284                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          183981284                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            7273832                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             175979129                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                174823422                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                174353147                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          174353147                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            8954437                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             165220115                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                164182726                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          199101325                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1418187336                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   183981284                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          174823422                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     411931747                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               120581871                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              775842898                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   72                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           439                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 187933146                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1412014                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1493732032                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.734289                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.070436                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          197081055                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1427085390                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   174353147                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          164182726                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     405643185                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               122961003                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              787624963                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   51                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           296                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 184521623                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1125658                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1498287760                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.715646                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.067557                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1084944891     72.63%     72.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 27695152      1.85%     74.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 18612240      1.25%     75.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 16931022      1.13%     76.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 30747713      2.06%     78.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 17254642      1.16%     80.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 38005540      2.54%     82.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 38774045      2.60%     85.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                220766787     14.78%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1095772488     73.13%     73.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 26898081      1.80%     74.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 18204566      1.22%     76.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 17325497      1.16%     77.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 23844032      1.59%     78.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 17164690      1.15%     80.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 40138916      2.68%     82.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 38301790      2.56%     85.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                220637700     14.73%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1493732032                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.123147                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.949255                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                299784199                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             683008972                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 314849688                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              89233622                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              106855551                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2563435147                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles              106855551                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                360599256                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               188215169                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           3353                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 328972953                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             509085750                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2506842740                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1358                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents              353300714                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents             135977984                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2507364398                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            6062894034                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       6062889786                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              4248                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1498287760                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.116345                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.952287                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                300082946                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             691709075                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 302993844                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              95563685                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              107938210                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2548886917                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles              107938210                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                357219052                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               188499779                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           3288                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 326836039                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             517791392                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2482037348                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  3801                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              365556322                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             131873603                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2483397127                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            6018409804                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       6018402452                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              7352                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1617994650                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                889369748                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                162                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            162                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 860776772                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            644217579                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           260359160                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         564219162                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        219825369                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2437807916                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  95                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1879814445                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            473311                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       816283522                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1731057121                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             45                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1493732032                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.258468                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.208875                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                865402477                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                169                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            169                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 866525950                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            641640659                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           260570368                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         562700768                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        217406187                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2410485981                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  96                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1860645622                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            297905                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       788955121                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1689446934                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             46                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1498287760                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.241848                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.192555                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           432191127     28.93%     28.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           591005322     39.57%     68.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           246823296     16.52%     85.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           135579868      9.08%     94.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            59328852      3.97%     98.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            22913004      1.53%     99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             4862881      0.33%     99.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              856243      0.06%     99.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              171439      0.01%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           431380009     28.79%     28.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           604501817     40.35%     69.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           252266719     16.84%     85.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           123988851      8.28%     94.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            58817201      3.93%     98.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            20817096      1.39%     99.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             5535754      0.37%     99.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              767498      0.05%     99.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              212815      0.01%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1493732032                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1498287760                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  145103      3.04%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                3853337     80.69%     83.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                777052     16.27%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  150800      3.27%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                3625649     78.65%     81.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                833140     18.07%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass          26397138      1.40%      1.40% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1212079345     64.48%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.88% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            449002654     23.89%     89.77% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           192335308     10.23%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass          28076414      1.51%      1.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1193303219     64.13%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.64% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            446918343     24.02%     89.66% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           192347646     10.34%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1879814445                       # Type of FU issued
-system.cpu.iq.rate                           1.258243                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     4775492                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.002540                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5258609690                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3260533161                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1853774167                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                  35                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               1274                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total             1860645622                       # Type of FU issued
+system.cpu.iq.rate                           1.241599                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     4609589                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.002477                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5224486461                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3205506305                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1835062624                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                  37                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               2036                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           12                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1858192780                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                      19                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        120571651                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses             1837178777                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        118533940                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    225175454                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         6636                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation      6448917                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     72173103                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    222598534                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         4428                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation      6067505                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     72384311                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads           67                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         30868                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads           48                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         30883                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              106855551                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 4276997                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                154006                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2437808011                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           3809571                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             644217579                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            260359160                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 95                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  92996                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    17                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents        6448917                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        4522013                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      2931532                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              7453545                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1858657499                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             444749829                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          21156946                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles              107938210                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 4267962                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                121894                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2410486077                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            630348                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             641640659                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            260570368                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 96                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  66625                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    20                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents        6067505                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4521579                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      4614873                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              9136452                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1840276566                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             443019520                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          20369056                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    636612361                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                111987428                       # Number of branches executed
-system.cpu.iew.exec_stores                  191862532                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.244082                       # Inst execution rate
-system.cpu.iew.wb_sent                     1856615108                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1853774179                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1441885120                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2107634936                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    634826939                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                111934330                       # Number of branches executed
+system.cpu.iew.exec_stores                  191807419                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.228007                       # Inst execution rate
+system.cpu.iew.wb_sent                     1838313315                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1835062636                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1427807499                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2086812885                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.240813                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.684125                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.224528                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.684205                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts     1621493982                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       816323432                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       789002361                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              50                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           7273892                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1386876481                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.169170                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.394530                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           8954478                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1390349550                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.166249                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.425241                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    510181205     36.79%     36.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    529583219     38.19%     74.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    122943422      8.86%     83.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3    138376651      9.98%     93.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     42654329      3.08%     96.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     24144434      1.74%     98.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      5177613      0.37%     99.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2036062      0.15%     99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11779546      0.85%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    517686759     37.23%     37.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    532094045     38.27%     75.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    126340876      9.09%     84.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3    122997225      8.85%     93.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     42691092      3.07%     96.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     23602651      1.70%     98.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      4988906      0.36%     98.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     10568517      0.76%     99.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      9379479      0.67%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1386876481                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1390349550                       # Number of insts commited each cycle
 system.cpu.commit.count                    1621493982                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      607228182                       # Number of memory references committed
@@ -255,48 +255,48 @@ system.cpu.commit.branches                  107161579                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1621354492                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              11779546                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               9379479                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3812914349                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4982493999                       # The number of ROB writes
-system.cpu.timesIdled                           44138                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          267579                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3791466414                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4929477020                       # The number of ROB writes
+system.cpu.timesIdled                           44919                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          300283                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1621493982                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1621493982                       # Number of Instructions Simulated
-system.cpu.cpi                               0.921372                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.921372                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.085338                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.085338                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3240601354                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1846777221                       # number of integer regfile writes
+system.cpu.cpi                               0.924202                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.924202                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.082014                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.082014                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3236351438                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1827281055                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        12                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               936479302                       # number of misc regfile reads
+system.cpu.misc_regfile_reads               926454727                       # number of misc regfile reads
 system.cpu.icache.replacements                     14                       # number of replacements
-system.cpu.icache.tagsinuse                820.004984                       # Cycle average of tags in use
-system.cpu.icache.total_refs                187931883                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    908                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               206973.439427                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                821.249711                       # Cycle average of tags in use
+system.cpu.icache.total_refs                184520340                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    906                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               203664.834437                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            820.004984                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.400393                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              187931883                       # number of ReadReq hits
-system.cpu.icache.demand_hits               187931883                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              187931883                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1263                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1263                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1263                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       44191500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        44191500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       44191500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          187933146                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           187933146                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          187933146                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0            821.249711                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.401001                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              184520379                       # number of ReadReq hits
+system.cpu.icache.demand_hits               184520379                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              184520379                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1244                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1244                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1244                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       43837000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        43837000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       43837000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          184521623                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           184521623                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          184521623                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000007                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate           0.000007                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate          0.000007                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 34989.311164                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 34989.311164                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 34989.311164                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 35238.745981                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35238.745981                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35238.745981                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -306,159 +306,159 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               355                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                355                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               355                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits               336                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                336                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               336                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses             908                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses              908                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses             908                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     32070500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     32070500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     32070500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     32023000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     32023000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     32023000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000005                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000005                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate     0.000005                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35319.933921                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35319.933921                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35319.933921                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35267.621145                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35267.621145                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35267.621145                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 459464                       # number of replacements
-system.cpu.dcache.tagsinuse               4095.142322                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                510865684                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 463560                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                1102.048675                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              317747000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4095.142322                       # Average occupied blocks per context
+system.cpu.dcache.replacements                 459267                       # number of replacements
+system.cpu.dcache.tagsinuse               4095.145013                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                511187603                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 463363                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                1103.211959                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              317737000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4095.145013                       # Average occupied blocks per context
 system.cpu.dcache.occ_percent::0             0.999791                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              323944700                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             186920984                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               510865684                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              510865684                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               217118                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1265073                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               1482191                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              1482191                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     2201155000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   24662905498                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     26864060498                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    26864060498                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          324161818                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits              324252389                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             186935214                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               511187603                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              511187603                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               216893                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1250843                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               1467736                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1467736                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     2202140000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   24456528497                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     26658668497                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    26658668497                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          324469282                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses         188186057                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           512347875                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          512347875                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000670                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.006722                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.002893                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.002893                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 10138.058567                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 19495.242961                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 18124.560531                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 18124.560531                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      1608500                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets    471924500                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               447                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           29514                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  3598.434004                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 15989.852273                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses           512655339                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          512655339                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000668                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.006647                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.002863                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.002863                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 10153.116975                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 19552.036904                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 18163.122317                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 18163.122317                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      1683000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets    471232500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               455                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           29502                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  3698.901099                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 15972.900142                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   410359                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits              3236                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1015395                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1018631                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1018631                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          213882                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         249678                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           463560                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          463560                       # number of overall MSHR misses
+system.cpu.dcache.writebacks                   410236                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits              3187                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1001186                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1004373                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1004373                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          213706                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         249657                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           463363                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          463363                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1535369000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   2499634500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   4035003500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   4035003500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   1537618500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   2504912000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   4042530500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   4042530500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000660                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000659                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.001327                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000905                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000905                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7178.579778                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10011.432725                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  8704.382388                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  8704.382388                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate      0.000904                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000904                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7195.017922                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10033.413844                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  8724.327363                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  8724.327363                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                 73641                       # number of replacements
-system.cpu.l2cache.tagsinuse             18052.437933                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  453217                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 89251                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  5.078005                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                 73626                       # number of replacements
+system.cpu.l2cache.tagsinuse             18020.121122                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  453087                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 89234                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.077515                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1921.052649                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         16131.385284                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.058626                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.492291                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                181658                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              410359                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              190902                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 372560                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                372560                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               33126                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             58782                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                91908                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               91908                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1130437500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   2022399000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     3152836500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    3152836500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            214784                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          410359                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          249684                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             464468                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            464468                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.154229                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.235426                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.197878                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.197878                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34125.384894                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34405.072982                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34304.266223                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34304.266223                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs        77500                       # number of cycles access was blocked
+system.cpu.l2cache.occ_blocks::0          1915.061823                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         16105.059300                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.058443                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.491487                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                181487                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              410236                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              190884                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 372371                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                372371                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               33119                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             58779                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                91898                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               91898                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1130363000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2022275000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     3152638000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    3152638000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            214606                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          410236                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          249663                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             464269                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            464269                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.154325                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.235433                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.197941                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.197941                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34130.348139                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.719373                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34305.839082                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34305.839082                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs       116500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs               72                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs               95                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  1076.388889                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  1226.315789                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   58527                       # number of writebacks
+system.cpu.l2cache.writebacks                   58523                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          33126                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        58782                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           91908                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          91908                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses          33119                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        58779                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           91898                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          91898                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1027129500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1831638000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   2858767500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   2858767500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1026905500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1830910000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   2857815500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   2857815500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.154229                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235426                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.197878                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.197878                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.746966                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31159.844850                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31104.664447                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31104.664447                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.154325                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235433                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.197941                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.197941                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.537033                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31149.049831                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31097.689830                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31097.689830                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 298e17d0f5cbbb088da6ae6b79b055dd49c26d87..ce4b09a6a490df6a8d3a7f0adb8d8fea10809a47 100644 (file)
@@ -10,13 +10,13 @@ type=LinuxAlphaSystem
 children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/arm/scratch/sysexplr/dist/binaries/console
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/arm/scratch/sysexplr/dist/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -931,7 +931,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -951,7 +951,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -1080,7 +1080,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
index b594e76f77da93481e517b1d3c01e8b39f3f1796..e8efa052262020ebf915ff981ee0b6a23282bc2a 100755 (executable)
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
+Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  9 2011 03:11:31
-gem5 started Aug  9 2011 03:11:36
-gem5 executing on burrito
+gem5 compiled Aug 15 2011 20:24:21
+gem5 started Aug 15 2011 20:25:29
+gem5 executing on nadc-0270
 command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 107915000
-Exiting @ tick 1897528709500 because m5_exit instruction encountered
+info: Launching CPU 1 @ 98887000
+Exiting @ tick 1899411597500 because m5_exit instruction encountered
index 669f31e44821790f72cf17473fc05c52324e0969..2eeafd392724df0cc0cb2881168a62159160387d 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.897529                       # Number of seconds simulated
-sim_ticks                                1897528709500                       # Number of ticks simulated
+sim_seconds                                  1.899412                       # Number of seconds simulated
+sim_ticks                                1899411597500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 133002                       # Simulator instruction rate (inst/s)
-host_tick_rate                             4420145385                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 318652                       # Number of bytes of host memory used
-host_seconds                                   429.29                       # Real time elapsed on the host
-sim_insts                                    57096369                       # Number of instructions simulated
-system.l2c.replacements                        396849                       # number of replacements
-system.l2c.tagsinuse                     35842.640466                       # Cycle average of tags in use
-system.l2c.total_refs                         2454377                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        435040                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          5.641727                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                    9253572000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                 12439.136290                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                   328.499708                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                 23075.004468                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.189806                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.005013                       # Average percentage of cache occupancy
-system.l2c.occ_percent::2                    0.352097                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    1462245                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     390216                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1852461                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                   805889                       # number of Writeback hits
-system.l2c.Writeback_hits::total               805889                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                     158                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                     388                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 546                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0                    42                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1                    29                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                71                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0                   131406                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1                    39589                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               170995                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     1593651                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      429805                       # number of demand (read+write) hits
+host_inst_rate                                 123946                       # Simulator instruction rate (inst/s)
+host_tick_rate                             4137994790                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 343492                       # Number of bytes of host memory used
+host_seconds                                   459.02                       # Real time elapsed on the host
+sim_insts                                    56893410                       # Number of instructions simulated
+system.l2c.replacements                        397094                       # number of replacements
+system.l2c.tagsinuse                     35529.229053                       # Cycle average of tags in use
+system.l2c.total_refs                         2438232                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        432488                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          5.637687                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                    9244135000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0                 10221.529700                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                  2327.457536                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                 22980.241816                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.155968                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.035514                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.350651                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0                    1442413                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                     407625                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1850038                       # number of ReadReq hits
+system.l2c.Writeback_hits::0                   800001                       # number of Writeback hits
+system.l2c.Writeback_hits::total               800001                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                     188                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1                      71                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 259                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::0                    35                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::1                    35                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                70                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::0                   148509                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1                    19811                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               168320                       # number of ReadExReq hits
+system.l2c.demand_hits::0                     1590922                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                      427436                       # number of demand (read+write) hits
 system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2023456                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    1593651                       # number of overall hits
-system.l2c.overall_hits::1                     429805                       # number of overall hits
+system.l2c.demand_hits::total                 2018358                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                    1590922                       # number of overall hits
+system.l2c.overall_hits::1                     427436                       # number of overall hits
 system.l2c.overall_hits::2                          0                       # number of overall hits
-system.l2c.overall_hits::total                2023456                       # number of overall hits
-system.l2c.ReadReq_misses::0                   304910                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                     5378                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               310288                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  2801                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                  1482                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              4283                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::0                 670                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1                 687                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1357                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::0                 114075                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                  11670                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             125745                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    418985                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                     17048                       # number of demand (read+write) misses
+system.l2c.overall_hits::total                2018358                       # number of overall hits
+system.l2c.ReadReq_misses::0                   301840                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                     7227                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               309067                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                  3348                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1                   792                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              4140                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::0                 439                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::1                 492                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total             931                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::0                 106737                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1                  17826                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             124563                       # number of ReadExReq misses
+system.l2c.demand_misses::0                    408577                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                     25053                       # number of demand (read+write) misses
 system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                436033                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   418985                       # number of overall misses
-system.l2c.overall_misses::1                    17048                       # number of overall misses
+system.l2c.demand_misses::total                433630                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                   408577                       # number of overall misses
+system.l2c.overall_misses::1                    25053                       # number of overall misses
 system.l2c.overall_misses::2                        0                       # number of overall misses
-system.l2c.overall_misses::total               436033                       # number of overall misses
-system.l2c.ReadReq_miss_latency           16152594500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency           19106500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency          3089000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          6595991500                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency            22748586000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency           22748586000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                1767155                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 395594                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2162749                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0               805889                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           805889                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                2959                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1                1870                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            4829                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::0               712                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1               716                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1428                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               245481                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                51259                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           296740                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 2012636                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  446853                       # number of demand (read+write) accesses
+system.l2c.overall_misses::total               433630                       # number of overall misses
+system.l2c.ReadReq_miss_latency           16078822000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency            5852000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency          5401500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency          6533699500                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency            22612521500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency           22612521500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::0                1744253                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                 414852                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2159105                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0               800001                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           800001                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0                3536                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1                 863                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            4399                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::0               474                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::1               527                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1001                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0               255246                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                37637                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           292883                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0                 1999499                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                  452489                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2459489                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                2012636                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 446853                       # number of overall (read+write) accesses
+system.l2c.demand_accesses::total             2451988                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::0                1999499                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                 452489                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2459489                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.172543                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.013595                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.946604                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1           0.792513                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::0         0.941011                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1         0.959497                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.464700                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.227667                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.208177                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.038151                       # miss rate for demand accesses
+system.l2c.overall_accesses::total            2451988                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0              0.173048                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.017421                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.946833                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1           0.917729                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::0         0.926160                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::1         0.933586                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0            0.418173                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1            0.473630                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.204340                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.055367                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.208177                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.038151                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::0              0.204340                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.055367                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   52974.958184                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   3003457.512086                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::0   53269.354625                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   2224826.622388                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0  6821.313816                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 12892.375169                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0  1747.909200                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1  7388.888889                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::0  4610.447761                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::1  4496.360990                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::0 12304.100228                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::1 10978.658537                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 57821.534078                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 565209.211654                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 61213.070444                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 366526.394031                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    54294.511737                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    1334384.443923                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::0    55344.577644                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    902587.374765                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   54294.511737                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   1334384.443923                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0   55344.577644                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   902587.374765                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
@@ -138,100 +138,100 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          121454                       # number of writebacks
+system.l2c.writebacks                          122463                       # number of writebacks
 system.l2c.ReadReq_mshr_hits                       17                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits                        17                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits                       17                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                 310271                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                4283                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses              1357                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               125745                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  436016                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 436016                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_misses                 309050                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                4140                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses               931                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses               124563                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses                  433613                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                 433613                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency      12421352000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency     171391500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency     54292500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     5066425000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency       17487777000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency      17487777000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency    838216000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency   1556318498                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency   2394534498                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.175577                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         0.784317                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_latency      12366985500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency     165615000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency     37241500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency     5018687000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency       17385672500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency      17385672500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency    838004500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency   1515144998                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency   2353149498                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.177182                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         0.744964                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      1.447448                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1      2.290374                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0      1.170814                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1      4.797219                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.905899                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.895251                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.964135                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.766603                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       0.512239                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1       2.453130                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0       0.488012                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1       3.309589                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.216639                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          0.975748                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::0          0.216861                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          0.958284                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.216639                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         0.975748                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::0         0.216861                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         0.958284                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40033.880060                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.693906                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40009.211496                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40291.264066                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40108.108418                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40108.108418                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40016.131694                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40003.623188                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40001.611171                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40290.351067                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency  40094.906057                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40094.906057                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.replacements                     41698                       # number of replacements
-system.iocache.tagsinuse                     0.465119                       # Cycle average of tags in use
+system.iocache.replacements                     41701                       # number of replacements
+system.iocache.tagsinuse                     0.379564                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     41714                       # Sample count of references to valid blocks.
+system.iocache.sampled_refs                     41717                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              1708345431000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1                 0.465119                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.029070                       # Average percentage of cache occupancy
+system.iocache.warmup_cycle              1708346603000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::1                 0.379564                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.023723                       # Average percentage of cache occupancy
 system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
 system.iocache.overall_hits::0                      0                       # number of overall hits
 system.iocache.overall_hits::1                      0                       # number of overall hits
 system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.ReadReq_misses::1                  178                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              178                       # number of ReadReq misses
+system.iocache.ReadReq_misses::1                  179                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              179                       # number of ReadReq misses
 system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
 system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 41730                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41730                       # number of demand (read+write) misses
+system.iocache.demand_misses::1                 41731                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41731                       # number of demand (read+write) misses
 system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                41730                       # number of overall misses
-system.iocache.overall_misses::total            41730                       # number of overall misses
-system.iocache.ReadReq_miss_latency          20503998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency       5720495806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency         5740999804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency        5740999804                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::1                178                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            178                       # number of ReadReq accesses(hits+misses)
+system.iocache.overall_misses::1                41731                       # number of overall misses
+system.iocache.overall_misses::total            41731                       # number of overall misses
+system.iocache.ReadReq_miss_latency          20618998                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency       5720800806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency         5741419804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency        5741419804                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::1                179                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            179                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               41730                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41730                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::1               41731                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41731                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              41730                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41730                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::1              41731                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41731                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
@@ -241,37 +241,37 @@ system.iocache.overall_miss_rate::0          no_value                       # mi
 system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1       115191                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 115189.932961                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137670.769301                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137678.109501                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
 system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137574.881476                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137581.649230                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137574.881476                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137581.649230                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs      64616068                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs      64641068                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                10458                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                10457                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  6178.625741                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6181.607344                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                       41520                       # number of writebacks
+system.iocache.writebacks                       41522                       # number of writebacks
 system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
 system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.ReadReq_mshr_misses                178                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses                179                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses               41730                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses              41730                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses               41731                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses              41731                       # number of overall MSHR misses
 system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.ReadReq_mshr_miss_latency     11247998                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency   3559637996                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency    3570885994                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency   3570885994                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency     11310998                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3559941996                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    3571252994                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   3571252994                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
@@ -285,10 +285,10 @@ system.iocache.demand_mshr_miss_rate::total          inf                       #
 system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency        63191                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85667.067674                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency 85571.195639                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency 85571.195639                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency 63189.932961                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85674.383808                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85577.939517                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85577.939517                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
@@ -309,22 +309,22 @@ system.cpu0.dtb.fetch_hits                          0                       # IT
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     8560359                       # DTB read hits
-system.cpu0.dtb.read_misses                     29048                       # DTB read misses
-system.cpu0.dtb.read_acv                          513                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  619639                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5419292                       # DTB write hits
-system.cpu0.dtb.write_misses                     5351                       # DTB write misses
-system.cpu0.dtb.write_acv                         235                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 205704                       # DTB write accesses
-system.cpu0.dtb.data_hits                    13979651                       # DTB hits
-system.cpu0.dtb.data_misses                     34399                       # DTB misses
-system.cpu0.dtb.data_acv                          748                       # DTB access violations
-system.cpu0.dtb.data_accesses                  825343                       # DTB accesses
-system.cpu0.itb.fetch_hits                     968518                       # ITB hits
-system.cpu0.itb.fetch_misses                    28074                       # ITB misses
-system.cpu0.itb.fetch_acv                         865                       # ITB acv
-system.cpu0.itb.fetch_accesses                 996592                       # ITB accesses
+system.cpu0.dtb.read_hits                     8691348                       # DTB read hits
+system.cpu0.dtb.read_misses                     30841                       # DTB read misses
+system.cpu0.dtb.read_acv                          585                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  626526                       # DTB read accesses
+system.cpu0.dtb.write_hits                    5727483                       # DTB write hits
+system.cpu0.dtb.write_misses                     5665                       # DTB write misses
+system.cpu0.dtb.write_acv                         282                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 212486                       # DTB write accesses
+system.cpu0.dtb.data_hits                    14418831                       # DTB hits
+system.cpu0.dtb.data_misses                     36506                       # DTB misses
+system.cpu0.dtb.data_acv                          867                       # DTB access violations
+system.cpu0.dtb.data_accesses                  839012                       # DTB accesses
+system.cpu0.itb.fetch_hits                    1018007                       # ITB hits
+system.cpu0.itb.fetch_misses                    28254                       # ITB misses
+system.cpu0.itb.fetch_acv                         951                       # ITB acv
+system.cpu0.itb.fetch_accesses                1046261                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -337,275 +337,275 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       103762975                       # number of cpu cycles simulated
+system.cpu0.numCycles                       103036446                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups                12289120                       # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted          10322639                       # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect            425623                       # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups             11096319                       # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits                 5846860                       # Number of BTB hits
+system.cpu0.BPredUnit.lookups                12345310                       # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted          10395868                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect            412413                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups             11143165                       # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits                 5756291                       # Number of BTB hits
 system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS                  811980                       # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect              29936                       # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles          23947551                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      63604775                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   12289120                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           6658840                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     12410125                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1977970                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles              32452881                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles               32113                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       186103                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       333368                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles           97                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  7852316                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               261746                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples          70661432                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.900134                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.212081                       # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS                  808447                       # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect              32944                       # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles          25643568                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      63130050                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   12345310                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           6564738                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     12229123                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1931790                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles              31463202                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles               31044                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       192852                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       226876                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles           96                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  7797411                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               265802                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples          71034720                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.888721                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.206546                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                58251307     82.44%     82.44% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  861864      1.22%     83.66% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1790389      2.53%     86.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  838279      1.19%     87.38% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2691367      3.81%     91.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  597435      0.85%     92.03% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  679704      0.96%     92.99% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  792267      1.12%     94.11% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4158820      5.89%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                58805597     82.78%     82.78% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  896633      1.26%     84.05% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1683822      2.37%     86.42% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  790380      1.11%     87.53% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2590451      3.65%     91.18% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  578678      0.81%     91.99% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  651939      0.92%     92.91% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  969955      1.37%     94.27% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4067265      5.73%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            70661432                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.118435                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.612981                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                25283379                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             31920291                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 11354348                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles               836358                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1267055                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              507127                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                32392                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              62175948                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts                94044                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1267055                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                26303467                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               12206310                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      16544701                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 10563376                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              3776521                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              58802666                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 6783                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                552005                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents              1306234                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands           39659853                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             71942390                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        71601283                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           341107                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             33288864                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 6370981                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1352745                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        204336                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 10335573                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             9033738                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            5759436                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1575901                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         1714897                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  51649014                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1711174                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 50034185                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            62931                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        7150176                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      3852149                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved       1166094                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     70661432                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.708083                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.331294                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total            71034720                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.119815                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.612696                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                26620678                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             31169441                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 11195503                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles               833782                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1215315                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              497181                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                32875                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              61799188                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts                97991                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1215315                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                27633845                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               10392034                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      17602675                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 10482679                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              3708170                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              58338786                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 6838                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                387997                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents              1347242                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands           39031988                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             70900966                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        70475489                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           425477                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             33170605                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 5861375                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1485068                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        227968                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 10243220                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             9180149                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            6097470                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1603652                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         1903642                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  51204618                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1864754                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 49739725                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            70469                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        6805118                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      3728302                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved       1267762                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     71034720                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.700217                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.322322                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           48300171     68.35%     68.35% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            9930839     14.05%     82.41% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            4875287      6.90%     89.31% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            3134712      4.44%     93.74% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2288875      3.24%     96.98% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1259030      1.78%     98.77% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             656858      0.93%     99.69% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             168442      0.24%     99.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8              47218      0.07%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           48628565     68.46%     68.46% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           10107628     14.23%     82.69% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            4889823      6.88%     89.57% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            3044033      4.29%     93.86% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2225901      3.13%     96.99% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1246231      1.75%     98.74% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             700109      0.99%     99.73% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             154501      0.22%     99.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              37929      0.05%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       70661432                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       71034720                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  64961     14.10%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     14.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                248589     53.97%     68.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               147038     31.92%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  52156     10.93%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                267781     56.13%     67.06% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               157153     32.94%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             3305      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             34793099     69.54%     69.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               56077      0.11%     69.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     69.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd              13836      0.03%     69.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     69.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv               1652      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             8926243     17.84%     87.53% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5486267     10.97%     98.49% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess            753706      1.51%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             3328      0.01%      0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             33971995     68.30%     68.31% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               53580      0.11%     68.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.41% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd              15560      0.03%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv               1654      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             9077168     18.25%     86.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5791424     11.64%     98.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            825016      1.66%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              50034185                       # Type of FU issued
-system.cpu0.iq.rate                          0.482197                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                     460588                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.009205                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         170766492                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         60297186                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     48772869                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             486828                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            236130                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       232978                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              50238035                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 253433                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          485739                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              49739725                       # Type of FU issued
+system.cpu0.iq.rate                          0.482739                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                     477090                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.009592                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         170451707                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         59601257                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     48417922                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             610021                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            293075                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       290010                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              49893944                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 319543                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          495668                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1334836                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        17971                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        25456                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       519571                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1332465                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        15476                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        20341                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       527918                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads        18977                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       164713                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads        14091                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       218656                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1267055                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                8486951                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               577503                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           56521315                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           733695                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              9033738                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             5759436                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts           1510903                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                459190                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents                 7711                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         25456                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        319028                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       300441                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              619469                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             49457194                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              8612039                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           576990                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1215315                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                6999311                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               544202                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           56199276                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           754553                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              9180149                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             6097470                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts           1645846                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                470730                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                 6896                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         20341                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        291584                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       326384                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              617968                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             49204821                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              8748371                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           534903                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                      3161127                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    14049434                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 7908844                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5437395                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.476636                       # Inst execution rate
-system.cpu0.iew.wb_sent                      49114578                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     49005847                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 24510505                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 32850763                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                      3129904                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    14495988                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 7765506                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5747617                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.477548                       # Inst execution rate
+system.cpu0.iew.wb_sent                      48811342                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     48707932                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 23956930                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 32092147                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.472286                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.746117                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.472725                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.746504                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitCommittedInsts      48687390                       # The number of committed instructions
-system.cpu0.commit.commitSquashedInsts        7735637                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         545080                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           563607                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     69394377                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.701604                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.587762                       # Number of insts commited each cycle
+system.cpu0.commit.commitCommittedInsts      48759720                       # The number of committed instructions
+system.cpu0.commit.commitSquashedInsts        7342909                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         596992                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           565842                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     69819405                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.698369                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.595257                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     50596179     72.91%     72.91% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      7970613     11.49%     84.40% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      4358860      6.28%     90.68% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2336816      3.37%     94.05% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1278043      1.84%     95.89% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       512868      0.74%     96.63% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       404165      0.58%     97.21% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       607557      0.88%     98.08% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1329276      1.92%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     51124042     73.22%     73.22% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      8032267     11.50%     84.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      4140271      5.93%     90.66% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2329968      3.34%     93.99% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1273302      1.82%     95.82% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       518646      0.74%     96.56% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       361032      0.52%     97.08% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       714639      1.02%     98.10% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1325238      1.90%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     69394377                       # Number of insts commited each cycle
-system.cpu0.commit.count                     48687390                       # Number of instructions committed
+system.cpu0.commit.committed_per_cycle::total     69819405                       # Number of insts commited each cycle
+system.cpu0.commit.count                     48759720                       # Number of instructions committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      12938767                       # Number of memory references committed
-system.cpu0.commit.loads                      7698902                       # Number of loads committed
-system.cpu0.commit.membars                     184242                       # Number of memory barriers committed
-system.cpu0.commit.branches                   7372386                       # Number of branches committed
-system.cpu0.commit.fp_insts                    230446                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 45102183                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              618802                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events              1329276                       # number cycles where commit BW limit reached
+system.cpu0.commit.refs                      13417236                       # Number of memory references committed
+system.cpu0.commit.loads                      7847684                       # Number of loads committed
+system.cpu0.commit.membars                     202015                       # Number of memory barriers committed
+system.cpu0.commit.branches                   7296729                       # Number of branches committed
+system.cpu0.commit.fp_insts                    287598                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 45136958                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              626830                       # Number of function calls committed.
+system.cpu0.commit.bw_lim_events              1325238                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   124302463                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  114114055                       # The number of ROB writes
-system.cpu0.timesIdled                        1107408                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       33101543                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts                   45891664                       # Number of Instructions Simulated
-system.cpu0.committedInsts_total             45891664                       # Number of Instructions Simulated
-system.cpu0.cpi                              2.261042                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.261042                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.442274                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.442274                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                65164143                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               35661718                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   113503                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  115176                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1562482                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                761048                       # number of misc regfile writes
+system.cpu0.rob.rob_reads                   124403287                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  113421475                       # The number of ROB writes
+system.cpu0.timesIdled                        1076474                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       32001726                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts                   45967748                       # Number of Instructions Simulated
+system.cpu0.committedInsts_total             45967748                       # Number of Instructions Simulated
+system.cpu0.cpi                              2.241494                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.241494                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.446131                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.446131                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                64511715                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               35217125                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   141815                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  144143                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads                1768684                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                843519                       # number of misc regfile writes
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -637,233 +637,233 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.cpu0.icache.replacements                795450                       # number of replacements
-system.cpu0.icache.tagsinuse               509.996584                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                 7012391                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                795959                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                  8.809990                       # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle           23368345000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0           509.996584                       # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0            0.996087                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::0            7012391                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        7012391                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::0             7012391                       # number of demand (read+write) hits
+system.cpu0.icache.replacements                880531                       # number of replacements
+system.cpu0.icache.tagsinuse               509.999835                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                 6871052                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                881041                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                  7.798788                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle           23352841000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::0           509.999835                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.996093                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::0            6871052                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        6871052                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::0             6871052                       # number of demand (read+write) hits
 system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         7012391                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::0            7012391                       # number of overall hits
+system.cpu0.icache.demand_hits::total         6871052                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::0            6871052                       # number of overall hits
 system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.icache.overall_hits::total        7012391                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::0           839924                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       839924                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::0            839924                       # number of demand (read+write) misses
+system.cpu0.icache.overall_hits::total        6871052                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::0           926359                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       926359                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::0            926359                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        839924                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::0           839924                       # number of overall misses
+system.cpu0.icache.demand_misses::total        926359                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::0           926359                       # number of overall misses
 system.cpu0.icache.overall_misses::1                0                       # number of overall misses
-system.cpu0.icache.overall_misses::total       839924                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency   12708309496                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency    12708309496                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency   12708309496                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::0        7852315                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      7852315                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::0         7852315                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_misses::total       926359                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency   13849490998                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency    13849490998                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency   13849490998                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::0        7797411                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      7797411                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::0         7797411                       # number of demand (read+write) accesses
 system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      7852315                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::0        7852315                       # number of overall (read+write) accesses
+system.cpu0.icache.demand_accesses::total      7797411                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::0        7797411                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      7852315                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::0      0.106965                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::0       0.106965                       # miss rate for demand accesses
+system.cpu0.icache.overall_accesses::total      7797411                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::0      0.118803                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::0       0.118803                       # miss rate for demand accesses
 system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::0      0.106965                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::0      0.118803                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::0 15130.308809                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::0 14950.457650                       # average ReadReq miss latency
 system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::0 15130.308809                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::0 14950.457650                       # average overall miss latency
 system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::0 15130.308809                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::0 14950.457650                       # average overall miss latency
 system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      1208998                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_mshrs      1091498                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              102                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              105                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 11852.921569                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 10395.219048                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks                     234                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits            43832                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits             43832                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits            43832                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses         796092                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses          796092                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses         796092                       # number of overall MSHR misses
+system.cpu0.icache.writebacks                     208                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits            45158                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits             45158                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits            45158                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses         881201                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses          881201                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses         881201                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency   9657065498                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency   9657065498                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency   9657065498                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency  10516036498                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency  10516036498                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency  10516036498                       # number of overall MSHR miss cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.101383                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.113012                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::0     0.101383                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::0     0.113012                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::0     0.101383                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::0     0.113012                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12130.589804                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 12130.589804                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 12130.589804                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11933.754612                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 11933.754612                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 11933.754612                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements               1219575                       # number of replacements
-system.cpu0.dcache.tagsinuse               498.032464                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                10118125                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs               1220087                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                  8.292954                       # Average number of references to valid blocks.
+system.cpu0.dcache.replacements               1121199                       # number of replacements
+system.cpu0.dcache.tagsinuse               488.854716                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                10572300                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs               1121711                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                  9.425155                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0           499.032464                       # Average occupied blocks per context
+system.cpu0.dcache.occ_blocks::0           489.854716                       # Average occupied blocks per context
 system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0            0.974673                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::0            0.956747                       # Average percentage of cache occupancy
 system.cpu0.dcache.occ_percent::1           -0.001953                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::0            6334107                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6334107                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::0           3441361                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3441361                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::0       153669                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       153669                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::0        174688                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       174688                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::0             9775468                       # number of demand (read+write) hits
+system.cpu0.dcache.ReadReq_hits::0            6494021                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6494021                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::0           3693282                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3693282                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::0       174657                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       174657                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::0        196468                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       196468                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::0            10187303                       # number of demand (read+write) hits
 system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         9775468                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::0            9775468                       # number of overall hits
+system.cpu0.dcache.demand_hits::total        10187303                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::0           10187303                       # number of overall hits
 system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        9775468                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::0          1480500                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1480500                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::0         1604462                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1604462                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::0        19020                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        19020                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::0         4294                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         4294                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::0           3084962                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_hits::total       10187303                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::0          1375687                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1375687                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::0         1662707                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1662707                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::0        20152                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        20152                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::0         3348                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         3348                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::0           3038394                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3084962                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::0          3084962                       # number of overall misses
+system.cpu0.dcache.demand_misses::total       3038394                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::0          3038394                       # number of overall misses
 system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3084962                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency   34097804500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency  52119525554                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency    280406500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency     58991000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency    86217330054                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency   86217330054                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::0        7814607                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7814607                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::0       5045823                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5045823                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::0       172689                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       172689                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::0       178982                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       178982                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::0        12860430                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_misses::total      3038394                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency   31827617500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency  51165322075                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency    294994000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency     41962000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency    82992939575                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency   82992939575                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::0        7869708                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      7869708                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::0       5355989                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5355989                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::0       194809                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       194809                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::0       199816                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       199816                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::0        13225697                       # number of demand (read+write) accesses
 system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12860430                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::0       12860430                       # number of overall (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     13225697                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::0       13225697                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12860430                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::0      0.189453                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::0     0.317978                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.110140                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::0     0.023991                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::0       0.239880                       # miss rate for demand accesses
+system.cpu0.dcache.overall_accesses::total     13225697                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::0      0.174808                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::0     0.310439                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.103445                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::0     0.016755                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::0       0.229734                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::0      0.239880                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::0      0.229734                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 23031.276258                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::0 23135.798695                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 32484.113400                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::0 30772.302080                       # average WriteReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14742.718191                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14638.447797                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13738.006521                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 12533.452808                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::0 27947.614931                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::0 27314.739160                       # average overall miss latency
 system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::0 27947.614931                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::0 27314.739160                       # average overall miss latency
 system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs    874274400                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       238500                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            96465                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_mshrs    855518470                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       221500                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            97807                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets             10                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs  9063.125486                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets        23850                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8747.006554                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets        22150                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks                  701727                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits           509168                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits         1351881                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits         4474                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits           1861049                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits          1861049                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses         971332                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses        252581                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses        14546                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses         4294                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses         1223913                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses        1223913                       # number of overall MSHR misses
+system.cpu0.dcache.writebacks                  602926                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits           516336                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits         1401114                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits         4413                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits           1917450                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits          1917450                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses         859351                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses        261593                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses        15739                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses         3348                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses         1120944                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses        1120944                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency  23290479000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency   7870556900                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    149366500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency     46100000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency  31161035900                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency  31161035900                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    917406500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1329367998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency   2246774498                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.124297                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_latency  21884756500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency   7717990970                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    167906500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency     31911000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency  29602747470                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency  29602747470                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    634931500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1090823998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency   1725755498                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.109197                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.050057                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.048841                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.084232                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.080792                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.023991                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.016755                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::0     0.095169                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::0     0.084755                       # mshr miss rate for demand accesses
 system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::0     0.095169                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::0     0.084755                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23977.876771                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 31160.526326                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10268.561804                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10735.910573                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 25460.172333                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 25460.172333                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 25466.609686                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29503.813061                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10668.180952                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency  9531.362007                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 26408.765710                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 26408.765710                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
@@ -874,22 +874,22 @@ system.cpu1.dtb.fetch_hits                          0                       # IT
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2434396                       # DTB read hits
-system.cpu1.dtb.read_misses                     12632                       # DTB read misses
-system.cpu1.dtb.read_acv                           51                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  349555                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1633702                       # DTB write hits
-system.cpu1.dtb.write_misses                     3988                       # DTB write misses
-system.cpu1.dtb.write_acv                          91                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 134749                       # DTB write accesses
-system.cpu1.dtb.data_hits                     4068098                       # DTB hits
-system.cpu1.dtb.data_misses                     16620                       # DTB misses
-system.cpu1.dtb.data_acv                          142                       # DTB access violations
-system.cpu1.dtb.data_accesses                  484304                       # DTB accesses
-system.cpu1.itb.fetch_hits                     488641                       # ITB hits
-system.cpu1.itb.fetch_misses                     8868                       # ITB misses
-system.cpu1.itb.fetch_acv                         207                       # ITB acv
-system.cpu1.itb.fetch_accesses                 497509                       # ITB accesses
+system.cpu1.dtb.read_hits                     2335038                       # DTB read hits
+system.cpu1.dtb.read_misses                     11141                       # DTB read misses
+system.cpu1.dtb.read_acv                           15                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  329726                       # DTB read accesses
+system.cpu1.dtb.write_hits                    1301059                       # DTB write hits
+system.cpu1.dtb.write_misses                     3075                       # DTB write misses
+system.cpu1.dtb.write_acv                          63                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 125932                       # DTB write accesses
+system.cpu1.dtb.data_hits                     3636097                       # DTB hits
+system.cpu1.dtb.data_misses                     14216                       # DTB misses
+system.cpu1.dtb.data_acv                           78                       # DTB access violations
+system.cpu1.dtb.data_accesses                  455658                       # DTB accesses
+system.cpu1.itb.fetch_hits                     423788                       # ITB hits
+system.cpu1.itb.fetch_misses                     7837                       # ITB misses
+system.cpu1.itb.fetch_acv                         166                       # ITB acv
+system.cpu1.itb.fetch_accesses                 431625                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -902,500 +902,500 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                        20348668                       # number of cpu cycles simulated
+system.cpu1.numCycles                        20152954                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups                 3352403                       # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted           2780204                       # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect            112990                       # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups              3035961                       # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits                 1319312                       # Number of BTB hits
+system.cpu1.BPredUnit.lookups                 3242658                       # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted           2662310                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect            131441                       # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups              2892914                       # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits                 1375784                       # Number of BTB hits
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS                  232566                       # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect               9070                       # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles           8042198                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      15968682                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    3352403                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           1551878                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      2969461                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 549599                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles               7368633                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles               27992                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles        74441                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles        61172                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles           29                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  1904129                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                71381                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples          18894151                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.845165                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.201588                       # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS                  235158                       # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect               7774                       # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles           6188689                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      16200802                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    3242658                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           1610942                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      3090469                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 613653                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles               7714239                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles               27241                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles        65046                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       159598                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles           12                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  1940544                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                74817                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples          17655267                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.917619                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.257026                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                15924690     84.28%     84.28% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  239855      1.27%     85.55% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  362060      1.92%     87.47% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  226098      1.20%     88.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  430016      2.28%     90.94% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  142596      0.75%     91.70% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  181045      0.96%     92.65% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  295229      1.56%     94.22% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 1092562      5.78%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                14564798     82.50%     82.50% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  197815      1.12%     83.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  462974      2.62%     86.24% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  255072      1.44%     87.68% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  513820      2.91%     90.59% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  162072      0.92%     91.51% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  211046      1.20%     92.71% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  121453      0.69%     93.39% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 1166217      6.61%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            18894151                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.164748                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.784753                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 7867478                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles              7772170                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  2762632                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               150042                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                341828                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              143049                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                 8486                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              15583049                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts                23483                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                341828                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 8134306                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                 601370                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles       6389331                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  2635739                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles               791575                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              14485157                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                  185                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 55864                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents               183661                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands            9468885                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups             17315691                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        17110872                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           204819                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps              7931339                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 1537546                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            569619                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts         61560                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  2500740                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             2578124                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            1732920                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           321113                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          190156                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  12582391                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             647000                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 12202318                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            26509                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        1926210                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined      1020296                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        460997                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     18894151                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.645825                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.311169                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            17655267                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.160902                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.803892                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 6415483                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles              7821687                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  2861971                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               154408                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                401717                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              149324                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                 8351                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              15726471                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts                21041                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                401717                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 6681295                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                2118018                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles       4943945                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  2656010                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles               854280                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              14736815                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                  186                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                221815                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents               138242                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands            9911157                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             18088761                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        17988130                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           100631                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps              7897558                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 2013599                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            424269                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts         36275                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  2592161                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             2485755                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            1426985                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           360752                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          285996                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  12852454                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             484885                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 12271073                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            26221                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        2300844                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      1315458                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        356394                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     17655267                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.695038                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.354056                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           13531447     71.62%     71.62% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            2408615     12.75%     84.37% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            1089992      5.77%     90.13% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3             719494      3.81%     93.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             600531      3.18%     97.12% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5             311690      1.65%     98.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             155684      0.82%     99.59% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7              53025      0.28%     99.87% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              23673      0.13%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           12407145     70.27%     70.27% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            2235941     12.66%     82.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            1035355      5.86%     88.80% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3             796484      4.51%     93.31% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             626149      3.55%     96.86% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             333560      1.89%     98.75% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             156466      0.89%     99.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7              49558      0.28%     99.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              14609      0.08%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       18894151                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       17655267                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                   4502      1.97%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                121874     53.21%     55.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               102674     44.83%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  13105      7.34%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      7.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                 95150     53.29%     60.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                70292     39.37%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass             3982      0.03%      0.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu              7613703     62.40%     62.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               19536      0.16%     62.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd              13122      0.11%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv               1991      0.02%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             2552683     20.92%     83.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            1661486     13.62%     97.25% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess            335815      2.75%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass             3979      0.03%      0.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu              8216703     66.96%     66.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               19600      0.16%     67.15% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.15% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd              11030      0.09%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv               1988      0.02%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             2431476     19.81%     87.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            1328460     10.83%     97.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            257837      2.10%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              12202318                       # Type of FU issued
-system.cpu1.iq.rate                          0.599662                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                     229050                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.018771                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          43260661                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         15016823                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     11811979                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads             293685                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            142362                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       139746                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              12273711                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 153675                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          108256                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              12271073                       # Type of FU issued
+system.cpu1.iq.rate                          0.608897                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                     178547                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.014550                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          42255695                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         15570864                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     11866318                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads             146486                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes             71642                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses        70264                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              12369614                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                  76027                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          105474                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       372523                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         7917                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         4307                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       156502                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       463598                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         9284                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         4789                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       195743                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads          333                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        28285                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads         5212                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        50812                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                341828                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 445544                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                34164                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           13910925                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           201807                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              2578124                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             1732920                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            582063                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 21599                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                 6281                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          4307                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         78974                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       111447                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              190421                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             12072034                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              2457890                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           130284                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                401717                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                1622444                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                62821                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           14027082                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           177744                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              2485755                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             1426985                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            441055                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 11459                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                 3097                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          4789                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        106850                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect        88794                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              195644                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             12103351                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              2352431                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           167722                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       681534                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     4103399                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 1804932                       # Number of branches executed
-system.cpu1.iew.exec_stores                   1645509                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.593259                       # Inst execution rate
-system.cpu1.iew.wb_sent                      11986744                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     11951725                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  5550831                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                  7770927                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       689743                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     3661778                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 1907962                       # Number of branches executed
+system.cpu1.iew.exec_stores                   1309347                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.600575                       # Inst execution rate
+system.cpu1.iew.wb_sent                      11974198                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     11936582                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  5946561                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                  8293064                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.587347                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.714307                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.592299                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.717052                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitCommittedInsts      11805751                       # The number of committed instructions
-system.cpu1.commit.commitSquashedInsts        2024872                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         186003                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           175934                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     18552323                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.636349                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.571810                       # Number of insts commited each cycle
+system.cpu1.commit.commitCommittedInsts      11515527                       # The number of committed instructions
+system.cpu1.commit.commitSquashedInsts        2436187                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         128491                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           177413                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     17253550                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.667429                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.563448                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     14118650     76.10%     76.10% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      2051209     11.06%     87.16% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2       792595      4.27%     91.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       477671      2.57%     94.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       327821      1.77%     95.77% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       149583      0.81%     96.58% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       116875      0.63%     97.21% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       167462      0.90%     98.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       350457      1.89%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     12827961     74.35%     74.35% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      1952306     11.32%     85.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2       928648      5.38%     91.05% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       493505      2.86%     93.91% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       338427      1.96%     95.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       153865      0.89%     96.76% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       124614      0.72%     97.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       119099      0.69%     98.17% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       315125      1.83%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     18552323                       # Number of insts commited each cycle
-system.cpu1.commit.count                     11805751                       # Number of instructions committed
+system.cpu1.commit.committed_per_cycle::total     17253550                       # Number of insts commited each cycle
+system.cpu1.commit.count                     11515527                       # Number of instructions committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       3782019                       # Number of memory references committed
-system.cpu1.commit.loads                      2205601                       # Number of loads committed
-system.cpu1.commit.membars                      61380                       # Number of memory barriers committed
-system.cpu1.commit.branches                   1685692                       # Number of branches committed
-system.cpu1.commit.fp_insts                    138212                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 10911872                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              184868                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events               350457                       # number cycles where commit BW limit reached
+system.cpu1.commit.refs                       3253399                       # Number of memory references committed
+system.cpu1.commit.loads                      2022157                       # Number of loads committed
+system.cpu1.commit.membars                      41280                       # Number of memory barriers committed
+system.cpu1.commit.branches                   1729331                       # Number of branches committed
+system.cpu1.commit.fp_insts                     68665                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 10682634                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              174972                       # Number of function calls committed.
+system.cpu1.commit.bw_lim_events               315125                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                    31928567                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   28001823                       # The number of ROB writes
-system.cpu1.timesIdled                         205057                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        1454517                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.committedInsts                   11204705                       # Number of Instructions Simulated
-system.cpu1.committedInsts_total             11204705                       # Number of Instructions Simulated
-system.cpu1.cpi                              1.816082                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.816082                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.550636                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.550636                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                15543323                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                8446180                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    74822                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   74815                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 675670                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                285692                       # number of misc regfile writes
-system.cpu1.icache.replacements                294345                       # number of replacements
-system.cpu1.icache.tagsinuse               471.340417                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                 1598818                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                294856                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                  5.422369                       # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle          1874432600000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0           471.340417                       # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0            0.920587                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::0            1598818                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        1598818                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::0             1598818                       # number of demand (read+write) hits
+system.cpu1.rob.rob_reads                    30796624                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   28304513                       # The number of ROB writes
+system.cpu1.timesIdled                         230784                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        2497687                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.committedInsts                   10925662                       # Number of Instructions Simulated
+system.cpu1.committedInsts_total             10925662                       # Number of Instructions Simulated
+system.cpu1.cpi                              1.844552                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.844552                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.542137                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.542137                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                15857410                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                8648406                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    40377                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   39511                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                 441161                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                195544                       # number of misc regfile writes
+system.cpu1.icache.replacements                205961                       # number of replacements
+system.cpu1.icache.tagsinuse               502.866762                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                 1723284                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                206473                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                  8.346292                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle          1708291874000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::0           502.866762                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.982162                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::0            1723284                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        1723284                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::0             1723284                       # number of demand (read+write) hits
 system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         1598818                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::0            1598818                       # number of overall hits
+system.cpu1.icache.demand_hits::total         1723284                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::0            1723284                       # number of overall hits
 system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.icache.overall_hits::total        1598818                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::0           305311                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       305311                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::0            305311                       # number of demand (read+write) misses
+system.cpu1.icache.overall_hits::total        1723284                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::0           217260                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       217260                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::0            217260                       # number of demand (read+write) misses
 system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        305311                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::0           305311                       # number of overall misses
+system.cpu1.icache.demand_misses::total        217260                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::0           217260                       # number of overall misses
 system.cpu1.icache.overall_misses::1                0                       # number of overall misses
-system.cpu1.icache.overall_misses::total       305311                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency    4483412500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency     4483412500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency    4483412500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::0        1904129                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      1904129                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::0         1904129                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_misses::total       217260                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency    3300371999                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency     3300371999                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency    3300371999                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::0        1940544                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1940544                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::0         1940544                       # number of demand (read+write) accesses
 system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      1904129                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::0        1904129                       # number of overall (read+write) accesses
+system.cpu1.icache.demand_accesses::total      1940544                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::0        1940544                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      1904129                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::0      0.160342                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::0       0.160342                       # miss rate for demand accesses
+system.cpu1.icache.overall_accesses::total      1940544                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::0      0.111958                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::0       0.111958                       # miss rate for demand accesses
 system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::0      0.160342                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::0      0.111958                       # miss rate for overall accesses
 system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::0 14684.739495                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::0 15190.886491                       # average ReadReq miss latency
 system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::0 14684.739495                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::0 15190.886491                       # average overall miss latency
 system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::0 14684.739495                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::0 15190.886491                       # average overall miss latency
 system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs       116500                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_mshrs       349000                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs               18                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs               33                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs  6472.222222                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 10575.757576                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks                      49                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits            10391                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits             10391                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits            10391                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses         294920                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses          294920                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses         294920                       # number of overall MSHR misses
+system.cpu1.icache.writebacks                      52                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits            10723                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits             10723                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits            10723                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses         206537                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses          206537                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses         206537                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency   3431981500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency   3431981500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency   3431981500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency   2520725000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency   2520725000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency   2520725000                       # number of overall MSHR miss cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.154884                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.106433                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::0     0.154884                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::0     0.106433                       # mshr miss rate for demand accesses
 system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::0     0.154884                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::0     0.106433                       # mshr miss rate for overall accesses
 system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11636.991387                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11636.991387                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11636.991387                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12204.713925                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 12204.713925                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 12204.713925                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                154143                       # number of replacements
-system.cpu1.dcache.tagsinuse               476.574727                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 3264047                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                154464                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                 21.131442                       # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle          1874646667000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0           476.574727                       # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0            0.930810                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::0            1976745                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1976745                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::0           1193181                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1193181                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::0        47069                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        47069                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::0         45973                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        45973                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::0             3169926                       # number of demand (read+write) hits
+system.cpu1.dcache.replacements                248685                       # number of replacements
+system.cpu1.dcache.tagsinuse               476.656972                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 2836087                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                248990                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                 11.390365                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle           39851697000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::0           476.656972                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.930971                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::0            1838875                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1838875                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::0            950135                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total        950135                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::0        25812                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        25812                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::0         24969                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        24969                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::0             2789010                       # number of demand (read+write) hits
 system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         3169926                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::0            3169926                       # number of overall hits
+system.cpu1.dcache.demand_hits::total         2789010                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::0            2789010                       # number of overall hits
 system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        3169926                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::0           282407                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       282407                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::0          325995                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       325995                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::0         7824                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         7824                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::0         4577                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         4577                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::0            608402                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_hits::total        2789010                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::0           315850                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       315850                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::0          245510                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       245510                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::0         5339                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         5339                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::0         3179                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         3179                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::0            561360                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        608402                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::0           608402                       # number of overall misses
+system.cpu1.dcache.demand_misses::total        561360                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::0           561360                       # number of overall misses
 system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       608402                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency    4155262000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency   7647875941                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency     85879000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency     62313500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency    11803137941                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency   11803137941                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::0        2259152                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2259152                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::0       1519176                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1519176                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::0        54893                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        54893                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::0        50550                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        50550                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0         3778328                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_misses::total       561360                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency    4714821500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency   8024030885                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency     65075500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency     42948000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency    12738852385                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency   12738852385                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::0        2154725                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2154725                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::0       1195645                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1195645                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::0        31151                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        31151                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::0        28148                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        28148                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::0         3350370                       # number of demand (read+write) accesses
 system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      3778328                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::0        3778328                       # number of overall (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      3350370                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::0        3350370                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      3778328                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0      0.125006                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0     0.214587                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.142532                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0     0.090544                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0       0.161024                       # miss rate for demand accesses
+system.cpu1.dcache.overall_accesses::total      3350370                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::0      0.146585                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::0     0.205337                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.171391                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::0     0.112939                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::0       0.167552                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::0      0.161024                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::0      0.167552                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 14713.735849                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::0 14927.406997                       # average ReadReq miss latency
 system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 23460.101968                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::0 32683.112236                       # average WriteReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 10976.354806                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 12188.705750                       # average LoadLockedReq miss latency
 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13614.485471                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13509.908776                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::0 19400.228699                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::0 22692.839506                       # average overall miss latency
 system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0 19400.228699                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::0 22692.839506                       # average overall miss latency
 system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs     94033995                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs             7725                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12172.685437                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.dcache.blocked_cycles::no_mshrs    135872392                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets       106000                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs            10757                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              4                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12631.067398                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets        26500                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks                  103879                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits           174324                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits          267778                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits          757                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits            442102                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits           442102                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses         108083                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses         58217                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses         7067                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses         4577                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses          166300                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses         166300                       # number of overall MSHR misses
+system.cpu1.dcache.writebacks                  196815                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits            98942                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits          203211                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits         1094                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits            302153                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits           302153                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses         216908                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses         42299                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses         4245                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses         3179                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses          259207                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses         259207                       # number of overall MSHR misses
 system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency   1297456000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency   1215847490                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     55744000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency     48574500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency   2513303490                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency   2513303490                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     18621500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    393979500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency    412601000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.047842                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_latency   2649753500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency   1268849871                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     33277000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency     33400500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency   3918603371                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency   3918603371                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency    300850000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    586892500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency    887742500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.100666                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.038321                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.035378                       # mshr miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.128741                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.136272                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.090544                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.112939                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::0     0.044014                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::0     0.077367                       # mshr miss rate for demand accesses
 system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0     0.044014                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::0     0.077367                       # mshr miss rate for overall accesses
 system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12004.255988                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 20884.749987                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  7887.929815                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10612.737601                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 15113.069693                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 15113.069693                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12216.024766                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29997.160004                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  7839.104829                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10506.605851                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 15117.660291                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 15117.660291                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
@@ -1403,164 +1403,160 @@ system.cpu1.dcache.mshr_cap_events                  0                       # nu
 system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6679                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    170123                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   59613     40.27%     40.27% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    237      0.16%     40.44% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1922      1.30%     41.73% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    309      0.21%     41.94% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  85934     58.06%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              148015                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    58855     49.10%     49.10% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     237      0.20%     49.30% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1922      1.60%     50.90% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     309      0.26%     51.16% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   58546     48.84%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               119869                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1860434296000     98.05%     98.05% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               90872000      0.00%     98.05% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              391830000      0.02%     98.07% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30              123760000      0.01%     98.08% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            36487097000      1.92%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1897527855000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.987285                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    5037                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    186073                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   65315     40.13%     40.13% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    237      0.15%     40.27% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1923      1.18%     41.46% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                    222      0.14%     41.59% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  95069     58.41%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              162766                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    63957     49.17%     49.17% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     237      0.18%     49.35% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1923      1.48%     50.83% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                     222      0.17%     51.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   63735     49.00%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               130074                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1863353937000     98.10%     98.10% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               90928000      0.00%     98.11% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              390512500      0.02%     98.13% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30               85006500      0.00%     98.13% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            35490372000      1.87%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1899410756000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.979208                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.681290                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2                         7      3.35%      3.35% # number of syscalls executed
-system.cpu0.kern.syscall::3                        17      8.13%     11.48% # number of syscalls executed
-system.cpu0.kern.syscall::4                         3      1.44%     12.92% # number of syscalls executed
-system.cpu0.kern.syscall::6                        31     14.83%     27.75% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.48%     28.23% # number of syscalls executed
-system.cpu0.kern.syscall::17                        8      3.83%     32.06% # number of syscalls executed
-system.cpu0.kern.syscall::19                        9      4.31%     36.36% # number of syscalls executed
-system.cpu0.kern.syscall::20                        6      2.87%     39.23% # number of syscalls executed
-system.cpu0.kern.syscall::23                        1      0.48%     39.71% # number of syscalls executed
-system.cpu0.kern.syscall::24                        3      1.44%     41.15% # number of syscalls executed
-system.cpu0.kern.syscall::33                        6      2.87%     44.02% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.96%     44.98% # number of syscalls executed
-system.cpu0.kern.syscall::45                       33     15.79%     60.77% # number of syscalls executed
-system.cpu0.kern.syscall::47                        3      1.44%     62.20% # number of syscalls executed
-system.cpu0.kern.syscall::48                        9      4.31%     66.51% # number of syscalls executed
-system.cpu0.kern.syscall::54                       10      4.78%     71.29% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.48%     71.77% # number of syscalls executed
-system.cpu0.kern.syscall::59                        5      2.39%     74.16% # number of syscalls executed
-system.cpu0.kern.syscall::71                       23     11.00%     85.17% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.44%     86.60% # number of syscalls executed
-system.cpu0.kern.syscall::74                        6      2.87%     89.47% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.48%     89.95% # number of syscalls executed
-system.cpu0.kern.syscall::90                        3      1.44%     91.39% # number of syscalls executed
-system.cpu0.kern.syscall::92                        9      4.31%     95.69% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.96%     96.65% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.96%     97.61% # number of syscalls executed
-system.cpu0.kern.syscall::132                       1      0.48%     98.09% # number of syscalls executed
-system.cpu0.kern.syscall::144                       2      0.96%     99.04% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.96%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   209                       # number of syscalls executed
+system.cpu0.kern.ipl_used::31                0.670408                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         8      3.72%      3.72% # number of syscalls executed
+system.cpu0.kern.syscall::3                        18      8.37%     12.09% # number of syscalls executed
+system.cpu0.kern.syscall::4                         3      1.40%     13.49% # number of syscalls executed
+system.cpu0.kern.syscall::6                        32     14.88%     28.37% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.47%     28.84% # number of syscalls executed
+system.cpu0.kern.syscall::17                        8      3.72%     32.56% # number of syscalls executed
+system.cpu0.kern.syscall::19                       10      4.65%     37.21% # number of syscalls executed
+system.cpu0.kern.syscall::20                        6      2.79%     40.00% # number of syscalls executed
+system.cpu0.kern.syscall::23                        1      0.47%     40.47% # number of syscalls executed
+system.cpu0.kern.syscall::24                        3      1.40%     41.86% # number of syscalls executed
+system.cpu0.kern.syscall::33                        6      2.79%     44.65% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      0.93%     45.58% # number of syscalls executed
+system.cpu0.kern.syscall::45                       33     15.35%     60.93% # number of syscalls executed
+system.cpu0.kern.syscall::47                        3      1.40%     62.33% # number of syscalls executed
+system.cpu0.kern.syscall::48                       10      4.65%     66.98% # number of syscalls executed
+system.cpu0.kern.syscall::54                       10      4.65%     71.63% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.47%     72.09% # number of syscalls executed
+system.cpu0.kern.syscall::59                        6      2.79%     74.88% # number of syscalls executed
+system.cpu0.kern.syscall::71                       23     10.70%     85.58% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.40%     86.98% # number of syscalls executed
+system.cpu0.kern.syscall::74                        6      2.79%     89.77% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.47%     90.23% # number of syscalls executed
+system.cpu0.kern.syscall::90                        3      1.40%     91.63% # number of syscalls executed
+system.cpu0.kern.syscall::92                        9      4.19%     95.81% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      0.93%     96.74% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      0.93%     97.67% # number of syscalls executed
+system.cpu0.kern.syscall::132                       1      0.47%     98.14% # number of syscalls executed
+system.cpu0.kern.syscall::144                       2      0.93%     99.07% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      0.93%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   215                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  406      0.26%      0.26% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.26% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.26% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.26% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3167      2.03%      2.29% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      45      0.03%      2.32% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.33% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               141170     90.48%     92.80% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6359      4.08%     96.88% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.88% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     2      0.00%     96.88% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     8      0.01%     96.89% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.89% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4376      2.80%     99.69% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 348      0.22%     99.91% # number of callpals executed
-system.cpu0.kern.callpal::imb                     134      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                156029                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             6806                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1160                       # number of protection mode switches
+system.cpu0.kern.callpal::wripir                  307      0.18%      0.18% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.18% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.18% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.18% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3778      2.20%      2.39% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      50      0.03%      2.42% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.42% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               155399     90.68%     93.10% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6322      3.69%     96.79% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.79% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     2      0.00%     96.79% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     9      0.01%     96.80% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     96.80% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4984      2.91%     99.71% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 369      0.22%     99.92% # number of callpals executed
+system.cpu0.kern.callpal::imb                     135      0.08%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                171369                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             7417                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1246                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1159                      
-system.cpu0.kern.mode_good::user                 1160                      
+system.cpu0.kern.mode_good::kernel               1245                      
+system.cpu0.kern.mode_good::user                 1246                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.170291                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.167858                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1895695413000     99.90%     99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          1832434000      0.10%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::kernel      1897486158000     99.90%     99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1924590000      0.10%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3168                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    3779                       # number of times the context was actually changed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2565                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     71341                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   23380     38.18%     38.18% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1920      3.14%     41.31% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    406      0.66%     41.98% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  35533     58.02%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               61239                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    22761     47.98%     47.98% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1920      4.05%     52.02% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     406      0.86%     52.88% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   22355     47.12%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                47442                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1868516653000     98.47%     98.47% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              343880500      0.02%     98.49% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              155607500      0.01%     98.50% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            28447585000      1.50%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1897463726000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.973524                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    4032                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     54228                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   17280     37.82%     37.82% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1921      4.20%     42.02% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    307      0.67%     42.69% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  26187     57.31%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               45695                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    17261     47.36%     47.36% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1921      5.27%     52.64% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     307      0.84%     53.48% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   16954     46.52%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                36443                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1869444423500     98.44%     98.44% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              345691000      0.02%     98.46% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              121909500      0.01%     98.46% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            29169069500      1.54%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1899081093500                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.998900                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.629133                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::2                         1      0.85%      0.85% # number of syscalls executed
-system.cpu1.kern.syscall::3                        13     11.11%     11.97% # number of syscalls executed
-system.cpu1.kern.syscall::4                         1      0.85%     12.82% # number of syscalls executed
-system.cpu1.kern.syscall::6                        11      9.40%     22.22% # number of syscalls executed
-system.cpu1.kern.syscall::15                        1      0.85%     23.08% # number of syscalls executed
-system.cpu1.kern.syscall::17                        7      5.98%     29.06% # number of syscalls executed
-system.cpu1.kern.syscall::19                        1      0.85%     29.91% # number of syscalls executed
-system.cpu1.kern.syscall::23                        3      2.56%     32.48% # number of syscalls executed
-system.cpu1.kern.syscall::24                        3      2.56%     35.04% # number of syscalls executed
-system.cpu1.kern.syscall::33                        5      4.27%     39.32% # number of syscalls executed
-system.cpu1.kern.syscall::45                       21     17.95%     57.26% # number of syscalls executed
-system.cpu1.kern.syscall::47                        3      2.56%     59.83% # number of syscalls executed
-system.cpu1.kern.syscall::48                        1      0.85%     60.68% # number of syscalls executed
-system.cpu1.kern.syscall::59                        2      1.71%     62.39% # number of syscalls executed
-system.cpu1.kern.syscall::71                       31     26.50%     88.89% # number of syscalls executed
-system.cpu1.kern.syscall::74                       10      8.55%     97.44% # number of syscalls executed
-system.cpu1.kern.syscall::132                       3      2.56%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                   117                       # number of syscalls executed
+system.cpu1.kern.ipl_used::31                0.647420                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::3                        12     10.81%     10.81% # number of syscalls executed
+system.cpu1.kern.syscall::4                         1      0.90%     11.71% # number of syscalls executed
+system.cpu1.kern.syscall::6                        10      9.01%     20.72% # number of syscalls executed
+system.cpu1.kern.syscall::15                        1      0.90%     21.62% # number of syscalls executed
+system.cpu1.kern.syscall::17                        7      6.31%     27.93% # number of syscalls executed
+system.cpu1.kern.syscall::23                        3      2.70%     30.63% # number of syscalls executed
+system.cpu1.kern.syscall::24                        3      2.70%     33.33% # number of syscalls executed
+system.cpu1.kern.syscall::33                        5      4.50%     37.84% # number of syscalls executed
+system.cpu1.kern.syscall::45                       21     18.92%     56.76% # number of syscalls executed
+system.cpu1.kern.syscall::47                        3      2.70%     59.46% # number of syscalls executed
+system.cpu1.kern.syscall::59                        1      0.90%     60.36% # number of syscalls executed
+system.cpu1.kern.syscall::71                       31     27.93%     88.29% # number of syscalls executed
+system.cpu1.kern.syscall::74                       10      9.01%     97.30% # number of syscalls executed
+system.cpu1.kern.syscall::132                       3      2.70%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                   111                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  309      0.49%      0.49% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.49% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.49% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 1667      2.62%      3.12% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       9      0.01%      3.13% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      3.14% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                55390     87.20%     90.34% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2392      3.77%     94.10% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.10% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     5      0.01%     94.11% # number of callpals executed
-system.cpu1.kern.callpal::rdusp                     1      0.00%     94.11% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     94.12% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3522      5.54%     99.66% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 167      0.26%     99.92% # number of callpals executed
-system.cpu1.kern.callpal::imb                      47      0.07%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                  222      0.47%      0.47% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.47% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.48% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                  871      1.85%      2.32% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       3      0.01%      2.33% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.01%      2.34% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                40736     86.30%     88.64% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2431      5.15%     93.79% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.79% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     5      0.01%     93.80% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.01%     93.81% # number of callpals executed
+system.cpu1.kern.callpal::rti                    2730      5.78%     99.59% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 146      0.31%     99.90% # number of callpals executed
+system.cpu1.kern.callpal::imb                      45      0.10%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 63524                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             1934                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                578                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2650                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                909                      
-system.cpu1.kern.mode_good::user                  578                      
-system.cpu1.kern.mode_good::idle                  331                      
-system.cpu1.kern.mode_switch_good::kernel     0.470010                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                 47204                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             1142                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                492                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2462                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                761                      
+system.cpu1.kern.mode_good::user                  492                      
+system.cpu1.kern.mode_good::idle                  269                      
+system.cpu1.kern.mode_switch_good::kernel     0.666375                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.124906                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     1.594916                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        6826914500      0.36%      0.36% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           949063500      0.05%      0.41% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1889043105000     99.59%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    1668                       # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle      0.109261                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     1.775636                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel       35491661500      1.87%      1.87% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user           858235500      0.05%      1.91% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1862377378000     98.09%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                     872                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
index 496218c55883e16f79d9b27fcf2345841c390cf3..4bc0cb36c52bbf5ac801255c14da56c801e8fe71 100644 (file)
@@ -10,13 +10,13 @@ type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/arm/scratch/sysexplr/dist/binaries/console
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/arm/scratch/sysexplr/dist/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -496,7 +496,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -516,7 +516,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -645,7 +645,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
index df759602b886900c219a6fd21b4d7f59043ce235..a2519d6a48be95c1d2d91ce0227010e76a8e0a67 100755 (executable)
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simout
+Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  9 2011 03:11:31
-gem5 started Aug  9 2011 03:11:36
-gem5 executing on burrito
+gem5 compiled Aug 15 2011 20:24:21
+gem5 started Aug 15 2011 20:25:48
+gem5 executing on nadc-0270
 command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1858690543500 because m5_exit instruction encountered
+Exiting @ tick 1858708914500 because m5_exit instruction encountered
index 615b7b1c53b36ac55496fbd334ba4b5e435f4781..eab7f53869cd890c7d8c5125f8f1ebed78bf06bd 100644 (file)
@@ -1,94 +1,94 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.858691                       # Number of seconds simulated
-sim_ticks                                1858690543500                       # Number of ticks simulated
+sim_seconds                                  1.858709                       # Number of seconds simulated
+sim_ticks                                1858708914500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 131020                       # Simulator instruction rate (inst/s)
-host_tick_rate                             4587017100                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 315160                       # Number of bytes of host memory used
-host_seconds                                   405.21                       # Real time elapsed on the host
-sim_insts                                    53090369                       # Number of instructions simulated
-system.l2c.replacements                        391395                       # number of replacements
-system.l2c.tagsinuse                     34960.020004                       # Cycle average of tags in use
-system.l2c.total_refs                         2406151                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        424265                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          5.671340                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                    5621019000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                 12378.384666                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 22581.635338                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.188879                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.344568                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    1801346                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1801346                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                   835143                       # number of Writeback hits
-system.l2c.Writeback_hits::total               835143                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                      15                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  15                       # number of UpgradeReq hits
+host_inst_rate                                 124964                       # Simulator instruction rate (inst/s)
+host_tick_rate                             4374927606                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 340632                       # Number of bytes of host memory used
+host_seconds                                   424.85                       # Real time elapsed on the host
+sim_insts                                    53091761                       # Number of instructions simulated
+system.l2c.replacements                        391302                       # number of replacements
+system.l2c.tagsinuse                     34944.632545                       # Cycle average of tags in use
+system.l2c.total_refs                         2405534                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        424233                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          5.670313                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                    5611809000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0                 12322.596332                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 22622.036213                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.188028                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.345185                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0                    1801216                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1801216                       # number of ReadReq hits
+system.l2c.Writeback_hits::0                   835065                       # number of Writeback hits
+system.l2c.Writeback_hits::total               835065                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                      13                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  13                       # number of UpgradeReq hits
 system.l2c.SCUpgradeReq_hits::0                     2                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                 2                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0                   183109                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               183109                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     1984455                       # number of demand (read+write) hits
+system.l2c.ReadExReq_hits::0                   183191                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               183191                       # number of ReadExReq hits
+system.l2c.demand_hits::0                     1984407                       # number of demand (read+write) hits
 system.l2c.demand_hits::1                           0                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1984455                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    1984455                       # number of overall hits
+system.l2c.demand_hits::total                 1984407                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                    1984407                       # number of overall hits
 system.l2c.overall_hits::1                          0                       # number of overall hits
-system.l2c.overall_hits::total                1984455                       # number of overall hits
-system.l2c.ReadReq_misses::0                   308108                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               308108                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                    34                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                34                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                 116921                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             116921                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    425029                       # number of demand (read+write) misses
+system.l2c.overall_hits::total                1984407                       # number of overall hits
+system.l2c.ReadReq_misses::0                   308126                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               308126                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                    31                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                31                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::0                 116919                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             116919                       # number of ReadExReq misses
+system.l2c.demand_misses::0                    425045                       # number of demand (read+write) misses
 system.l2c.demand_misses::1                         0                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                425029                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   425029                       # number of overall misses
+system.l2c.demand_misses::total                425045                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                   425045                       # number of overall misses
 system.l2c.overall_misses::1                        0                       # number of overall misses
-system.l2c.overall_misses::total               425029                       # number of overall misses
-system.l2c.ReadReq_miss_latency           16037313500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency             372000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          6133457500                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency            22170771000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency           22170771000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                2109454                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2109454                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0               835143                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           835143                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                  49                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              49                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.overall_misses::total               425045                       # number of overall misses
+system.l2c.ReadReq_miss_latency           16035962500                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency             425000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency          6137530000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency            22173492500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency           22173492500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::0                2109342                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2109342                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0               835065                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           835065                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0                  44                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              44                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::0                 2                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               300030                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           300030                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 2409484                       # number of demand (read+write) accesses
+system.l2c.ReadExReq_accesses::0               300110                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           300110                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0                 2409452                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::1                       0                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2409484                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                2409484                       # number of overall (read+write) accesses
+system.l2c.demand_accesses::total             2409452                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::0                2409452                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2409484                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.146061                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.693878                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.389698                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.176398                       # miss rate for demand accesses
+system.l2c.overall_accesses::total            2409452                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0              0.146077                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.704545                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0            0.389587                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.176407                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::1               no_value                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.176398                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::0              0.176407                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::1              no_value                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   52050.948044                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::0   52043.522780                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::1            inf                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 10941.176471                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0 13709.677419                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52458.134125                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 52493.863273                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    52162.960645                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::0    52167.399922                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::1             inf                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   52162.960645                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0   52167.399922                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::1            inf                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
@@ -99,43 +99,43 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          117784                       # number of writebacks
+system.l2c.writebacks                          117722                       # number of writebacks
 system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                 308108                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                  34                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               116921                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  425029                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 425029                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_misses                 308126                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                  31                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses               116919                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses                  425045                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                 425045                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency      12333770000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency       1420000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     4711661500                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency       17045431500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency      17045431500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency    810039500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency   1115188998                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency   1925228498                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.146061                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_latency      12333217500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency       1300000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency     4715307000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency       17048524500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency      17048524500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency    809593500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency   1114721998                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency   1924315498                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.146077                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::1              inf                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      0.693878                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0      0.704545                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       0.389698                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0       0.389587                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.176398                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::0          0.176407                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::1               inf                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.176398                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::0         0.176407                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::1              inf                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40030.671063                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 41764.705882                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40297.820751                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40104.161128                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40104.161128                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40026.539468                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 41935.483871                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40329.689785                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency  40109.928361                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40109.928361                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
@@ -143,13 +143,13 @@ system.l2c.mshr_cap_events                          0                       # nu
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41685                       # number of replacements
-system.iocache.tagsinuse                     1.266648                       # Cycle average of tags in use
+system.iocache.tagsinuse                     1.266801                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              1708339298000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1                 1.266648                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.079165                       # Average percentage of cache occupancy
+system.iocache.warmup_cycle              1708338851000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::1                 1.266801                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.079175                       # Average percentage of cache occupancy
 system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
@@ -166,10 +166,10 @@ system.iocache.demand_misses::total             41725                       # nu
 system.iocache.overall_misses::0                    0                       # number of overall misses
 system.iocache.overall_misses::1                41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency          19939998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency       5722104806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency         5742044804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency        5742044804                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency          19937998                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency       5722275806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency         5742213804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency        5742213804                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::1                173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
@@ -189,22 +189,22 @@ system.iocache.overall_miss_rate::0          no_value                       # mi
 system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115260.104046                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 115248.543353                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137709.491866                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137713.607191                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
 system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137616.412319                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137620.462648                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137616.412319                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137620.462648                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs      64599068                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs      64594068                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                10462                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                10468                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  6174.638501                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6170.621704                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -216,10 +216,10 @@ system.iocache.WriteReq_mshr_misses             41552                       # nu
 system.iocache.demand_mshr_misses               41725                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses              41725                       # number of overall MSHR misses
 system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.ReadReq_mshr_miss_latency     10943998                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency   3561252994                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency    3572196992                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency   3572196992                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency     10941998                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3561421998                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    3572363996                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   3572363996                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
@@ -233,10 +233,10 @@ system.iocache.demand_mshr_miss_rate::total          inf                       #
 system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85705.934588                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency 85612.869790                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency 85612.869790                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85710.001877                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85616.872283                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85616.872283                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
@@ -257,22 +257,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     10172213                       # DTB read hits
-system.cpu.dtb.read_misses                      43494                       # DTB read misses
-system.cpu.dtb.read_acv                           580                       # DTB read access violations
-system.cpu.dtb.read_accesses                   956567                       # DTB read accesses
-system.cpu.dtb.write_hits                     6637652                       # DTB write hits
-system.cpu.dtb.write_misses                      9272                       # DTB write misses
-system.cpu.dtb.write_acv                          322                       # DTB write access violations
-system.cpu.dtb.write_accesses                  335213                       # DTB write accesses
-system.cpu.dtb.data_hits                     16809865                       # DTB hits
-system.cpu.dtb.data_misses                      52766                       # DTB misses
-system.cpu.dtb.data_acv                           902                       # DTB access violations
-system.cpu.dtb.data_accesses                  1291780                       # DTB accesses
-system.cpu.itb.fetch_hits                     1342789                       # ITB hits
-system.cpu.itb.fetch_misses                     39758                       # ITB misses
-system.cpu.itb.fetch_acv                         1040                       # ITB acv
-system.cpu.itb.fetch_accesses                 1382547                       # ITB accesses
+system.cpu.dtb.read_hits                     10154080                       # DTB read hits
+system.cpu.dtb.read_misses                      43144                       # DTB read misses
+system.cpu.dtb.read_acv                           557                       # DTB read access violations
+system.cpu.dtb.read_accesses                   952445                       # DTB read accesses
+system.cpu.dtb.write_hits                     6614848                       # DTB write hits
+system.cpu.dtb.write_misses                      9467                       # DTB write misses
+system.cpu.dtb.write_acv                          320                       # DTB write access violations
+system.cpu.dtb.write_accesses                  334339                       # DTB write accesses
+system.cpu.dtb.data_hits                     16768928                       # DTB hits
+system.cpu.dtb.data_misses                      52611                       # DTB misses
+system.cpu.dtb.data_acv                           877                       # DTB access violations
+system.cpu.dtb.data_accesses                  1286784                       # DTB accesses
+system.cpu.itb.fetch_hits                     1336327                       # ITB hits
+system.cpu.itb.fetch_misses                     39787                       # ITB misses
+system.cpu.itb.fetch_acv                         1065                       # ITB acv
+system.cpu.itb.fetch_accesses                 1376114                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -285,275 +285,275 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        117561370                       # number of cpu cycles simulated
+system.cpu.numCycles                        117237485                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 14512096                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           12124763                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             534985                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              13082442                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  6780681                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 14455551                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           12084424                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             532367                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              13050115                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  6745735                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                   985415                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               44835                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           29301348                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       74523128                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    14512096                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            7766096                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      14456496                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2475230                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               37352483                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                32620                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        262284                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       336025                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          123                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9183314                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                332127                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           83379045                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.893787                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.210786                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                   978348                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               45278                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           29236023                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       74164805                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    14455551                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            7724083                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      14385478                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2439202                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               37224537                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                33011                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        262840                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       335923                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          148                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9135306                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                330174                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           83080083                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.892691                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.209867                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 68922549     82.66%     82.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1028480      1.23%     83.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2035774      2.44%     86.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   998762      1.20%     87.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2982144      3.58%     91.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   700003      0.84%     91.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   807750      0.97%     92.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1076941      1.29%     94.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  4826642      5.79%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 68694605     82.68%     82.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1023953      1.23%     83.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2033478      2.45%     86.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   975932      1.17%     87.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2976777      3.58%     91.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   700548      0.84%     91.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   794915      0.96%     92.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1072238      1.29%     94.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  4807637      5.79%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             83379045                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.123443                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.633908                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 30625799                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              36960246                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  13171913                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1025264                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1595822                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved               618911                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 42154                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               72819380                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                127184                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1595822                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 31874108                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                12944384                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       19864625                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  12330385                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               4769719                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               68803114                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  4210                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 997602                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               1469982                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands            46108022                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              83655268                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         83175686                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            479582                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              38259780                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  7848234                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1700711                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         251216                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12962201                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             10843547                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             7060604                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2097425                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2214211                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   60377206                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2118999                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  58263583                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             82757                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         9009938                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      4851831                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1451256                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      83379045                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.698780                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.313076                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total             83080083                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.123301                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.632603                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 30551542                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              36838313                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  13095678                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1034253                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1560296                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved               613869                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 42144                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               72480994                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                127271                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1560296                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 31800995                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                12812731                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       19871114                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  12262779                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               4772166                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               68475649                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  4094                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 996372                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               1464404                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands            45853535                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              83251938                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         82772461                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            479477                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              38260770                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  7592757                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1700825                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         251533                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12956852                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             10812074                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             7051744                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2165147                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2346616                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   60096918                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2117388                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  58031681                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             82818                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         8738509                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      4816872                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1449642                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      83080083                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.698503                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.311149                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            56881095     68.22%     68.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            11965083     14.35%     82.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             5985120      7.18%     89.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             3573465      4.29%     94.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             2606291      3.13%     97.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1333403      1.60%     98.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6              786052      0.94%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              188914      0.23%     99.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8               59622      0.07%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            56639169     68.17%     68.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            11994103     14.44%     82.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5929931      7.14%     89.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             3560683      4.29%     94.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2591551      3.12%     97.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1336446      1.61%     98.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6              797054      0.96%     99.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              184259      0.22%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               46887      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        83379045                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        83080083                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   66647     11.94%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 311938     55.88%     67.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                179673     32.18%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   68783     12.83%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     12.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 305726     57.04%     69.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                161454     30.12%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              7281      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              39837502     68.37%     68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                63640      0.11%     68.50% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd               25605      0.04%     68.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.55% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             10651640     18.28%     86.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             6721971     11.54%     98.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess             952308      1.63%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              39661101     68.34%     68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                62145      0.11%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd               25610      0.04%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.51% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             10623971     18.31%     86.82% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6695582     11.54%     98.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess             952355      1.64%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               58263583                       # Type of FU issued
-system.cpu.iq.rate                           0.495601                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                      558258                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.009582                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          199861715                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          71197744                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     56697880                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              685510                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             334104                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       327554                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               58457489                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  357071                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           546714                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               58031681                       # Type of FU issued
+system.cpu.iq.rate                           0.494993                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                      535963                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.009236                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          199072460                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          70641414                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     56449878                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              689765                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             333951                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       328040                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               58199260                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  361103                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           552721                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1730283                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        13242                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        28963                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       668160                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1698615                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        15451                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        23451                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       659180                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        18982                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        168763                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        18682                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        200829                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1595822                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 9001389                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                625458                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            66156357                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            866739                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              10843547                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              7060604                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1871783                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 491434                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 13753                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          28963                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         389249                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       383472                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               772721                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              57555020                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              10245935                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            708562                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1560296                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 8872665                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                625505                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            65852816                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            871025                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              10812074                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              7051744                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1870069                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 491565                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  7470                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          23451                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         385257                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       383183                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               768440                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              57350351                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              10227555                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            681329                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3660152                       # number of nop insts executed
-system.cpu.iew.exec_refs                     16908045                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  9133755                       # Number of branches executed
-system.cpu.iew.exec_stores                    6662110                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.489574                       # Inst execution rate
-system.cpu.iew.wb_sent                       57159115                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      57025434                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  28218942                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  38051860                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       3638510                       # number of nop insts executed
+system.cpu.iew.exec_refs                     16867130                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                  9102477                       # Number of branches executed
+system.cpu.iew.exec_stores                    6639575                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.489181                       # Inst execution rate
+system.cpu.iew.wb_sent                       56909286                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      56777918                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  28083144                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  37838196                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.485069                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.741592                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.484298                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.742190                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       56284997                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts         9746037                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          667743                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            704725                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     81783223                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.688222                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.561458                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts       56286421                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts         9443080                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          667746                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            702134                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     81519787                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.690463                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.566765                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     59869495     73.21%     73.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      9271272     11.34%     84.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      5260342      6.43%     90.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2449132      2.99%     93.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1675900      2.05%     96.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       634046      0.78%     96.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       464374      0.57%     97.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       783725      0.96%     98.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1374937      1.68%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     59658965     73.18%     73.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      9249179     11.35%     84.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      5213125      6.39%     90.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2451549      3.01%     93.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1701758      2.09%     96.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       617367      0.76%     96.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       434350      0.53%     97.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       791574      0.97%     98.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1401920      1.72%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     81783223                       # Number of insts commited each cycle
-system.cpu.commit.count                      56284997                       # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total     81519787                       # Number of insts commited each cycle
+system.cpu.commit.count                      56286421                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       15505708                       # Number of memory references committed
-system.cpu.commit.loads                       9113264                       # Number of loads committed
-system.cpu.commit.membars                      227891                       # Number of memory barriers committed
-system.cpu.commit.branches                    8461884                       # Number of branches committed
-system.cpu.commit.fp_insts                     324250                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  52123418                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               744517                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               1374937                       # number cycles where commit BW limit reached
+system.cpu.commit.refs                       15506023                       # Number of memory references committed
+system.cpu.commit.loads                       9113459                       # Number of loads committed
+system.cpu.commit.membars                      227879                       # Number of memory barriers committed
+system.cpu.commit.branches                    8462155                       # Number of branches committed
+system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                  52124782                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               744514                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               1401920                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    146188247                       # The number of ROB reads
-system.cpu.rob.rob_writes                   133660667                       # The number of ROB writes
-system.cpu.timesIdled                         1252693                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        34182325                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                    53090369                       # Number of Instructions Simulated
-system.cpu.committedInsts_total              53090369                       # Number of Instructions Simulated
-system.cpu.cpi                               2.214363                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.214363                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.451597                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.451597                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 75435318                       # number of integer regfile reads
-system.cpu.int_regfile_writes                41215589                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    165687                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   167399                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 1995946                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 949866                       # number of misc regfile writes
+system.cpu.rob.rob_reads                    145596309                       # The number of ROB reads
+system.cpu.rob.rob_writes                   133022104                       # The number of ROB writes
+system.cpu.timesIdled                         1258228                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        34157402                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                    53091761                       # Number of Instructions Simulated
+system.cpu.committedInsts_total              53091761                       # Number of Instructions Simulated
+system.cpu.cpi                               2.208205                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.208205                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.452857                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.452857                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                 75150720                       # number of integer regfile reads
+system.cpu.int_regfile_writes                41017067                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    166113                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   167453                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                 1996494                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 949911                       # number of misc regfile writes
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -585,231 +585,231 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.cpu.icache.replacements                1005223                       # number of replacements
-system.cpu.icache.tagsinuse                509.948854                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  8118172                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                1005732                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   8.071904                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            23367175000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            509.948854                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.995994                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0             8118173                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8118173                       # number of ReadReq hits
-system.cpu.icache.demand_hits::0              8118173                       # number of demand (read+write) hits
+system.cpu.icache.replacements                1005090                       # number of replacements
+system.cpu.icache.tagsinuse                509.951538                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  8070754                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                1005599                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   8.025817                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            23351335000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            509.951538                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.995999                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::0             8070755                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8070755                       # number of ReadReq hits
+system.cpu.icache.demand_hits::0              8070755                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8118173                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0             8118173                       # number of overall hits
+system.cpu.icache.demand_hits::total          8070755                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::0             8070755                       # number of overall hits
 system.cpu.icache.overall_hits::1                   0                       # number of overall hits
-system.cpu.icache.overall_hits::total         8118173                       # number of overall hits
-system.cpu.icache.ReadReq_misses::0           1065140                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1065140                       # number of ReadReq misses
-system.cpu.icache.demand_misses::0            1065140                       # number of demand (read+write) misses
+system.cpu.icache.overall_hits::total         8070755                       # number of overall hits
+system.cpu.icache.ReadReq_misses::0           1064551                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1064551                       # number of ReadReq misses
+system.cpu.icache.demand_misses::0            1064551                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1065140                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0           1065140                       # number of overall misses
+system.cpu.icache.demand_misses::total        1064551                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::0           1064551                       # number of overall misses
 system.cpu.icache.overall_misses::1                 0                       # number of overall misses
-system.cpu.icache.overall_misses::total       1065140                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency    15927800996                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency     15927800996                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency    15927800996                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0         9183313                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9183313                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0          9183313                       # number of demand (read+write) accesses
+system.cpu.icache.overall_misses::total       1064551                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency    15926988994                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency     15926988994                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency    15926988994                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::0         9135306                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9135306                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::0          9135306                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9183313                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0         9183313                       # number of overall (read+write) accesses
+system.cpu.icache.demand_accesses::total      9135306                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::0         9135306                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9183313                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0       0.115986                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0        0.115986                       # miss rate for demand accesses
+system.cpu.icache.overall_accesses::total      9135306                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::0       0.116532                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::0        0.116532                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0       0.115986                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::0       0.116532                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 14953.715940                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::0 14961.226840                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 14953.715940                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::0 14961.226840                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 14953.715940                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::0 14961.226840                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      1340497                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs      1261996                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               122                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               120                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 10987.680328                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 10516.633333                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                      231                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits             59195                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits              59195                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits             59195                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses         1005945                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses          1005945                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses         1005945                       # number of overall MSHR misses
+system.cpu.icache.writebacks                      232                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits             58739                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits              58739                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits             58739                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses         1005812                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses          1005812                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses         1005812                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency  12050423497                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency  12050423497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency  12050423497                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency  12051659996                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency  12051659996                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency  12051659996                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.109541                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::0     0.110102                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0     0.109541                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::0     0.110102                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0     0.109541                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::0     0.110102                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11979.207111                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11979.207111                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11979.207111                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11982.020493                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11982.020493                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11982.020493                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1403249                       # number of replacements
-system.cpu.dcache.tagsinuse                511.995942                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 12177929                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1403761                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                   8.675215                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               19464000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            511.995942                       # Average occupied blocks per context
+system.cpu.dcache.replacements                1403296                       # number of replacements
+system.cpu.dcache.tagsinuse                511.995990                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 12128638                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1403808                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                   8.639813                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               19282000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0            511.995990                       # Average occupied blocks per context
 system.cpu.dcache.occ_percent::0             0.999992                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0             7541924                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7541924                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0            4223581                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4223581                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::0        192169                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       192169                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::0         220074                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       220074                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::0             11765505                       # number of demand (read+write) hits
+system.cpu.dcache.ReadReq_hits::0             7493448                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7493448                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::0            4222901                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4222901                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::0        192043                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       192043                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::0         220080                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       220080                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::0             11716349                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         11765505                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0            11765505                       # number of overall hits
+system.cpu.dcache.demand_hits::total         11716349                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::0            11716349                       # number of overall hits
 system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
-system.cpu.dcache.overall_hits::total        11765505                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::0           1785380                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1785380                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0          1933647                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1933647                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::0        23245                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        23245                       # number of LoadLockedReq misses
+system.cpu.dcache.overall_hits::total        11716349                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::0           1778869                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1778869                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::0          1934444                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1934444                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::0        23262                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        23262                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::0            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::0            3719027                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0            3713313                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3719027                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0           3719027                       # number of overall misses
+system.cpu.dcache.demand_misses::total        3713313                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::0           3713313                       # number of overall misses
 system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3719027                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    38531981000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   57348648047                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency    361113000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.overall_misses::total       3713313                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    38377192500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   57331444318                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency    363604000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency        28500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency     95880629047                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    95880629047                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0         9327304                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9327304                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0        6157228                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6157228                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::0       215414                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       215414                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::0       220076                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       220076                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0         15484532                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_miss_latency     95708636818                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    95708636818                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::0         9272317                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9272317                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::0        6157345                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6157345                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::0       215305                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       215305                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::0       220082                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       220082                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::0         15429662                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15484532                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0        15484532                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15429662                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::0        15429662                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15484532                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0       0.191414                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0      0.314045                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0     0.107908                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.overall_accesses::total     15429662                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0       0.191847                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0      0.314169                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::0     0.108042                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::0     0.000009                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::0        0.240177                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::0        0.240661                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0       0.240177                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::0       0.240661                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 21581.949501                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::0 21573.928434                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 29658.282017                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::0 29637.169294                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15535.082814                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15630.814203                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::0        14250                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 25781.105931                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::0 25774.459847                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 25781.105931                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0 25774.459847                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs    904772827                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       266500                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             99710                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              12                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  9074.042995                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 22208.333333                       # average number of cycles each access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs    916364836                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       209000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            100291                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               9                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  9137.059517                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 23222.222222                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   834912                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            697810                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1634824                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits         5710                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            2332634                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           2332634                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1087570                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         298823                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses        17535                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks                   834833                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            691203                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1635634                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits         5726                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            2326837                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           2326837                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1087666                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         298810                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses        17536                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1386393                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1386393                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses          1386476                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1386476                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  24793495000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   8488664327                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency    207086500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  24813377000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   8487477836                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency    207860000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency        22000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  33282159327                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  33282159327                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency    904509000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1234461998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency   2138970998                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.116601                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency  33300854836                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  33300854836                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency    904007000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1234009498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency   2138016498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.117303                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.048532                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.048529                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.081401                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.081447                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::0     0.000009                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0     0.089534                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::0     0.089858                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0     0.089534                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::0     0.089858                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22797.148689                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28406.997878                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11809.894497                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22813.416067                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28404.263030                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11853.330292                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency        11000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 24006.294988                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 24006.294988                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 24018.342067                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 24018.342067                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
@@ -818,26 +818,26 @@ system.cpu.dcache.soft_prefetch_mshr_full            0                       # n
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     6434                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211584                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74877     40.96%     40.96% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     244      0.13%     41.09% # number of times we switched to this ipl
+system.cpu.kern.inst.hwrei                     211594                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74884     40.96%     40.96% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     241      0.13%     41.09% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1882      1.03%     42.12% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105811     57.88%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182814                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73510     49.29%     49.29% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      244      0.16%     49.45% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::31                  105815     57.88%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182822                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73517     49.29%     49.29% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21                      241      0.16%     49.45% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::22                     1882      1.26%     50.71% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73514     49.29%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149150                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1819958547500     97.92%     97.92% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                94089500      0.01%     97.92% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               384592500      0.02%     97.94% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             38252453500      2.06%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1858689683000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981743                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::31                    73519     49.29%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                149159                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1820013648500     97.92%     97.92% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                93762000      0.01%     97.92% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               384408000      0.02%     97.94% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             38216235500      2.06%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1858708054000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981745                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694767                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694788                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -873,32 +873,32 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4174      2.17%      2.17% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4176      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175475     91.19%     93.39% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175485     91.19%     93.39% # number of callpals executed
 system.cpu.kern.callpal::rdps                    6787      3.53%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.93% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.93% # number of callpals executed
-system.cpu.kern.callpal::rti                     5216      2.71%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5215      2.71%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192432                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5955                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1737                       # number of protection mode switches
+system.cpu.kern.callpal::total                 192443                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5956                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
 system.cpu.kern.mode_switch::idle                2101                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1906                      
-system.cpu.kern.mode_good::user                  1737                      
-system.cpu.kern.mode_good::idle                   169                      
-system.cpu.kern.mode_switch_good::kernel     0.320067                       # fraction of useful protection mode switches
+system.cpu.kern.mode_good::kernel                1908                      
+system.cpu.kern.mode_good::user                  1738                      
+system.cpu.kern.mode_good::idle                   170                      
+system.cpu.kern.mode_switch_good::kernel     0.320349                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080438                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      1.400505                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        29488985500      1.59%      1.59% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           2865820500      0.15%      1.74% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1826334869000     98.26%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4175                       # number of times the context was actually changed
+system.cpu.kern.mode_switch_good::idle       0.080914                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      1.401263                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        29483328500      1.59%      1.59% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           2787065000      0.15%      1.74% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1826437652500     98.26%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
index 43cca93f6a8995fb0f911f63c5a529941fe87349..4a2cdb53388cbb457ffa00bb72dfe87690969a02 100644 (file)
@@ -15,7 +15,7 @@ boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 m
 flags_addr=0
 gic_cpu_addr=0
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.arm
+kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
@@ -501,7 +501,7 @@ type=ExeTracer
 
 [system.diskmem]
 type=PhysicalMemory
-file=/dist/m5/system/disks/ael-arm.ext2
+file=/arm/scratch/sysexplr/dist/disks/ael-arm.ext2
 latency=30000
 latency_var=0
 null=false
@@ -553,7 +553,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[6]
+mem_side=system.membus.port[7]
 
 [system.l2c]
 type=BaseCache
@@ -585,7 +585,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[7]
+mem_side=system.membus.port[8]
 
 [system.membus]
 type=Bus
@@ -597,7 +597,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -628,7 +628,7 @@ port=system.membus.port[2]
 
 [system.realview]
 type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
 intrctrl=system.intrctrl
 system=system
 
@@ -836,6 +836,18 @@ update_data=false
 warn_access=
 pio=system.membus.port[4]
 
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clock=1000
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=520095232
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[6]
+
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0
index 7079792890b9e5d86147c0abdac49c4629a6fe18..3ff5b25a63673e5129ff4bc8cd557d8189c7ac24 100755 (executable)
@@ -1,11 +1,13 @@
+Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simout
+Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  9 2011 03:11:31
-gem5 started Aug  9 2011 03:11:37
-gem5 executing on burrito
+gem5 compiled Aug 16 2011 18:25:06
+gem5 started Aug 16 2011 18:26:03
+gem5 executing on nadc-0270
 command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm
+info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 80748998500 because m5_exit instruction encountered
+Exiting @ tick 79671140500 because m5_exit instruction encountered
index d56f088ea91a650ccda218f29d77d9fa2d8af6ee..149a25fbae6437323d79ca8cca8919eedcdb496c 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.080749                       # Number of seconds simulated
-sim_ticks                                 80748998500                       # Number of ticks simulated
+sim_seconds                                  0.079671                       # Number of seconds simulated
+sim_ticks                                 79671140500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 110010                       # Simulator instruction rate (inst/s)
-host_tick_rate                              171236576                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 368976                       # Number of bytes of host memory used
-host_seconds                                   471.56                       # Real time elapsed on the host
-sim_insts                                    51876948                       # Number of instructions simulated
-system.l2c.replacements                         94981                       # number of replacements
-system.l2c.tagsinuse                     38166.685860                       # Cycle average of tags in use
-system.l2c.total_refs                         1060946                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        127430                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          8.325716                       # Average number of references to valid blocks.
+host_inst_rate                                  87754                       # Simulator instruction rate (inst/s)
+host_tick_rate                              134768287                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 390652                       # Number of bytes of host memory used
+host_seconds                                   591.17                       # Real time elapsed on the host
+sim_insts                                    51877383                       # Number of instructions simulated
+system.l2c.replacements                         94989                       # number of replacements
+system.l2c.tagsinuse                     38233.191793                       # Cycle average of tags in use
+system.l2c.total_refs                         1049232                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        127381                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          8.236958                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                  6723.855274                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 31442.830586                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.102598                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.479780                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                     746399                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     123135                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 869534                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                   435298                       # number of Writeback hits
-system.l2c.Writeback_hits::total               435298                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                      24                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  24                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0                    60890                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                60890                       # number of ReadExReq hits
-system.l2c.demand_hits::0                      807289                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      123135                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  930424                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                     807289                       # number of overall hits
-system.l2c.overall_hits::1                     123135                       # number of overall hits
-system.l2c.overall_hits::total                 930424                       # number of overall hits
-system.l2c.ReadReq_misses::0                    21130                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                      101                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                21231                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  1677                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1677                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                 107756                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             107756                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    128886                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                       101                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                128987                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   128886                       # number of overall misses
-system.l2c.overall_misses::1                      101                       # number of overall misses
-system.l2c.overall_misses::total               128987                       # number of overall misses
-system.l2c.ReadReq_miss_latency            1109806000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency             780500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          5651942000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency             6761748000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency            6761748000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                 767529                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 123236                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total             890765                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0               435298                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           435298                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                1701                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            1701                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               168646                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           168646                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                  936175                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  123236                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1059411                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                 936175                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 123236                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1059411                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.027530                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.000820                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.028349                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.985891                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.638948                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.137673                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.000820                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.138493                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.137673                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.000820                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.138493                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   52522.763843                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   10988178.217822                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 11040700.981665                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0   465.414431                       # average UpgradeReq miss latency
+system.l2c.occ_blocks::0                  6845.786735                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 31387.405058                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.104458                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.478934                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0                     745449                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                      96884                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 842333                       # number of ReadReq hits
+system.l2c.Writeback_hits::0                   434303                       # number of Writeback hits
+system.l2c.Writeback_hits::total               434303                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                      53                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  53                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::0                    11                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                11                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::0                    61363                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                61363                       # number of ReadExReq hits
+system.l2c.demand_hits::0                      806812                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                       96884                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  903696                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                     806812                       # number of overall hits
+system.l2c.overall_hits::1                      96884                       # number of overall hits
+system.l2c.overall_hits::total                 903696                       # number of overall hits
+system.l2c.ReadReq_misses::0                    21092                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                       91                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                21183                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                  1724                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              1724                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::0                 107716                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             107716                       # number of ReadExReq misses
+system.l2c.demand_misses::0                    128808                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                        91                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                128899                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                   128808                       # number of overall misses
+system.l2c.overall_misses::1                       91                       # number of overall misses
+system.l2c.overall_misses::total               128899                       # number of overall misses
+system.l2c.ReadReq_miss_latency            1106899000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency             676000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency          5649720000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency             6756619000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency            6756619000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::0                 766541                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                  96975                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total             863516                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0               434303                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           434303                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0                1777                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            1777                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::0                11                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total            11                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0               169079                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           169079                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0                  935620                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                   96975                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1032595                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::0                 935620                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                  96975                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1032595                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0              0.027516                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.000938                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.028454                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.970174                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0            0.637075                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.137671                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.000938                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.138610                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::0              0.137671                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.000938                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.138610                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0   52479.565712                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   12163725.274725                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 12216204.840437                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0   392.111369                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52451.297376                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 52450.146682                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    52463.013826                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1        66948000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 67000463.013826                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   52463.013826                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1       66948000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 67000463.013826                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::0    52454.963977                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    74248560.439560                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 74301015.403538                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0   52454.963977                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   74248560.439560                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 74301015.403538                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -100,44 +104,44 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                           87796                       # number of writebacks
-system.l2c.ReadReq_mshr_hits                       58                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits                        58                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                       58                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                  21173                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                1677                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               107756                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  128929                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 128929                       # number of overall MSHR misses
+system.l2c.writebacks                           87788                       # number of writebacks
+system.l2c.ReadReq_mshr_hits                       54                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits                        54                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits                       54                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses                  21129                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                1724                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses               107716                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses                  128845                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                 128845                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency        848032500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency      67081500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     4311568500                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency        5159601000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency       5159601000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency  28946618000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency    748818447                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency  29695436447                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.027586                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         0.171809                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.199394                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      0.985891                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadReq_mshr_miss_latency        846282000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency      68961500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency     4309813000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency        5156095000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency       5156095000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency  28946860000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency    748497446                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency  29695357446                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.027564                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         0.217881                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.245445                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0      0.970174                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       0.638948                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0       0.637075                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.137719                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          1.046196                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      1.183915                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.137719                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         1.046196                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     1.183915                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40052.543333                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.894454                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40012.328780                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40018.932901                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40018.932901                       # average overall mshr miss latency
+system.l2c.demand_mshr_miss_rate::0          0.137711                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          1.328641                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      1.466352                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0         0.137711                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         1.328641                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     1.466352                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 40053.102371                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.870070                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40010.889747                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency  40017.812100                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40017.812100                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
@@ -146,27 +150,27 @@ system.l2c.soft_prefetch_mshr_full                  0                       # nu
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     28177040                       # DTB read hits
-system.cpu.dtb.read_misses                      72386                       # DTB read misses
-system.cpu.dtb.write_hits                     7691310                       # DTB write hits
-system.cpu.dtb.write_misses                     13556                       # DTB write misses
+system.cpu.dtb.read_hits                     13454003                       # DTB read hits
+system.cpu.dtb.read_misses                      56352                       # DTB read misses
+system.cpu.dtb.write_hits                     7087382                       # DTB write hits
+system.cpu.dtb.write_misses                      9992                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid               33678                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     2922                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      4054                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   1092                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     2710                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      2485                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                    947                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                       940                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 28249426                       # DTB read accesses
-system.cpu.dtb.write_accesses                 7704866                       # DTB write accesses
+system.cpu.dtb.perms_faults                       572                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 13510355                       # DTB read accesses
+system.cpu.dtb.write_accesses                 7097374                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          35868350                       # DTB hits
-system.cpu.dtb.misses                           85942                       # DTB misses
-system.cpu.dtb.accesses                      35954292                       # DTB accesses
-system.cpu.itb.inst_hits                      7355634                       # ITB inst hits
-system.cpu.itb.inst_misses                       7654                       # ITB inst misses
+system.cpu.dtb.hits                          20541385                       # DTB hits
+system.cpu.dtb.misses                           66344                       # DTB misses
+system.cpu.dtb.accesses                      20607729                       # DTB accesses
+system.cpu.itb.inst_hits                      6364119                       # ITB inst hits
+system.cpu.itb.inst_misses                       7846                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -175,502 +179,515 @@ system.cpu.itb.flush_tlb                            2                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid               33678                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     1641                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     1638                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      4616                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      4337                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                  7363288                       # ITB inst accesses
-system.cpu.itb.hits                           7355634                       # DTB hits
-system.cpu.itb.misses                            7654                       # DTB misses
-system.cpu.itb.accesses                       7363288                       # DTB accesses
-system.cpu.numCycles                        161497998                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                  6371965                       # ITB inst accesses
+system.cpu.itb.hits                           6364119                       # DTB hits
+system.cpu.itb.misses                            7846                       # DTB misses
+system.cpu.itb.accesses                       6371965                       # DTB accesses
+system.cpu.numCycles                        159342282                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 13590326                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           11456360                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             648707                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              12127952                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  9362916                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 12557399                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           10608534                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             646709                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              11154990                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  8780554                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                   895596                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect              148738                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           16866017                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       67484906                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    13590326                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           10258512                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      17034266                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 4123173                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                      93207                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               55393473                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                18245                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         90602                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          223                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   7350509                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                337942                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    4453                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples           92525962                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.899758                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.157294                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                   870083                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect              147860                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           16065730                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       58984795                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    12557399                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9650637                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      15473829                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2924896                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                      92331                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               54317634                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                13079                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         97476                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles          352                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   6359256                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                271099                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    4481                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples           88159945                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.843576                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.082771                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 75510639     81.61%     81.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1420262      1.53%     83.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1864587      2.02%     85.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1402898      1.52%     86.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4892259      5.29%     91.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   936046      1.01%     92.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   818442      0.88%     93.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   713663      0.77%     94.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  4967166      5.37%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 72705101     82.47%     82.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1269251      1.44%     83.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1767868      2.01%     85.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1323104      1.50%     87.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4670929      5.30%     92.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   784846      0.89%     93.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   764674      0.87%     94.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   594095      0.67%     95.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  4280077      4.85%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             92525962                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.084152                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.417868                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 18966191                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              54065669                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  15364429                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1171991                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2957682                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              1326698                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 73964                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               80385244                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                241077                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2957682                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 20606631                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                33478689                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       16542065                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  13879452                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               5061443                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               77021348                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                458130                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 143873                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               2652425                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              147                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands            79088993                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             335825078                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        335758422                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             66656                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              51887194                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 27201798                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             847863                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         665654                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  14013888                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             13554810                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             9178167                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads               336                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores              727                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   69117949                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             4041398                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  82091279                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            240337                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        20597655                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     41996969                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1078579                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      92525962                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.887224                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.470662                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total             88159945                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.078808                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.370177                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 18165141                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              52904570                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  13778388                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1284946                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2026900                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              1217125                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 74219                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               71956332                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                242640                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2026900                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 19696589                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                30046666                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       18688452                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  12532114                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               5169224                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               69519785                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                458017                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 271395                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               2649588                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              136                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands            71288380                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             300070248                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        300002932                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             67316                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              51888569                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 19399810                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             812076                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         663924                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  14280198                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             12080470                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             8183550                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           3516652                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          4162890                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   62699092                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             4040128                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  64163344                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            176578                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        14335802                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     27947195                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1077859                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      88159945                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.727806                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.267218                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            58116859     62.81%     62.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            14058568     15.19%     78.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             6650411      7.19%     85.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             4537690      4.90%     90.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6374184      6.89%     96.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1626800      1.76%     98.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6              758213      0.82%     99.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              287091      0.31%     99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              116146      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            57192817     64.87%     64.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14605860     16.57%     81.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7161098      8.12%     89.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             4501948      5.11%     94.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2827013      3.21%     97.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1117751      1.27%     99.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6              514797      0.58%     99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              165433      0.19%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               73228      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        92525962                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        88159945                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   27856      0.57%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      1      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                4535089     92.61%     93.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                334124      6.82%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   31666      2.83%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      2      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 952275     85.11%     87.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                134939     12.06%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2393223      2.92%      2.92% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              42162127     51.36%     54.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                71788      0.09%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                  14      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc              13      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc            883      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc           13      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             29248881     35.63%     89.99% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             8214337     10.01%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2393223      3.73%      3.73% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              39946954     62.26%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                68785      0.11%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    1      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   5      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc            883      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             14271744     22.24%     88.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             7481749     11.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               82091279                       # Type of FU issued
-system.cpu.iq.rate                           0.508311                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     4897070                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.059654                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          261914662                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          94097771                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     62682872                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               16678                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               9625                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses         6496                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               84586375                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                    8751                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           425783                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               64163344                       # Type of FU issued
+system.cpu.iq.rate                           0.402676                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1118882                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.017438                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          217833874                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          81127166                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     59171315                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               14043                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               9868                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         6386                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               62881739                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    7264                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           405736                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4375336                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        13490                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       405193                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2100755                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2901377                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         4794                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        62495                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1106451                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads     17024856                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          9533                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      3460272                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          8665                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2957682                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                21379595                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                254604                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            73328942                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            354348                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              13554810                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              9178167                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            4009809                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  13226                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 41705                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         405193                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         534373                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       174123                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               708496                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              80713996                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              28682342                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1377283                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                2026900                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                18611531                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                438534                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            66914101                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            333018                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              12080470                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              8183550                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            4008088                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  19000                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                218050                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          62495                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         538548                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       174972                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               713520                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              63251439                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              13958320                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            911905                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        169595                       # number of nop insts executed
-system.cpu.iew.exec_refs                     36687563                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 10549834                       # Number of branches executed
-system.cpu.iew.exec_stores                    8005221                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.499783                       # Inst execution rate
-system.cpu.iew.wb_sent                       80082379                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      62689368                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  33196620                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  59589146                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        174881                       # number of nop insts executed
+system.cpu.iew.exec_refs                     21351791                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 10154168                       # Number of branches executed
+system.cpu.iew.exec_stores                    7393471                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.396953                       # Inst execution rate
+system.cpu.iew.wb_sent                       62861793                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      59177701                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  31313815                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  56258797                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.388174                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.557092                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.371387                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.556603                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       52000178                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        19092846                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         2962819                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            623054                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     89568308                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.580564                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.463287                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts       52000613                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        12648879                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         2962269                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            619998                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     86133073                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.603724                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.472813                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     69902534     78.04%     78.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      9240090     10.32%     88.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      2668754      2.98%     91.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      1387483      1.55%     92.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3444879      3.85%     96.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       818955      0.91%     97.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       553093      0.62%     98.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       352878      0.39%     98.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1199642      1.34%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     65560207     76.12%     76.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     10449932     12.13%     88.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      2547278      2.96%     91.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1482527      1.72%     92.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3350826      3.89%     96.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       701267      0.81%     97.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       459898      0.53%     98.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       309587      0.36%     98.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1271551      1.48%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     89568308                       # Number of insts commited each cycle
-system.cpu.commit.count                      52000178                       # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total     86133073                       # Number of insts commited each cycle
+system.cpu.commit.count                      52000613                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       16256886                       # Number of memory references committed
-system.cpu.commit.loads                       9179474                       # Number of loads committed
+system.cpu.commit.refs                       16256192                       # Number of memory references committed
+system.cpu.commit.loads                       9179093                       # Number of loads committed
 system.cpu.commit.membars                           3                       # Number of memory barriers committed
-system.cpu.commit.branches                    8429121                       # Number of branches committed
+system.cpu.commit.branches                    8429232                       # Number of branches committed
 system.cpu.commit.fp_insts                       6017                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  42423758                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               530189                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               1199642                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                  42424073                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               530211                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               1271551                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    158520597                       # The number of ROB reads
-system.cpu.rob.rob_writes                   145188457                       # The number of ROB writes
-system.cpu.timesIdled                         1073623                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        68972036                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                    51876948                       # Number of Instructions Simulated
-system.cpu.committedInsts_total              51876948                       # Number of Instructions Simulated
-system.cpu.cpi                               3.113098                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.113098                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.321223                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.321223                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                356113054                       # number of integer regfile reads
-system.cpu.int_regfile_writes                64703490                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      5644                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                     1932                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                88421211                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 512467                       # number of misc regfile writes
-system.cpu.icache.replacements                 513097                       # number of replacements
-system.cpu.icache.tagsinuse                496.956364                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  6781343                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 513609                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  13.203318                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle             5987250000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            496.956364                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.970618                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0             6781343                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         6781343                       # number of ReadReq hits
-system.cpu.icache.demand_hits::0              6781343                       # number of demand (read+write) hits
+system.cpu.rob.rob_reads                    148569921                       # The number of ROB reads
+system.cpu.rob.rob_writes                   131336271                       # The number of ROB writes
+system.cpu.timesIdled                         1042391                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        71182337                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                    51877383                       # Number of Instructions Simulated
+system.cpu.committedInsts_total              51877383                       # Number of Instructions Simulated
+system.cpu.cpi                               3.071517                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.071517                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.325572                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.325572                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                282588210                       # number of integer regfile reads
+system.cpu.int_regfile_writes                61106256                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      4893                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     1856                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                78190097                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 511386                       # number of misc regfile writes
+system.cpu.icache.replacements                 514643                       # number of replacements
+system.cpu.icache.tagsinuse                498.228732                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  5803201                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 515155                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  11.264961                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle             4757853000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            498.228732                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.973103                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::0             5803201                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         5803201                       # number of ReadReq hits
+system.cpu.icache.demand_hits::0              5803201                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          6781343                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0             6781343                       # number of overall hits
+system.cpu.icache.demand_hits::total          5803201                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::0             5803201                       # number of overall hits
 system.cpu.icache.overall_hits::1                   0                       # number of overall hits
-system.cpu.icache.overall_hits::total         6781343                       # number of overall hits
-system.cpu.icache.ReadReq_misses::0            569051                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        569051                       # number of ReadReq misses
-system.cpu.icache.demand_misses::0             569051                       # number of demand (read+write) misses
+system.cpu.icache.overall_hits::total         5803201                       # number of overall hits
+system.cpu.icache.ReadReq_misses::0            555943                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        555943                       # number of ReadReq misses
+system.cpu.icache.demand_misses::0             555943                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         569051                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0            569051                       # number of overall misses
+system.cpu.icache.demand_misses::total         555943                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::0            555943                       # number of overall misses
 system.cpu.icache.overall_misses::1                 0                       # number of overall misses
-system.cpu.icache.overall_misses::total        569051                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency     8379802495                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency      8379802495                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency     8379802495                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0         7350394                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      7350394                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0          7350394                       # number of demand (read+write) accesses
+system.cpu.icache.overall_misses::total        555943                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency     8279205988                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency      8279205988                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency     8279205988                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::0         6359144                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      6359144                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::0          6359144                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      7350394                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0         7350394                       # number of overall (read+write) accesses
+system.cpu.icache.demand_accesses::total      6359144                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::0         6359144                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      7350394                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0       0.077418                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0        0.077418                       # miss rate for demand accesses
+system.cpu.icache.overall_accesses::total      6359144                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::0       0.087424                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::0        0.087424                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0       0.077418                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::0       0.087424                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 14725.925260                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::0 14892.184969                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 14725.925260                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::0 14892.184969                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 14725.925260                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::0 14892.184969                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      1742497                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs      1847492                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               223                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               239                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs  7813.887892                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs  7730.092050                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                    42974                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits             55439                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits              55439                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits             55439                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses          513612                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses           513612                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses          513612                       # number of overall MSHR misses
+system.cpu.icache.writebacks                    43333                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits             40711                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits              40711                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits             40711                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses          515232                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses           515232                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses          515232                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency   6212945497                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency   6212945497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency   6212945497                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency   6216481992                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency   6216481992                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency   6216481992                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency      5831500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency      5831500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.069875                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::0     0.081022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0     0.069875                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::0     0.081022                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0     0.069875                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::0     0.081022                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12096.573867                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12096.573867                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12096.573867                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 12065.403531                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 12065.403531                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 12065.403531                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 424539                       # number of replacements
-system.cpu.dcache.tagsinuse                511.742336                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 14092021                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 425051                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  33.153718                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                 422430                       # number of replacements
+system.cpu.dcache.tagsinuse                511.738850                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 13008876                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 422942                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  30.758061                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               48622000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            511.742336                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999497                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0             9263117                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         9263117                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0            4618459                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4618459                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::0        103676                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       103676                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::0         104941                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       104941                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::0             13881576                       # number of demand (read+write) hits
+system.cpu.dcache.occ_blocks::0            511.738850                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999490                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::0             8178281                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         8178281                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::0            4620670                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4620670                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::0        103371                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       103371                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::0         104399                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       104399                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::0             12798951                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13881576                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0            13881576                       # number of overall hits
+system.cpu.dcache.demand_hits::total         12798951                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::0            12798951                       # number of overall hits
 system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13881576                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::0            533393                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        533393                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0          2044461                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2044461                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::0         6632                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total         6632                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::0            2577854                       # number of demand (read+write) misses
+system.cpu.dcache.overall_hits::total        12798951                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::0            482976                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        482976                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::0          2042377                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2042377                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::0         6546                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total         6546                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::0           11                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           11                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::0            2525353                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2577854                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0           2577854                       # number of overall misses
+system.cpu.dcache.demand_misses::total        2525353                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::0           2525353                       # number of overall misses
 system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2577854                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     7849628500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   81637522770                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency     99339500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency     89487151270                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    89487151270                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0         9796510                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9796510                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0        6662920                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6662920                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::0       110308                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       110308                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::0       104941                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       104941                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0         16459430                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_misses::total       2525353                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     7135135000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   80554552279                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency     99000500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency       159000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency     87689687279                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    87689687279                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::0         8661257                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      8661257                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::0        6663047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6663047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::0       109917                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       109917                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::0       104410                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       104410                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::0         15324304                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     16459430                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0        16459430                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15324304                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::0        15324304                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     16459430                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0       0.054447                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0      0.306842                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0     0.060123                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::0        0.156619                       # miss rate for demand accesses
+system.cpu.dcache.overall_accesses::total     15324304                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0       0.055763                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0      0.306523                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::0     0.059554                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::0     0.000105                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::0        0.164794                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0       0.156619                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::0       0.164794                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 14716.407039                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::0 14773.270307                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 39931.073652                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::0 39441.568466                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14978.814837                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15123.816071                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 34713.816713                       # average overall miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14454.545455                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::0 34723.734575                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 34713.816713                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0 34723.734575                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      9881489                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       841000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              1354                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              29                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  7297.997784                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets        29000                       # average number of cycles each access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs      7890493                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       750500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              1025                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              25                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  7698.041951                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        30020                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   392324                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            282537                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1874151                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits         1046                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            2156688                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           2156688                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          250856                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         170310                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses         5586                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           421166                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          421166                       # number of overall MSHR misses
+system.cpu.dcache.writebacks                   390970                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            234674                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1871578                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits          927                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            2106252                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           2106252                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          248302                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         170799                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses         5619                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses           11                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           419101                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          419101                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   3355794000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   6558107489                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency     66303500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   9913901489                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   9913901489                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency  38199628000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency    946945664                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency  39146573664                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.025607                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency   3306153500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   6559898993                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency     66534000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency       121000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   9866052493                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   9866052493                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency  38199897500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency    945697168                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency  39145594668                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.028668                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.025561                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.025634                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.050640                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.051120                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0     0.025588                       # mshr miss rate for demand accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::0     0.000105                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::0     0.027349                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0     0.025588                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::0     0.027349                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13377.371879                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38506.884440                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11869.584676                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23539.178113                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23539.178113                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13315.049818                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38407.127635                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11840.896957                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency        11000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23540.990103                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23540.990103                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
index 334b73543e3230845e8ff375ef31088f078e49ec..97c12ec46d4b9060e7b7262eee33a3ce607f8249 100644 (file)
Binary files a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal and b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal differ
index 70d5b6fa2aed64a4fbdfa0a17affdde57b3fd116..3bb35a8826408783906db7b4c7ff0504791439bd 100644 (file)
@@ -15,7 +15,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/chips/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=timing
 memories=system.physmem
@@ -1300,7 +1300,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
+image_file=/chips/pd/randd/dist/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1320,7 +1320,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
index cf1d2e1e5abb9509eaeac70a59a96ac9efa6e206..1778e84dc8992d2cd90a44ff5df525e5c2e35cb5 100755 (executable)
@@ -1,13 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 14 2011 17:50:33
-gem5 started Aug 14 2011 17:50:50
-gem5 executing on burrito
+gem5 compiled Aug 15 2011 11:12:24
+gem5 started Aug 15 2011 11:17:26
+gem5 executing on u200439-lin.austin.arm.com
 command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /chips/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5147635094500 because m5_exit instruction encountered
+Exiting @ tick 5151638875500 because m5_exit instruction encountered
index 220e5eac6332daeae23d49d0d1f6a5d84e87edf3..34270b518bfa04343c46f1aee1a857fb0555213b 100644 (file)
@@ -1,97 +1,97 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.147635                       # Number of seconds simulated
-sim_ticks                                5147635094500                       # Number of ticks simulated
+sim_seconds                                  5.151639                       # Number of seconds simulated
+sim_ticks                                5151638875500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 351632                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2155130798                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 384428                       # Number of bytes of host memory used
-host_seconds                                  2388.55                       # Real time elapsed on the host
-sim_insts                                   839890138                       # Number of instructions simulated
-system.l2c.replacements                        168889                       # number of replacements
-system.l2c.tagsinuse                     38220.032298                       # Cycle average of tags in use
-system.l2c.total_refs                         3756292                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        202498                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         18.549773                       # Average number of references to valid blocks.
+host_inst_rate                                 136272                       # Simulator instruction rate (inst/s)
+host_tick_rate                              835912815                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 404376                       # Number of bytes of host memory used
+host_seconds                                  6162.89                       # Real time elapsed on the host
+sim_insts                                   839831731                       # Number of instructions simulated
+system.l2c.replacements                        168782                       # number of replacements
+system.l2c.tagsinuse                     38205.196893                       # Cycle average of tags in use
+system.l2c.total_refs                         3762867                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        202558                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         18.576739                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                 11771.329873                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 26448.702425                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.179616                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.403575                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    2324685                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     121813                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2446498                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                  1589010                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1589010                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                     347                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 347                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0                   150926                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               150926                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     2475611                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      121813                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2597424                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    2475611                       # number of overall hits
-system.l2c.overall_hits::1                     121813                       # number of overall hits
-system.l2c.overall_hits::total                2597424                       # number of overall hits
-system.l2c.ReadReq_misses::0                    64844                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                       78                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                64922                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  3952                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3952                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                 141925                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             141925                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    206769                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                        78                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                206847                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   206769                       # number of overall misses
-system.l2c.overall_misses::1                       78                       # number of overall misses
-system.l2c.overall_misses::total               206847                       # number of overall misses
-system.l2c.ReadReq_miss_latency            3405563500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency           38740500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          7426067500                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency            10831631000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency           10831631000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                2389529                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 121891                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2511420                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0              1589010                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1589010                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                4299                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            4299                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               292851                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           292851                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 2682380                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  121891                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2804271                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                2682380                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 121891                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2804271                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.027137                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.000640                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.027777                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.919284                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.484632                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.077084                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.000640                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.077724                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.077084                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.000640                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.077724                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   52519.331010                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   43661070.512821                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 43713589.843830                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0  9802.758097                       # average UpgradeReq miss latency
+system.l2c.occ_blocks::0                 11735.089031                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 26470.107863                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.179063                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.403902                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0                    2331067                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                     125887                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                2456954                       # number of ReadReq hits
+system.l2c.Writeback_hits::0                  1588356                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1588356                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                     357                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 357                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::0                   150454                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               150454                       # number of ReadExReq hits
+system.l2c.demand_hits::0                     2481521                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                      125887                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2607408                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                    2481521                       # number of overall hits
+system.l2c.overall_hits::1                     125887                       # number of overall hits
+system.l2c.overall_hits::total                2607408                       # number of overall hits
+system.l2c.ReadReq_misses::0                    64696                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                       91                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                64787                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                  3960                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              3960                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::0                 142190                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             142190                       # number of ReadExReq misses
+system.l2c.demand_misses::0                    206886                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                        91                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                206977                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                   206886                       # number of overall misses
+system.l2c.overall_misses::1                       91                       # number of overall misses
+system.l2c.overall_misses::total               206977                       # number of overall misses
+system.l2c.ReadReq_miss_latency            3398610000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency           37586500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency          7439728500                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency            10838338500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency           10838338500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::0                2395763                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                 125978                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2521741                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0              1588356                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          1588356                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0                4317                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            4317                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0               292644                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           292644                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0                 2688407                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                  125978                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2814385                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::0                2688407                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                 125978                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2814385                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0              0.027004                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.000722                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.027727                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.917304                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0            0.485880                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.076955                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.000722                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.077677                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::0              0.076955                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.000722                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.077677                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0   52531.995796                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   37347362.637363                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 37399894.633158                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0  9491.540404                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52323.885855                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 52322.445320                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    52385.178629                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    138867064.102564                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 138919449.281193                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   52385.178629                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   138867064.102564                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 138919449.281193                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::0    52387.974537                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    119102620.879121                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 119155008.853658                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0   52387.974537                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   119102620.879121                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 119155008.853658                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -100,88 +100,88 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          142854                       # number of writebacks
+system.l2c.writebacks                          142964                       # number of writebacks
 system.l2c.ReadReq_mshr_hits                        2                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits                         2                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits                        2                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                  64920                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                3952                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               141925                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  206845                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 206845                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_misses                  64785                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                3960                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses               142190                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses                  206975                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                 206975                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency       2614002500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency     158446500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     5695372500                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency        8309375000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency       8309375000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency  61532786000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency   1222293500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency  62755079500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.027169                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         0.532607                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.559776                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      0.919284                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadReq_mshr_miss_latency       2608555500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency     158748000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency     5705556000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency        8314111500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency       8314111500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency  61533015500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency   1222291500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency  62755307000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.027041                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         0.514256                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.541298                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0      0.917304                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       0.484632                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0       0.485880                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.077112                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          1.696967                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      1.774079                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.077112                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         1.696967                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     1.774079                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40264.979975                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40092.737854                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40129.452175                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40171.988687                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40171.988687                       # average overall mshr miss latency
+system.l2c.demand_mshr_miss_rate::0          0.076988                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          1.642946                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      1.719934                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0         0.076988                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         1.642946                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     1.719934                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 40264.806668                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40087.878788                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40126.281736                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency  40169.641261                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40169.641261                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.replacements                     47572                       # number of replacements
-system.iocache.tagsinuse                     0.153668                       # Cycle average of tags in use
+system.iocache.replacements                     47575                       # number of replacements
+system.iocache.tagsinuse                     0.165993                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     47588                       # Sample count of references to valid blocks.
+system.iocache.sampled_refs                     47591                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              4994556805000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1                 0.153668                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.009604                       # Average percentage of cache occupancy
+system.iocache.warmup_cycle              4994554828000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::1                 0.165993                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.010375                       # Average percentage of cache occupancy
 system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
 system.iocache.overall_hits::0                      0                       # number of overall hits
 system.iocache.overall_hits::1                      0                       # number of overall hits
 system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.ReadReq_misses::1                  907                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              907                       # number of ReadReq misses
+system.iocache.ReadReq_misses::1                  909                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              909                       # number of ReadReq misses
 system.iocache.WriteReq_misses::1               46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
 system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 47627                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47627                       # number of demand (read+write) misses
+system.iocache.demand_misses::1                 47629                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47629                       # number of demand (read+write) misses
 system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                47627                       # number of overall misses
-system.iocache.overall_misses::total            47627                       # number of overall misses
-system.iocache.ReadReq_miss_latency         113709932                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency       6375573160                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency         6489283092                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency        6489283092                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::1                907                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            907                       # number of ReadReq accesses(hits+misses)
+system.iocache.overall_misses::1                47629                       # number of overall misses
+system.iocache.overall_misses::total            47629                       # number of overall misses
+system.iocache.ReadReq_miss_latency         113908932                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency       6372665160                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency         6486574092                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency        6486574092                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::1                909                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            909                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::1             46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               47627                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47627                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::1               47629                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47629                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              47627                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47627                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::1              47629                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47629                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
@@ -191,37 +191,37 @@ system.iocache.overall_miss_rate::0          no_value                       # mi
 system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 125369.274531                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 125312.356436                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 136463.466610                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 136401.223459                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
 system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 136252.190816                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 136189.592307                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 136252.190816                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 136189.592307                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs      68827406                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs      68832452                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                11262                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                11274                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  6111.472740                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6105.415292                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                       46667                       # number of writebacks
+system.iocache.writebacks                       46668                       # number of writebacks
 system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
 system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.ReadReq_mshr_misses                907                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses                909                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses             46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses               47627                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses              47627                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses               47629                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses              47629                       # number of overall MSHR misses
 system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.ReadReq_mshr_miss_latency     66523980                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency   3945823756                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency    4012347736                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency   4012347736                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency     66617982                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3942909802                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    4009527784                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   4009527784                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
@@ -235,10 +235,10 @@ system.iocache.demand_mshr_miss_rate::total          inf                       #
 system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency 73345.071665                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 84456.844092                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency 84245.233502                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency 84245.233502                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency 73287.108911                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 84394.473502                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 84182.489324                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 84182.489324                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
@@ -255,140 +255,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu.numCycles                        449675417                       # number of cpu cycles simulated
+system.cpu.numCycles                        449440116                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 91353557                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           91353557                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1252427                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              90165441                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 83892399                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 91251942                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           91251942                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1248755                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              89986362                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 83883414                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           28404587                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      452020244                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    91353557                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           83892399                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     171490466                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6282228                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     138765                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               82802558                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                39799                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         48979                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          284                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9973165                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                538692                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    4066                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          287848736                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.084298                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.403265                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           28443020                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      451559426                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    91251942                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           83883414                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     171343402                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6212938                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     155361                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               82525667                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                36777                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         48486                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles          319                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9929678                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                556225                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    4240                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          287412747                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.086350                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.403158                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                116937192     40.62%     40.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1491081      0.52%     41.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72826914     25.30%     66.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1443953      0.50%     66.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1857439      0.65%     67.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4043841      1.40%     68.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1607058      0.56%     69.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  2086920      0.73%     70.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 85554338     29.72%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                116615067     40.57%     40.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1502902      0.52%     41.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72824785     25.34%     66.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1334009      0.46%     66.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1960992      0.68%     67.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  4008264      1.39%     68.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1565099      0.54%     69.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  2187101      0.76%     70.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 85414528     29.72%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            287848736                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.203154                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.005214                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 33515134                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              79162809                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 165880226                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               4367269                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4923298                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              883825801                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   605                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4923298                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 37698163                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                52621688                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       10095648                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 165755555                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              16754384                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              879127879                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 13400                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               11681979                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               2180375                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           881488672                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1726997540                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1726996684                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               856                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             843288974                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 38199691                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             489429                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         491577                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  43341957                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             19857410                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10789691                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           3385955                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          3355339                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  872068801                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded              901279                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 866609285                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            183699                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        32269790                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     48278487                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         149791                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     287848736                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         3.010641                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.369672                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            287412747                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.203035                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.004715                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 33501642                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              78913894                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 165819274                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               4318222                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4859715                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              883193903                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   620                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4859715                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 37708099                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                52423571                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       10078562                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 165633752                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              16709048                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              878518097                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 13834                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               11653087                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               2148761                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents                8                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           880915046                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1725729327                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1725728311                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              1016                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             843223982                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 37691057                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             489641                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         492542                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  43070507                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             19803638                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10755992                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           3194647                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          3198862                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  871443389                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded              900411                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 866326988                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            165756                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        31682293                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     47289832                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         148825                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     287412747                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         3.014226                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.369116                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            82414213     28.63%     28.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            23159181      8.05%     36.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            14360314      4.99%     41.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             9848044      3.42%     45.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            79584318     27.65%     72.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4908294      1.71%     74.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72848439     25.31%     99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              591496      0.21%     99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              134437      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            82109167     28.57%     28.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            23029898      8.01%     36.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            14429245      5.02%     41.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             9845202      3.43%     45.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            79549613     27.68%     72.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4871174      1.69%     74.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72852960     25.35%     99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              572992      0.20%     99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              152496      0.05%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       287848736                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       287412747                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  190888      9.04%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1791204     84.82%     93.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                129613      6.14%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  198235      9.39%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1790050     84.77%     94.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                123321      5.84%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            300110      0.03%      0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             831340529     95.93%     95.96% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            300321      0.03%      0.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             831068974     95.93%     95.96% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     95.96% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     95.96% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     95.96% # Type of FU issued
@@ -417,252 +418,252 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     95.96% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     95.96% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     95.96% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     95.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             25503279      2.94%     98.91% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9465367      1.09%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             25494883      2.94%     98.91% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9462810      1.09%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              866609285                       # Type of FU issued
-system.cpu.iq.rate                           1.927188                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2111705                       # FU busy when requested
+system.cpu.iq.FU_type_0::total              866326988                       # Type of FU issued
+system.cpu.iq.rate                           1.927569                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2111606                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.002437                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2023502478                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         905270549                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    855795997                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 118                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                426                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           39                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              868420821                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                      59                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1311302                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_inst_queue_reads         2022483969                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         904056296                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    855552025                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 163                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                498                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           60                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              868138190                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      83                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1311048                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4519097                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14074                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        32279                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2365528                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4470522                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        13972                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        31558                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2334229                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      7816755                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        157456                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      7818225                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        154758                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4923298                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                33675049                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               6020092                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           872970080                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            307769                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              19857410                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10789736                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             900477                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                5569363                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 25535                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          32279                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         904299                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       527474                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1431773                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             864483471                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25041287                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2125813                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                4859715                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                33597470                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               6022609                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           872343800                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            300494                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              19803638                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10756022                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             899609                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                5535817                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 26257                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          31558                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         897955                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       529978                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1427933                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             864227296                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25025491                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2099691                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     34281165                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 86747902                       # Number of branches executed
-system.cpu.iew.exec_stores                    9239878                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.922461                       # Inst execution rate
-system.cpu.iew.wb_sent                      863862887                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     855796036                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 671971409                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1172569006                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     34264216                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 86728541                       # Number of branches executed
+system.cpu.iew.exec_stores                    9238725                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.922898                       # Inst execution rate
+system.cpu.iew.wb_sent                      863623792                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     855552085                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 671682498                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1172193952                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.903142                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.573076                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.903595                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.573013                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      839890138                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        32974049                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          751486                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1258131                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    282941233                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.968426                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.859611                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts      839831731                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        32406647                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          751584                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           1254294                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    282568841                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.972131                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.859839                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    102772882     36.32%     36.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     13081684      4.62%     40.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4919909      1.74%     42.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     76957003     27.20%     69.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4031247      1.42%     71.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1851904      0.65%     71.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1144492      0.40%     72.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     71610729     25.31%     97.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6571383      2.32%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    102495617     36.27%     36.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     13009464      4.60%     40.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4878881      1.73%     42.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     76962899     27.24%     69.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4022439      1.42%     71.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1857740      0.66%     71.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1158664      0.41%     72.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     71619728     25.35%     97.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6563409      2.32%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    282941233                       # Number of insts commited each cycle
-system.cpu.commit.count                     839890138                       # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total    282568841                       # Number of insts commited each cycle
+system.cpu.commit.count                     839831731                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       23762518                       # Number of memory references committed
-system.cpu.commit.loads                      15338310                       # Number of loads committed
+system.cpu.commit.refs                       23754906                       # Number of memory references committed
+system.cpu.commit.loads                      15333113                       # Number of loads committed
 system.cpu.commit.membars                         801                       # Number of memory barriers committed
-system.cpu.commit.branches                   85528433                       # Number of branches committed
+system.cpu.commit.branches                   85519800                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 768507409                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 768449243                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               6571383                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               6563409                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1149152761                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1750664129                       # The number of ROB writes
-system.cpu.timesIdled                         3067558                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       161826681                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   839890138                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             839890138                       # Number of Instructions Simulated
-system.cpu.cpi                               0.535398                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.535398                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.867770                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.867770                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1406887924                       # number of integer regfile reads
-system.cpu.int_regfile_writes               857851212                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        39                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               282323555                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 407360                       # number of misc regfile writes
-system.cpu.icache.replacements                1023301                       # number of replacements
-system.cpu.icache.tagsinuse                510.501366                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  8883561                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                1023813                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   8.676937                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            54617484000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            510.501366                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.997073                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0             8883561                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8883561                       # number of ReadReq hits
-system.cpu.icache.demand_hits::0              8883561                       # number of demand (read+write) hits
+system.cpu.rob.rob_reads                   1148162427                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1749350545                       # The number of ROB writes
+system.cpu.timesIdled                         3069835                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       162027369                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   839831731                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             839831731                       # Number of Instructions Simulated
+system.cpu.cpi                               0.535155                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.535155                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.868618                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.868618                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1406651660                       # number of integer regfile reads
+system.cpu.int_regfile_writes               857603051                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        60                       # number of floating regfile reads
+system.cpu.misc_regfile_reads               282221875                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 407507                       # number of misc regfile writes
+system.cpu.icache.replacements                1029232                       # number of replacements
+system.cpu.icache.tagsinuse                510.471706                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  8833811                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                1029744                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   8.578648                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            54597932000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            510.471706                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.997015                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::0             8833811                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8833811                       # number of ReadReq hits
+system.cpu.icache.demand_hits::0              8833811                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8883561                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0             8883561                       # number of overall hits
+system.cpu.icache.demand_hits::total          8833811                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::0             8833811                       # number of overall hits
 system.cpu.icache.overall_hits::1                   0                       # number of overall hits
-system.cpu.icache.overall_hits::total         8883561                       # number of overall hits
-system.cpu.icache.ReadReq_misses::0           1089602                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1089602                       # number of ReadReq misses
-system.cpu.icache.demand_misses::0            1089602                       # number of demand (read+write) misses
+system.cpu.icache.overall_hits::total         8833811                       # number of overall hits
+system.cpu.icache.ReadReq_misses::0           1095865                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1095865                       # number of ReadReq misses
+system.cpu.icache.demand_misses::0            1095865                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1089602                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0           1089602                       # number of overall misses
+system.cpu.icache.demand_misses::total        1095865                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::0           1095865                       # number of overall misses
 system.cpu.icache.overall_misses::1                 0                       # number of overall misses
-system.cpu.icache.overall_misses::total       1089602                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency    16315202989                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency     16315202989                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency    16315202989                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0         9973163                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9973163                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0          9973163                       # number of demand (read+write) accesses
+system.cpu.icache.overall_misses::total       1095865                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency    16411974488                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency     16411974488                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency    16411974488                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::0         9929676                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9929676                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::0          9929676                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9973163                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0         9973163                       # number of overall (read+write) accesses
+system.cpu.icache.demand_accesses::total      9929676                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::0         9929676                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9973163                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0       0.109253                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0        0.109253                       # miss rate for demand accesses
+system.cpu.icache.overall_accesses::total      9929676                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::0       0.110363                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::0        0.110363                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0       0.109253                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::0       0.110363                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 14973.543541                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::0 14976.273983                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 14973.543541                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::0 14976.273983                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 14973.543541                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::0 14976.273983                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      2502991                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs      2523491                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               249                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               250                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 10052.172691                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 10093.964000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                     1566                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits             63225                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits              63225                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits             63225                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses         1026377                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses          1026377                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses         1026377                       # number of overall MSHR misses
+system.cpu.icache.writebacks                     1562                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits             63554                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits              63554                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits             63554                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses         1032311                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses          1032311                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses         1032311                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency  12387818491                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency  12387818491                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency  12387818491                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency  12460934991                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency  12460934991                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency  12460934991                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.102914                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::0     0.103962                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0     0.102914                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::0     0.103962                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0     0.102914                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::0     0.103962                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12069.462284                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12069.462284                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12069.462284                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 12070.911761                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 12070.911761                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 12070.911761                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements        10573                       # number of replacements
-system.cpu.itb_walker_cache.tagsinuse        6.015451                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs          26778                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs        10582                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs         2.530524                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5110516160500                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::1     6.015451                       # Average occupied blocks per context
-system.cpu.itb_walker_cache.occ_percent::1     0.375966                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::1        26928                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        26928                       # number of ReadReq hits
+system.cpu.itb_walker_cache.replacements        11904                       # number of replacements
+system.cpu.itb_walker_cache.tagsinuse        6.021281                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.total_refs          25742                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.sampled_refs        11916                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.avg_refs         2.160289                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.warmup_cycle 5113551809500                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.occ_blocks::1     6.021281                       # Average occupied blocks per context
+system.cpu.itb_walker_cache.occ_percent::1     0.376330                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.ReadReq_hits::1        25787                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        25787                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::1            3                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            3                       # number of WriteReq hits
 system.cpu.itb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::1        26931                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        26931                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::1        25790                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        25790                       # number of demand (read+write) hits
 system.cpu.itb_walker_cache.overall_hits::0            0                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::1        26931                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        26931                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::1        11444                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total        11444                       # number of ReadReq misses
+system.cpu.itb_walker_cache.overall_hits::1        25790                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        25790                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::1        12756                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total        12756                       # number of ReadReq misses
 system.cpu.itb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::1        11444                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total        11444                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::1        12756                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total        12756                       # number of demand (read+write) misses
 system.cpu.itb_walker_cache.overall_misses::0            0                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::1        11444                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total        11444                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency    147254000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency    147254000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency    147254000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::1        38372                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        38372                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.overall_misses::1        12756                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total        12756                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency    165450000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency    165450000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency    165450000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::1        38543                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        38543                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::1            3                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            3                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::1        38375                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        38375                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::1        38546                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        38546                       # number of demand (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::1        38375                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        38375                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::1     0.298238                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.overall_accesses::1        38546                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        38546                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::1     0.330955                       # miss rate for ReadReq accesses
 system.cpu.itb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::1     0.298215                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::1     0.330929                       # miss rate for demand accesses
 system.cpu.itb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
 system.cpu.itb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::1     0.298215                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::1     0.330929                       # miss rate for overall accesses
 system.cpu.itb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12867.354072                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12970.366886                       # average ReadReq miss latency
 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.cpu.itb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12867.354072                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12970.366886                       # average overall miss latency
 system.cpu.itb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu.itb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12867.354072                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12970.366886                       # average overall miss latency
 system.cpu.itb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -672,83 +673,83 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks           1953                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks           2156                       # number of writebacks
 system.cpu.itb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
 system.cpu.itb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
-system.cpu.itb_walker_cache.ReadReq_mshr_misses        11444                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses        11444                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses        11444                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses        12756                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses        12756                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses        12756                       # number of overall MSHR misses
 system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency    112503000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency    112503000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency    112503000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency    126704000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency    126704000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency    126704000                       # number of overall MSHR miss cycles
 system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1     0.298238                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1     0.330955                       # mshr miss rate for ReadReq accesses
 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.itb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::1     0.298215                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::1     0.330929                       # mshr miss rate for demand accesses
 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
 system.cpu.itb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::1     0.298215                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::1     0.330929                       # mshr miss rate for overall accesses
 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency  9830.741000                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency  9830.741000                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency  9830.741000                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency  9932.894324                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency  9932.894324                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency  9932.894324                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.itb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
 system.cpu.itb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements       121016                       # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse       13.855490                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs         127830                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs       121032                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs         1.056167                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5101318853000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::1    13.855490                       # Average occupied blocks per context
-system.cpu.dtb_walker_cache.occ_percent::1     0.865968                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::1       127830                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       127830                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.replacements       123389                       # number of replacements
+system.cpu.dtb_walker_cache.tagsinuse       13.858352                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.total_refs         128795                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.sampled_refs       123405                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.avg_refs         1.043677                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.warmup_cycle 5101298251000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.occ_blocks::1    13.858352                       # Average occupied blocks per context
+system.cpu.dtb_walker_cache.occ_percent::1     0.866147                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::1       128795                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       128795                       # number of ReadReq hits
 system.cpu.dtb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::1       127830                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       127830                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::1       128795                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       128795                       # number of demand (read+write) hits
 system.cpu.dtb_walker_cache.overall_hits::0            0                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::1       127830                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       127830                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::1       121934                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total       121934                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.overall_hits::1       128795                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       128795                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::1       124284                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total       124284                       # number of ReadReq misses
 system.cpu.dtb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::1       121934                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total       121934                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::1       124284                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total       124284                       # number of demand (read+write) misses
 system.cpu.dtb_walker_cache.overall_misses::0            0                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::1       121934                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total       121934                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency   1683985000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency   1683985000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency   1683985000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::1       249764                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       249764                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.overall_misses::1       124284                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total       124284                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency   1723739000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency   1723739000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency   1723739000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::1       253079                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       253079                       # number of ReadReq accesses(hits+misses)
 system.cpu.dtb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::1       249764                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       249764                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::1       253079                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       253079                       # number of demand (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::1       249764                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       249764                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::1     0.488197                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.overall_accesses::1       253079                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       253079                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::1     0.491088                       # miss rate for ReadReq accesses
 system.cpu.dtb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::1     0.488197                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::1     0.491088                       # miss rate for demand accesses
 system.cpu.dtb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
 system.cpu.dtb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::1     0.488197                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::1     0.491088                       # miss rate for overall accesses
 system.cpu.dtb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13810.627061                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13869.355669                       # average ReadReq miss latency
 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.cpu.dtb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13810.627061                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13869.355669                       # average overall miss latency
 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu.dtb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13810.627061                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13869.355669                       # average overall miss latency
 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -758,136 +759,136 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks          38699                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks          38359                       # number of writebacks
 system.cpu.dtb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
 system.cpu.dtb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses       121934                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses       121934                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses       121934                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses       124284                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses       124284                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses       124284                       # number of overall MSHR misses
 system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency   1314199000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency   1314199000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency   1314199000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency   1347076500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency   1347076500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency   1347076500                       # number of overall MSHR miss cycles
 system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1     0.488197                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1     0.491088                       # mshr miss rate for ReadReq accesses
 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1     0.488197                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1     0.491088                       # mshr miss rate for demand accesses
 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1     0.488197                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1     0.491088                       # mshr miss rate for overall accesses
 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10777.953647                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10777.953647                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10777.953647                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10838.696051                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10838.696051                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10838.696051                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dtb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
 system.cpu.dtb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1658649                       # number of replacements
-system.cpu.dcache.tagsinuse                511.998343                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 17949632                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1659161                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  10.818499                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                1658768                       # number of replacements
+system.cpu.dcache.tagsinuse                511.997453                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 17937343                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1659280                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  10.810317                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               13135000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            511.998343                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999997                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0            11386734                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        11386734                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0            6540638                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6540638                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::0             17927372                       # number of demand (read+write) hits
+system.cpu.dcache.occ_blocks::0            511.997453                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999995                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::0            11377605                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        11377605                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::0            6537446                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6537446                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::0             17915051                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         17927372                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0            17927372                       # number of overall hits
+system.cpu.dcache.demand_hits::total         17915051                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::0            17915051                       # number of overall hits
 system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
-system.cpu.dcache.overall_hits::total        17927372                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::0           2451014                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2451014                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0          1874260                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1874260                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::0            4325274                       # number of demand (read+write) misses
+system.cpu.dcache.overall_hits::total        17915051                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::0           2443873                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2443873                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::0          1875033                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1875033                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::0            4318906                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4325274                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0           4325274                       # number of overall misses
+system.cpu.dcache.demand_misses::total        4318906                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::0           4318906                       # number of overall misses
 system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4325274                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    36760499500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   62950533530                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     99711033030                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    99711033030                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0        13837748                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13837748                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0        8414898                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8414898                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0         22252646                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_misses::total       4318906                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    36695573000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   63002180530                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     99697753530                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    99697753530                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::0        13821478                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13821478                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::0        8412479                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8412479                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::0         22233957                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     22252646                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0        22252646                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::total     22233957                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::0        22233957                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     22252646                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0       0.177125                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0      0.222731                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::0        0.194371                       # miss rate for demand accesses
+system.cpu.dcache.overall_accesses::total     22233957                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0       0.176817                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0      0.222887                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::0        0.194248                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0       0.194371                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::0       0.194248                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 14998.078142                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::0 15015.335494                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 33586.873502                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::0 33600.571579                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 23053.113636                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::0 23084.029504                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 23053.113636                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0 23084.029504                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs   1060124132                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      6661500                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             70229                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             395                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 15095.247433                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 16864.556962                       # average number of cycles each access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs   1066704607                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      6645500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             69708                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             391                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 15302.470405                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 16996.163683                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1546792                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits           1084106                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1577234                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            2661340                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           2661340                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1366908                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         297026                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1663934                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1663934                       # number of overall MSHR misses
+system.cpu.dcache.writebacks                  1546279                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits           1076649                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1578166                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            2654815                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           2654815                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1367224                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         296867                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          1664091                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1664091                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  18014700500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   9717717632                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  27732418132                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  27732418132                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency  86947187500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1385675500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency  88332863000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.098781                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency  18012012500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   9730106607                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  27742119107                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  27742119107                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency  86947466500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1385748000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency  88333214500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.098920                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.035298                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.035289                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0     0.074775                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::0     0.074845                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0     0.074775                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::0     0.074845                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13179.160924                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32716.723896                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 16666.777728                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 16666.777728                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13174.148859                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32775.979166                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 16671.034882                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 16671.034882                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
index 4a81b3d8fa31230e0d205f90cbf2cfe3992a5542..c90ea128a2d7986370b22b9ba0c8231b68ca6217 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:18:43
-gem5 started Jul  9 2011 01:04:44
+gem5 compiled Jul 15 2011 18:02:03
+gem5 started Jul 16 2011 01:23:12
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -23,4 +23,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 33955329500 because target called exit()
+Exiting @ tick 34059187000 because target called exit()
index cba4db906de5163c046dd2a3e702c134257fa90f..4687ee8e50ab95a411c95520dcc0b1d54b9a443f 100644 (file)
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.033955                       # Number of seconds simulated
-sim_ticks                                 33955329500                       # Number of ticks simulated
+sim_seconds                                  0.034059                       # Number of seconds simulated
+sim_ticks                                 34059187000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  64380                       # Simulator instruction rate (inst/s)
-host_tick_rate                               23956859                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 390580                       # Number of bytes of host memory used
-host_seconds                                  1417.35                       # Real time elapsed on the host
-sim_insts                                    91249680                       # Number of instructions simulated
+host_inst_rate                                  66126                       # Simulator instruction rate (inst/s)
+host_tick_rate                               24681632                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 390692                       # Number of bytes of host memory used
+host_seconds                                  1379.94                       # Real time elapsed on the host
+sim_insts                                    91249685                       # Number of instructions simulated
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -51,300 +51,300 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                         67910660                       # number of cpu cycles simulated
+system.cpu.numCycles                         68118375                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 28244508                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           22629080                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1414299                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              25112752                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 24086234                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 28264225                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           22664811                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1422221                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              25307717                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 24243974                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                   121674                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               12927                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           16032012                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      135606393                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    28244508                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           24207908                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      33529641                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6010411                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               13862842                       # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS                   113570                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               12949                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           16006756                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      135411326                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    28264225                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           24357544                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      33580343                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 5963217                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               14095577                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    2                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           146                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  15326942                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                412294                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           67880028                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.019137                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.751435                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles           149                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  15302646                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                409174                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           68087836                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.009786                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.740415                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 34404593     50.68%     50.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  6761573      9.96%     60.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  5940167      8.75%     69.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4952932      7.30%     76.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2875416      4.24%     80.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1738729      2.56%     83.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1585314      2.34%     85.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3119241      4.60%     90.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  6502063      9.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 34562720     50.76%     50.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  6711035      9.86%     60.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  6005592      8.82%     69.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5006532      7.35%     76.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2908486      4.27%     81.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1809535      2.66%     83.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1604855      2.36%     86.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3043201      4.47%     90.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  6435880      9.45%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             67880028                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.415907                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.996835                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 18687820                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              12370381                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  31414917                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                983964                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4422946                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              4499724                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 32863                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              133147735                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 31368                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4422946                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 20483676                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                  968140                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles        8316666                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  30556439                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               3132161                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              128513000                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    19                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 288426                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               1795950                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents               14                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           149798068                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             559931036                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        559926436                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              4600                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             107429111                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 42368952                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             668763                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         669407                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   7564309                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             30008124                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             6129267                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1456420                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           516652                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  120184129                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded              637684                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 107766890                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             87998                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        29120799                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     70180475                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          83323                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      67880028                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.587608                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.759573                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total             68087836                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.414928                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.987883                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 18687372                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              12574245                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  31471424                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                979506                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4375289                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4503619                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 30122                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              132907777                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 31137                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4375289                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 20501176                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 1029913                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles        8340304                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  30584541                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               3256613                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              128189435                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    22                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 288306                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               1934414                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents               17                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           149540723                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             558211899                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        558194258                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             17641                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             107429119                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 42111599                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             671866                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         673475                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   7619625                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             29869898                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6025284                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1488843                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           609505                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  119834900                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded              639591                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 107581328                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             88511                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        28762009                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     69412751                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          85229                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      68087836                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.580037                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.751787                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            25488891     37.55%     37.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            14322408     21.10%     58.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            10131350     14.93%     73.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             8118242     11.96%     85.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4318324      6.36%     91.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2337223      3.44%     95.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2482658      3.66%     99.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              475759      0.70%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              205173      0.30%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            25433380     37.35%     37.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14679481     21.56%     58.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            10190142     14.97%     73.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             8113823     11.92%     85.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4222569      6.20%     92.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2284074      3.35%     95.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2481556      3.64%     99.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              482376      0.71%     99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              200435      0.29%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        67880028                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        68087836                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   57394     10.75%     10.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     27      0.01%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 196663     36.84%     47.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                279761     52.40%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   54498     10.46%     10.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     27      0.01%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 191599     36.78%     47.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                274842     52.76%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              75833735     70.37%     70.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                10982      0.01%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               1      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt             110      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc            182      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.38% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26490777     24.58%     94.96% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             5431101      5.04%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              75715085     70.38%     70.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                10984      0.01%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               1      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt             147      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc            460      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26496641     24.63%     95.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             5358008      4.98%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              107766890                       # Type of FU issued
-system.cpu.iq.rate                           1.586892                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                      533845                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.004954                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          284035005                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         150060826                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    103585232                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 646                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                916                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          298                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              108300410                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     325                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           363305                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              107581328                       # Type of FU issued
+system.cpu.iq.rate                           1.579329                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                      520966                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.004843                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          283858560                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         149349424                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    103392608                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                1409                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               1914                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          392                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              108101654                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     640                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           354645                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      7432292                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        39631                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       124361                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1382559                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      7294065                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        41309                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       115131                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1278575                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads            2                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         30723                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         30521                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4422946                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  101110                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 18559                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           120860696                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            802315                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              30008124                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              6129267                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             632825                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  10731                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   224                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         124361                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1290705                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       209600                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1500305                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             105816782                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              26069680                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1950108                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                4375289                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  100045                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 19331                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           120513426                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            799995                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              29869898                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              6025284                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             634734                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  10994                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  1046                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         115131                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1306667                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       208134                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1514801                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             105623962                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              26069380                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1957366                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         38883                       # number of nop insts executed
-system.cpu.iew.exec_refs                     31358457                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 21276544                       # Number of branches executed
-system.cpu.iew.exec_stores                    5288777                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.558176                       # Inst execution rate
-system.cpu.iew.wb_sent                      104017986                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     103585530                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  60888984                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  97986900                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         38935                       # number of nop insts executed
+system.cpu.iew.exec_refs                     31285154                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 21282801                       # Number of branches executed
+system.cpu.iew.exec_stores                    5215774                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.550594                       # Inst execution rate
+system.cpu.iew.wb_sent                      103821828                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     103393000                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  60779146                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  97604196                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.525321                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.621399                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.517843                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.622710                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       91262289                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        29597995                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          554361                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1394652                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     63457083                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.438173                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.204542                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts       91262294                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        29250695                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          554362                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           1405283                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     63712548                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.432407                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.197517                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     29495808     46.48%     46.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     16759375     26.41%     72.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      5313552      8.37%     81.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4030004      6.35%     87.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1955590      3.08%     90.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       709900      1.12%     91.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       461456      0.73%     92.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       205982      0.32%     92.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      4525416      7.13%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     29657705     46.55%     46.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     16839810     26.43%     72.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      5318691      8.35%     81.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      3965283      6.22%     87.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2147247      3.37%     90.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       617953      0.97%     91.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       460758      0.72%     92.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       194856      0.31%     92.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4510245      7.08%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     63457083                       # Number of insts commited each cycle
-system.cpu.commit.count                      91262289                       # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total     63712548                       # Number of insts commited each cycle
+system.cpu.commit.count                      91262294                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27322539                       # Number of memory references committed
-system.cpu.commit.loads                      22575831                       # Number of loads committed
+system.cpu.commit.refs                       27322541                       # Number of memory references committed
+system.cpu.commit.loads                      22575832                       # Number of loads committed
 system.cpu.commit.membars                        3888                       # Number of memory barriers committed
-system.cpu.commit.branches                   18722425                       # Number of branches committed
+system.cpu.commit.branches                   18722426                       # Number of branches committed
 system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  72533138                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                  72533142                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                56148                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               4525416                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               4510245                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    179786217                       # The number of ROB reads
-system.cpu.rob.rob_writes                   246157217                       # The number of ROB writes
-system.cpu.timesIdled                            1527                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           30632                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                    91249680                       # Number of Instructions Simulated
-system.cpu.committedInsts_total              91249680                       # Number of Instructions Simulated
-system.cpu.cpi                               0.744229                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.744229                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.343672                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.343672                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                502577811                       # number of integer regfile reads
-system.cpu.int_regfile_writes               122258624                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       150                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      373                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               189862426                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                  11512                       # number of misc regfile writes
+system.cpu.rob.rob_reads                    179709558                       # The number of ROB reads
+system.cpu.rob.rob_writes                   245415120                       # The number of ROB writes
+system.cpu.timesIdled                            1511                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           30539                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                    91249685                       # Number of Instructions Simulated
+system.cpu.committedInsts_total              91249685                       # Number of Instructions Simulated
+system.cpu.cpi                               0.746505                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.746505                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.339575                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.339575                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                501634552                       # number of integer regfile reads
+system.cpu.int_regfile_writes               122095043                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       176                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      493                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               189665669                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                  11514                       # number of misc regfile writes
 system.cpu.icache.replacements                      2                       # number of replacements
-system.cpu.icache.tagsinuse                615.328313                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 15326008                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    726                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               21110.203857                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                611.147709                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 15301726                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    719                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               21281.955494                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            615.328313                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.300453                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               15326008                       # number of ReadReq hits
-system.cpu.icache.demand_hits                15326008                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               15326008                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  934                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   934                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  934                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       32832500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        32832500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       32832500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           15326942                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            15326942                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           15326942                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000061                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000061                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000061                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 35152.569593                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 35152.569593                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 35152.569593                       # average overall miss latency
+system.cpu.icache.occ_blocks::0            611.147709                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.298412                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               15301726                       # number of ReadReq hits
+system.cpu.icache.demand_hits                15301726                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               15301726                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  920                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   920                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  920                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       32420000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        32420000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       32420000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           15302646                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            15302646                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           15302646                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000060                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000060                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000060                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 35239.130435                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35239.130435                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35239.130435                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -354,142 +354,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               207                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                207                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               207                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             727                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              727                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             727                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits               201                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                201                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               201                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             719                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              719                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             719                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     25012500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     25012500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     25012500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     24811500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     24811500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     24811500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000047                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000047                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate     0.000047                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34405.089409                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34405.089409                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34405.089409                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34508.344924                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34508.344924                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34508.344924                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 943475                       # number of replacements
-system.cpu.dcache.tagsinuse               3548.617037                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 29160006                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 947571                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  30.773426                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            12936791000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           3548.617037                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.866362                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               24566182                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits               4581344                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits             6728                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits              5751                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits                29147526                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               29147526                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               998551                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              153637                       # number of WriteReq misses
+system.cpu.dcache.replacements                 943449                       # number of replacements
+system.cpu.dcache.tagsinuse               3548.737651                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 29169762                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 947545                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  30.784566                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            12973953000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           3548.737651                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.866391                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               24598373                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits               4558911                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits             6726                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits              5752                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                29157284                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               29157284                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               981426                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              176070                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses              7                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses               1152188                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              1152188                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     5569139000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    4384723397                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency       126500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency      9953862397                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency     9953862397                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           25564733                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses               1157496                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1157496                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     5458949500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    4506223422                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency       124500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency      9965172922                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency     9965172922                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           25579799                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses           4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses         6735                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses          5751                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            30299714                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           30299714                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.039060                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.032447                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.001039                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.038026                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.038026                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency  5577.220392                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 28539.501533                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 18071.428571                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency  8639.095701                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency  8639.095701                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     23292477                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses         6733                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses          5752                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            30314780                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           30314780                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.038367                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.037185                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.001040                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.038183                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.038183                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency  5562.262972                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 25593.362992                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency  8609.250418                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency  8609.250418                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     23278498                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              8136                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              8128                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  2862.890487                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  2863.988435                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   942916                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits             85616                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           119000                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks                   942894                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits             79978                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           129972                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits            7                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits             204616                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits            204616                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          912935                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses          34637                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           947572                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          947572                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_hits             209950                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits            209950                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          901448                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses          46098                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           947546                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          947546                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   2294888500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   1057301024                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   3352189524                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   3352189524                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   2249272000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   1085068550                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   3334340550                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   3334340550                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.035711                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.007315                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.031273                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.031273                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2513.747967                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30525.190519                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  3537.662071                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  3537.662071                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.035241                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.009736                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.031257                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.031257                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2495.176649                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23538.299926                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  3518.922089                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  3518.922089                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                   747                       # number of replacements
-system.cpu.l2cache.tagsinuse              9154.979721                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1625557                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 15570                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                104.403147                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                   744                       # number of replacements
+system.cpu.l2cache.tagsinuse              9122.566359                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1596024                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 15565                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                102.539287                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           397.893639                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          8757.086082                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.012143                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.267245                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                912568                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              942916                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               20133                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 932701                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                932701                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                1056                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
+system.cpu.l2cache.occ_blocks::0           396.658867                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          8725.907492                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.012105                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.266294                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                901114                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              942894                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits               31559                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 932673                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                932673                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                1052                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses             14540                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                15596                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               15596                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      36204000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency    498983500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      535187500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     535187500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            913624                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          942916                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses           34673                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             948297                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            948297                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.001156                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.419346                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.016446                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.016446                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34284.090909                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34317.984869                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34315.689920                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34315.689920                       # average overall miss latency
+system.cpu.l2cache.demand_misses                15592                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               15592                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency      36036000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency    498937500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      534973500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     534973500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            902166                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          942894                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses           46099                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             948265                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            948265                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.001166                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.315408                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.016443                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.016443                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34254.752852                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34314.821183                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34310.768343                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34310.768343                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -502,28 +499,24 @@ system.cpu.l2cache.writebacks                      32                       # nu
 system.cpu.l2cache.ReadReq_mshr_hits               10                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits                10                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits               10                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           1046                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses           1042                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses        14540                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           15586                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          15586                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses           15582                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          15582                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     32557500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    451767000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    484324500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    484324500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency     32402000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    451783000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    484185000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    484185000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.001145                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.419346                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.016436                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.016436                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31125.717017                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31500                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31070.632737                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31074.329526                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31074.329526                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.001155                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.315408                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.016432                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.016432                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31095.969290                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31071.733150                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31073.353870                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31073.353870                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 43f4aeb7318ab9d6f6f49437682b036932269d29..bc7ad177a6149ff9b95dd526e83bb924e06f8fd1 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:18:15
-gem5 started Jul  8 2011 19:53:01
+gem5 compiled Jul 15 2011 18:01:24
+gem5 started Jul 15 2011 21:20:28
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -19,9 +19,8 @@ simplex iterations         : 1502
 flow value                 : 4990014995
 new implicit arcs          : 23867
 active arcs                : 25772
-info: Increasing stack size by one page.
 simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 72726971500 because target called exit()
+Exiting @ tick 72477044500 because target called exit()
index 8534b7b7b6ece1803fe0b880a6f09c495d84e3df..705599adbc9bab8c26b738a87d9307b81b7e285c 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.072727                       # Number of seconds simulated
-sim_ticks                                 72726971500                       # Number of ticks simulated
+sim_seconds                                  0.072477                       # Number of seconds simulated
+sim_ticks                                 72477044500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  68290                       # Simulator instruction rate (inst/s)
-host_tick_rate                               17852786                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 388028                       # Number of bytes of host memory used
-host_seconds                                  4073.70                       # Real time elapsed on the host
+host_inst_rate                                  77321                       # Simulator instruction rate (inst/s)
+host_tick_rate                               20144405                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 388184                       # Number of bytes of host memory used
+host_seconds                                  3597.87                       # Real time elapsed on the host
 sim_insts                                   278192519                       # Number of instructions simulated
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        145453944                       # number of cpu cycles simulated
+system.cpu.numCycles                        144954090                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 39128056                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           39128056                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1285795                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              34407152                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 33889591                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 38824502                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           38824502                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1297953                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              34176085                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 33665907                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           29588069                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      209386921                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    39128056                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33889591                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      65111619                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                11621082                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               39294448                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   23                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           127                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  28796477                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                238037                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          144111677                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.561755                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.288092                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           29621269                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      208413424                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    38824502                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33665907                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      64871665                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                11337306                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               39226989                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   33                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           173                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  28797824                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                223613                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          143548717                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.559587                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.289378                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 81461032     56.53%     56.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3926007      2.72%     59.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2843085      1.97%     61.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4618863      3.21%     64.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  6929331      4.81%     69.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  5578828      3.87%     73.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  7691595      5.34%     78.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  4554481      3.16%     81.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 26508455     18.39%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 81263708     56.61%     56.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3814966      2.66%     59.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2940174      2.05%     61.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4531865      3.16%     64.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  6958174      4.85%     69.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5381940      3.75%     73.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  7686471      5.35%     78.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4497983      3.13%     81.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 26473436     18.44%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            144111677                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.269006                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.439541                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 42334644                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              29762063                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  54385999                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               7511580                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               10117391                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              364671921                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               10117391                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 49398641                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4827860                       # Number of cycles rename is blocking
+system.cpu.fetch.rateDist::total            143548717                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.267840                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.437789                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 42470221                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              29708132                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  53823823                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               7717953                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9828588                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              362980420                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                9828588                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 49423752                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 5177939                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles           6920                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  54606982                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              25153883                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              359809940                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    28                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 255433                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              20983622                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           323256675                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             885580834                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        885576522                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              4312                       # Number of floating rename lookups
+system.cpu.rename.RunCycles                  54367682                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              24743836                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              358046310                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    26                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 279275                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              20623155                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           321830310                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             881760386                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        881756685                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              3701                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             248344192                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 74912483                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                481                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            474                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  57974009                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            116578971                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            38504515                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          58165962                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         12487625                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  352625128                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 468                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 320274168                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            148663                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        74313113                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    111731092                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             22                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     144111677                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.222403                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.776502                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 73486118                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                479                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            472                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  57368685                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            115894254                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            38422039                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          63771824                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11957885                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  350732960                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 465                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 318496999                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            118138                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        72405796                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    110903478                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             19                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     143548717                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.218738                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.761833                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            34558203     23.98%     23.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            19108427     13.26%     37.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            27976000     19.41%     56.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            28361257     19.68%     76.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            18381125     12.75%     89.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            10394236      7.21%     96.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2736273      1.90%     98.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             2552596      1.77%     99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8               43560      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            32402965     22.57%     22.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            21621693     15.06%     37.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            28790762     20.06%     57.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            27748357     19.33%     77.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            16847570     11.74%     88.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            10612221      7.39%     96.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             3153195      2.20%     98.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             2297476      1.60%     99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               74478      0.05%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       144111677                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       143548717                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   26349      1.28%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1847389     89.85%     91.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                182278      8.87%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   25496      0.77%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                3039528     91.70%     92.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                249529      7.53%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             16711      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             182479275     56.98%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  71      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.98% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            103720585     32.38%     89.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            34057526     10.63%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             181568475     57.01%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  37      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            102910190     32.31%     89.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            34001586     10.68%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              320274168                       # Type of FU issued
-system.cpu.iq.rate                           2.201894                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2056016                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006420                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          786864122                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         427256918                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    315787747                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 570                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               2776                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          224                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              322313191                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     282                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         45099386                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              318496999                       # Type of FU issued
+system.cpu.iq.rate                           2.197227                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3314553                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010407                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          783974996                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         423448386                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    314158938                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 410                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               2380                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          163                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              321794634                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     207                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         44143933                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     25799583                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         7450                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       343486                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      7064764                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     25114866                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         7244                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       332312                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6982288                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3530                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         14483                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3439                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         14779                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               10117391                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  811347                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                102359                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           352625596                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             16735                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             116578971                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             38504515                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                468                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    471                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 58728                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         343486                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1207902                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       198656                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1406558                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             317936612                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             103056411                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2337556                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                9828588                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  873179                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                111050                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           350733425                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             18952                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             115894254                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             38422039                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                465                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    328                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 81820                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         332312                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1218982                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       194001                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1412983                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             316233239                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             102244590                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2263760                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    136663121                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31969004                       # Number of branches executed
-system.cpu.iew.exec_stores                   33606710                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.185823                       # Inst execution rate
-system.cpu.iew.wb_sent                      316589546                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     315787971                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 236874431                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 330545022                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    135866033                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31754283                       # Number of branches executed
+system.cpu.iew.exec_stores                   33621443                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.181610                       # Inst execution rate
+system.cpu.iew.wb_sent                      314904091                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     314159101                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 236907780                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 336010619                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.171051                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.716618                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.167301                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.705060                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      278192519                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        74441748                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        72547467                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             446                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1285812                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    133994286                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.076152                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.625929                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1297979                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    133720129                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.080409                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.620850                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     52509499     39.19%     39.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     24995000     18.65%     57.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     17512781     13.07%     70.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     12345203      9.21%     80.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3532539      2.64%     82.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      3553321      2.65%     85.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      3000350      2.24%     87.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1127257      0.84%     88.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     15418336     11.51%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     52184328     39.03%     39.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     25094085     18.77%     57.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     17016190     12.73%     70.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12703052      9.50%     80.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3715852      2.78%     82.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      3516909      2.63%     85.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3092720      2.31%     87.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1223319      0.91%     88.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     15173674     11.35%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    133994286                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    133720129                       # Number of insts commited each cycle
 system.cpu.commit.count                     278192519                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      122219139                       # Number of memory references committed
@@ -255,49 +255,49 @@ system.cpu.commit.branches                   29309710                       # Nu
 system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 278186227                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              15418336                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              15173674                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    471210217                       # The number of ROB reads
-system.cpu.rob.rob_writes                   715407828                       # The number of ROB writes
-system.cpu.timesIdled                           40427                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         1342267                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    469286441                       # The number of ROB reads
+system.cpu.rob.rob_writes                   711329741                       # The number of ROB writes
+system.cpu.timesIdled                           41147                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         1405373                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   278192519                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             278192519                       # Number of Instructions Simulated
-system.cpu.cpi                               0.522854                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.522854                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.912581                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.912581                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                557964995                       # number of integer regfile reads
-system.cpu.int_regfile_writes               283520691                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       186                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      177                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               204022079                       # number of misc regfile reads
-system.cpu.icache.replacements                     65                       # number of replacements
-system.cpu.icache.tagsinuse                828.162739                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 28795146                       # Total number of references to valid blocks.
+system.cpu.cpi                               0.521057                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.521057                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.919177                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.919177                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                555871897                       # number of integer regfile reads
+system.cpu.int_regfile_writes               282032504                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       111                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      126                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               202657544                       # number of misc regfile reads
+system.cpu.icache.replacements                     67                       # number of replacements
+system.cpu.icache.tagsinuse                826.564016                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 28796514                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                   1029                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               27983.620991                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               27984.950437                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            828.162739                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.404376                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               28795146                       # number of ReadReq hits
-system.cpu.icache.demand_hits                28795146                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               28795146                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1331                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1331                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1331                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       47629500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        47629500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       47629500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           28796477                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            28796477                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           28796477                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000046                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000046                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000046                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 35784.748310                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 35784.748310                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 35784.748310                       # average overall miss latency
+system.cpu.icache.occ_blocks::0            826.564016                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.403596                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               28796514                       # number of ReadReq hits
+system.cpu.icache.demand_hits                28796514                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               28796514                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1310                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1310                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1310                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       47269000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        47269000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       47269000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           28797824                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            28797824                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           28797824                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000045                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000045                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000045                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 36083.206107                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 36083.206107                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 36083.206107                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -307,166 +307,166 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               301                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                301                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               301                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits               280                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                280                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               280                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses            1030                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses             1030                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses            1030                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     36247000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     36247000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     36247000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     36240000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     36240000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     36240000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000036                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000036                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate     0.000036                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35191.262136                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35191.262136                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35191.262136                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35184.466019                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35184.466019                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35184.466019                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2072723                       # number of replacements
-system.cpu.dcache.tagsinuse               4076.250938                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 86852791                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2076819                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  41.820106                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            24787226000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4076.250938                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.995178                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               55654749                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              31198033                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                86852782                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               86852782                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              2230129                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              241718                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               2471847                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2471847                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    14270225000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    4343136672                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     18613361672                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    18613361672                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           57884878                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                2072715                       # number of replacements
+system.cpu.dcache.tagsinuse               4076.040338                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 86994905                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2076811                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  41.888696                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            24878005000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4076.040338                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.995127                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               55797094                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              31197802                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                86994896                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               86994896                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              2231267                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              241949                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               2473216                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2473216                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    14264095500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    4347965193                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     18612060693                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    18612060693                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           58028361                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses          31439751                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            89324629                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           89324629                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.038527                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.007688                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.027673                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.027673                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency  6398.833879                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 17967.783417                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency  7530.143116                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency  7530.143116                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       275500                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses            89468112                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           89468112                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.038451                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.007696                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.027644                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.027644                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency  6392.823226                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 17970.585508                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency  7525.448927                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency  7525.448927                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       284000                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                82                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                84                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  3359.756098                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  3380.952381                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1446764                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            259013                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           136012                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits             395025                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits            395025                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1971116                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         105706                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          2076822                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         2076822                       # number of overall MSHR misses
+system.cpu.dcache.writebacks                  1447001                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            260149                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           136252                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits             396401                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits            396401                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1971118                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         105697                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          2076815                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         2076815                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   5556895000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   1872300172                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   7429195172                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   7429195172                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   5560817000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   1877216693                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   7438033693                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   7438033693                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.034052                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.033968                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.003362                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.023250                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.023250                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2819.161835                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17712.335837                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  3577.193988                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  3577.193988                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate      0.023213                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.023213                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2821.148708                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17760.359263                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  3581.461850                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  3581.461850                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                 49102                       # number of replacements
-system.cpu.l2cache.tagsinuse             18807.221207                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3317038                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 77109                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 43.017521                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             18748.930580                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3317286                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 77110                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 43.020179                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          6724.342247                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         12082.878960                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.205211                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.368740                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               1937588                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             1446764                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               63709                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                2001297                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               2001297                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               34500                       # number of ReadReq misses
+system.cpu.l2cache.occ_blocks::0          6700.733856                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         12048.196724                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.204490                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.367682                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               1937583                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             1447001                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits               63701                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                2001284                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               2001284                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               34508                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses             42053                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                76553                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               76553                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1179515000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   1442921000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     2622436000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    2622436000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1972088                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         1446764                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_misses             42051                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                76559                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               76559                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1180262000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   1442869500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     2623131500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    2623131500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1972091                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         1447001                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          105762                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            2077850                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           2077850                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.017494                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_accesses          105752                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            2077843                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           2077843                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.017498                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.397619                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.036842                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.036842                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34188.840580                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34311.963475                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34256.475906                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34256.475906                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs        32000                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate       0.397638                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.036845                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.036845                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34202.561725                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34312.370693                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34262.875691                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34262.875691                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs        35000                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs               13                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs               14                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  2461.538462                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs         2500                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   29195                       # number of writebacks
+system.cpu.l2cache.writebacks                   29193                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          34500                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses          34508                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        42053                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           76553                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          76553                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        42051                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           76559                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          76559                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1070219000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1070240500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1309892500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   2380111500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   2380111500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1310019500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   2380260000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   2380260000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.017494                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.017498                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.397619                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.036842                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.036842                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.840580                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.397638                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.036845                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.036845                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31014.272053                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31148.610087                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31091.028438                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31091.028438                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31153.111698                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31090.531486                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31090.531486                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 9edf46eb36b30b19eb8bfe796846f3dedda34a4a..6f903bc98df8868f271507ae4d6d19205db9a3b8 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:18:43
-gem5 started Jul  9 2011 01:33:51
+gem5 compiled Jul 15 2011 18:02:03
+gem5 started Jul 16 2011 01:32:47
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -67,4 +67,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 302517583000 because target called exit()
+Exiting @ tick 298073533000 because target called exit()
index 954793f3dd9b6e5f1a2922b6538390cb3ad7f9e3..2fcdf0e96595b7d730cdea9f5cd94a7ba775cb58 100644 (file)
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.302518                       # Number of seconds simulated
-sim_ticks                                302517583000                       # Number of ticks simulated
+sim_seconds                                  0.298074                       # Number of seconds simulated
+sim_ticks                                298073533000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  48998                       # Simulator instruction rate (inst/s)
-host_tick_rate                               25853029                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 270368                       # Number of bytes of host memory used
-host_seconds                                 11701.44                       # Real time elapsed on the host
-sim_insts                                   573342442                       # Number of instructions simulated
+host_inst_rate                                  55166                       # Simulator instruction rate (inst/s)
+host_tick_rate                               28679876                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 269720                       # Number of bytes of host memory used
+host_seconds                                 10393.12                       # Real time elapsed on the host
+sim_insts                                   573342447                       # Number of instructions simulated
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -51,299 +51,299 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        605035167                       # number of cpu cycles simulated
+system.cpu.numCycles                        596147067                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                237948628                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          189643896                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           18525471                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             200558633                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                165003293                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                233829808                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          186147170                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           18448610                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             196945817                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                163449853                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                 12776963                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect             2655849                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          165318082                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1053599180                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   237948628                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          177780256                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     271034430                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                85133152                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              100456864                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 3051                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        121417                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 151931838                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               4658920                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          600617430                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.083903                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.829133                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                 12453913                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect             2627969                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          162380426                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1034385613                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   233829808                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          175903766                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     266887423                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                82201728                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              101000880                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 4224                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        119559                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 149451578                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               4693812                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          591651753                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.074862                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.819629                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                329595233     54.88%     54.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 24765043      4.12%     59.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 43080599      7.17%     66.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 41413060      6.90%     73.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 43530596      7.25%     80.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 16033141      2.67%     82.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 19523127      3.25%     86.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 16376620      2.73%     88.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 66300011     11.04%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                324776586     54.89%     54.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 24968353      4.22%     59.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 42079547      7.11%     66.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 41036258      6.94%     73.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 43058687      7.28%     80.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 15845137      2.68%     83.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 19209353      3.25%     86.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 16779568      2.84%     89.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 63898264     10.80%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            600617430                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.393281                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.741385                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                185610198                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              93209648                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 249465251                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               8754516                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               63577817                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             34830541                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                109065                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1190327461                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                219958                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               63577817                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                203483134                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                12711979                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       52382429                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 240021493                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              28440578                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1124560978                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   631                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                9752153                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              15058133                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents             1694                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1243412483                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            4977837521                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       4977834393                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              3128                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             672201344                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                571211134                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2776537                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2776073                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  72944066                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            210041655                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           130199534                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          69466757                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         73938650                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  989222584                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             4552609                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 764881922                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1674381                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       418150078                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1236634953                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         674707                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     600617430                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.273493                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.529486                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            591651753                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.392235                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.735118                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                182259766                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              93638385                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 246087836                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               8499427                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               61166339                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             34309417                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 95729                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1169323827                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                222317                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               61166339                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                199917017                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                12999514                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       52654373                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 236541446                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              28373064                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1103035585                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   553                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                9425467                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              15260638                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents             2023                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1222978410                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            4879529633                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       4879526297                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              3336                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             672201352                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                550777016                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2758214                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2758162                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  72689740                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            205506720                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           126653600                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          67829085                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         74819363                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  969401999                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             4509720                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 756022991                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1531556                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       398123182                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1180507714                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         631817                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     591651753                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.277818                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.523431                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           269133638     44.81%     44.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           116546536     19.40%     64.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            93441125     15.56%     79.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            61796479     10.29%     90.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            37339082      6.22%     96.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            12656566      2.11%     98.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             5425017      0.90%     99.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3357457      0.56%     99.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              921530      0.15%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           262870171     44.43%     44.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           115951413     19.60%     64.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            93032822     15.72%     79.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            60874777     10.29%     90.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            37273328      6.30%     96.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            12385550      2.09%     98.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             5290297      0.89%     99.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3168401      0.54%     99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              804994      0.14%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       600617430                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       591651753                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  286700      3.30%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5674602     65.33%     68.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2725077     31.37%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  275664      3.50%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5340824     67.91%     71.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2248514     28.59%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             522376749     68.30%     68.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               381409      0.05%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  80      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            170546214     22.30%     90.64% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            71577467      9.36%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             517172409     68.41%     68.41% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               381200      0.05%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 134      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            168107388     22.24%     90.69% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            70361857      9.31%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              764881922                       # Type of FU issued
-system.cpu.iq.rate                           1.264194                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     8686379                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.011356                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2140741838                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1412472990                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    713443043                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 196                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                472                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total              756022991                       # Type of FU issued
+system.cpu.iq.rate                           1.268182                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     7865002                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010403                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2113093981                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1372453088                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    706634766                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 304                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                520                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              773568201                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     100                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          6159543                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              763887839                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     154                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          6326745                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     83268468                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        32978                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       628275                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     72595427                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     78733524                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        32052                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       425394                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     69049484                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        27007                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           156                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        27275                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           239                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               63577817                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 2968769                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                160563                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1003649799                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts          12343350                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             210041655                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            130199534                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            2755333                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  81778                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 10213                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         628275                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       18784960                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      6284429                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             25069389                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             737887948                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             162551175                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          26993974                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               61166339                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 3065417                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                178437                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           983562638                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts          12157762                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             205506720                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            126653600                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            2737845                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  99480                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  4232                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         425394                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       18747710                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      6190012                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             24937722                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             730148660                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             160105072                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          25874323                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       9874606                       # number of nop insts executed
-system.cpu.iew.exec_refs                    230127290                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                150192140                       # Number of branches executed
-system.cpu.iew.exec_stores                   67576115                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.219579                       # Inst execution rate
-system.cpu.iew.wb_sent                      726019609                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     713443059                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 405782893                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 732949927                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       9650919                       # number of nop insts executed
+system.cpu.iew.exec_refs                    226764096                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                149136596                       # Number of branches executed
+system.cpu.iew.exec_stores                   66659024                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.224779                       # Inst execution rate
+system.cpu.iew.wb_sent                      718776639                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     706634782                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 402647843                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 726069262                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.179176                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.553630                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.185336                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.554558                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      574686326                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       428980158                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         3877902                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          20816789                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    537039614                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.070100                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.725106                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts      574686331                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       408895774                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         3877903                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          20690983                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    530485415                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.083322                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.748938                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    281877385     52.49%     52.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    136335503     25.39%     77.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     48132590      8.96%     86.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     21242728      3.96%     90.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     19119215      3.56%     94.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      6739612      1.25%     95.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8597333      1.60%     97.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3363443      0.63%     97.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11631805      2.17%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    277701641     52.35%     52.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    135265417     25.50%     77.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     46444883      8.76%     86.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     21050080      3.97%     90.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     18829655      3.55%     94.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7074631      1.33%     95.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8453874      1.59%     97.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3355983      0.63%     97.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     12309251      2.32%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    537039614                       # Number of insts commited each cycle
-system.cpu.commit.count                     574686326                       # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total    530485415                       # Number of insts commited each cycle
+system.cpu.commit.count                     574686331                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      184377293                       # Number of memory references committed
-system.cpu.commit.loads                     126773186                       # Number of loads committed
+system.cpu.commit.refs                      184377295                       # Number of memory references committed
+system.cpu.commit.loads                     126773187                       # Number of loads committed
 system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
-system.cpu.commit.branches                  120192371                       # Number of branches committed
+system.cpu.commit.branches                  120192372                       # Number of branches committed
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 473702221                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 473702225                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              11631805                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              12309251                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1529067155                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2071246317                       # The number of ROB writes
-system.cpu.timesIdled                          105999                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         4417737                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   573342442                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             573342442                       # Number of Instructions Simulated
-system.cpu.cpi                               1.055277                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.055277                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.947618                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.947618                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3393544591                       # number of integer regfile reads
-system.cpu.int_regfile_writes               828738212                       # number of integer regfile writes
+system.cpu.rob.rob_reads                   1501751131                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2028662566                       # The number of ROB writes
+system.cpu.timesIdled                          111416                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         4495314                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   573342447                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             573342447                       # Number of Instructions Simulated
+system.cpu.cpi                               1.039775                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.039775                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.961747                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.961747                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3357392406                       # number of integer regfile reads
+system.cpu.int_regfile_writes               822350092                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.misc_regfile_reads              1294615924                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                4464344                       # number of misc regfile writes
-system.cpu.icache.replacements                  14868                       # number of replacements
-system.cpu.icache.tagsinuse               1047.725210                       # Cycle average of tags in use
-system.cpu.icache.total_refs                151911457                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  16514                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                9198.949800                       # Average number of references to valid blocks.
+system.cpu.misc_regfile_reads              1272268831                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                4464346                       # number of misc regfile writes
+system.cpu.icache.replacements                  14584                       # number of replacements
+system.cpu.icache.tagsinuse               1057.611572                       # Cycle average of tags in use
+system.cpu.icache.total_refs                149431777                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  16238                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                9202.597426                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1047.725210                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.511585                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              151911844                       # number of ReadReq hits
-system.cpu.icache.demand_hits               151911844                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              151911844                       # number of overall hits
-system.cpu.icache.ReadReq_misses                19994                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 19994                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                19994                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      277167000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       277167000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      277167000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          151931838                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           151931838                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          151931838                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000132                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000132                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000132                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 13862.508753                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 13862.508753                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 13862.508753                       # average overall miss latency
+system.cpu.icache.occ_blocks::0           1057.611572                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.516412                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              149431999                       # number of ReadReq hits
+system.cpu.icache.demand_hits               149431999                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              149431999                       # number of overall hits
+system.cpu.icache.ReadReq_misses                19579                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 19579                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                19579                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      272035000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       272035000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      272035000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          149451578                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           149451578                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          149451578                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000131                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000131                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000131                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 13894.223403                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 13894.223403                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 13894.223403                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -352,146 +352,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                       29                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              1670                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               1670                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              1670                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           18324                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            18324                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           18324                       # number of overall MSHR misses
+system.cpu.icache.writebacks                       26                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits              1649                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               1649                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              1649                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           17930                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            17930                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           17930                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    184845500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    184845500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    184845500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    181899000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    181899000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    181899000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000121                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000121                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000121                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 10087.617332                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 10087.617332                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 10087.617332                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000120                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000120                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000120                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 10144.952593                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 10144.952593                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 10144.952593                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1208536                       # number of replacements
-system.cpu.dcache.tagsinuse               4059.803539                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                207709608                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1212632                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 171.288246                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             5997963000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4059.803539                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.991163                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              150052810                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              52876507                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits          2544785                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits           2232171                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits               202929317                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              202929317                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              1147618                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1362799                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses             51                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses               2510417                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2510417                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    12147896500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   20751705500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency       582000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency     32899602000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    32899602000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          151200428                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                1208610                       # number of replacements
+system.cpu.dcache.tagsinuse               4059.103651                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                205025542                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1212706                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 169.064507                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             6026143000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4059.103651                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.990992                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              147450901                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              52819924                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits          2519475                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits           2232172                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               200270825                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              200270825                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              1161160                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1419382                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses             55                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses               2580542                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2580542                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    12492305000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   23242142500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency       536000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency     35734447500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    35734447500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          148612061                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses          54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses      2544836                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses       2232171                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           205439734                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          205439734                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.007590                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.025126                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.000020                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.012220                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.012220                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 10585.313667                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 15227.267924                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 11411.764706                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 13105.233911                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 13105.233911                       # average overall miss latency
+system.cpu.dcache.LoadLockedReq_accesses      2519530                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses       2232172                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           202851367                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          202851367                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.007813                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.026169                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.000022                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.012721                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.012721                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 10758.469978                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 16374.832498                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency  9745.454545                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 13847.651966                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 13847.651966                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        98500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       438000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              20                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              58                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets         4925                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets  7551.724138                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1079332                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            271534                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1024501                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits           51                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1296035                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1296035                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          876084                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         338298                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1214382                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1214382                       # number of overall MSHR misses
+system.cpu.dcache.writebacks                  1078008                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            287250                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1078933                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits           55                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1366183                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1366183                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          873910                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         340449                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          1214359                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1214359                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   6267336500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   4269582000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  10536918500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  10536918500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   6242148500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   4342773500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  10584922000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  10584922000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.005794                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.006237                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.005911                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.005911                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7153.807740                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12620.772219                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  8676.774277                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  8676.774277                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.005880                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006277                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.005986                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.005986                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7142.781865                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12756.017788                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  8716.468524                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  8716.468524                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                217502                       # number of replacements
-system.cpu.l2cache.tagsinuse             21268.774974                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1567233                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                237739                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  6.592242                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                218841                       # number of replacements
+system.cpu.l2cache.tagsinuse             21122.736231                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1563440                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                239107                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  6.538663                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          7619.579259                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         13649.195715                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.232531                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.416540                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                761070                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             1079361                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits               1189                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits              231140                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 992210                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                992210                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses              130897                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses              521                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses            105763                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               236660                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              236660                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    4476495000                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency      5061500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   3624223500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     8100718500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    8100718500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            891967                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         1079361                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses           1710                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          336903                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            1228870                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           1228870                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.146751                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate      0.304678                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.313927                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.192583                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.192583                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34198.606538                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency  9714.971209                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34267.404480                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34229.352235                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34229.352235                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::0          7625.121037                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         13497.615194                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.232700                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.411915                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                759429                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             1078034                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits               1135                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits              231317                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 990746                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                990746                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses              130133                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses              466                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses            107854                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               237987                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              237987                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    4450629000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency      3872500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   3694232000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     8144861000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    8144861000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            889562                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         1078034                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses           1601                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          339171                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            1228733                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           1228733                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.146289                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate      0.291068                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.317993                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.193685                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.193685                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34200.617829                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency  8310.085837                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34252.155692                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34223.974419                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34223.974419                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -500,32 +500,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                  170191                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits               22                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits                22                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits               22                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses         130875                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses          521                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       105763                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          236638                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         236638                       # number of overall MSHR misses
+system.cpu.l2cache.writebacks                  171107                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               21                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                21                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits               21                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses         130112                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses          466                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       107854                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          237966                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         237966                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   4061689500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency     16157000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   3279601500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   7341291000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   7341291000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency   4038190500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency     14451000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   3344342000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   7382532500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   7382532500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.146726                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.304678                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.313927                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.192566                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.192566                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.876791                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31011.516315                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.968165                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31023.297188                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31023.297188                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.146265                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.291068                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.317993                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.193668                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.193668                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31036.264910                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31010.729614                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.047917                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31023.476043                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31023.476043                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 8d64d1d962892258cca5a3074478432fc6ab9b27..6e985035adb9bd7b5d2a2573cab0bf38c2f82f6e 100644 (file)
@@ -499,9 +499,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/arm/scratch/sysexplr/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
index ccc89b5e3a46d185d0d303dfa954cdd24fb2d24b..5c3a273850f9f3adfa831bfadaa4e68413732dcd 100755 (executable)
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 13 2011 13:43:39
-gem5 started Aug 13 2011 13:43:42
-gem5 executing on burrito
+gem5 compiled Aug 15 2011 22:29:28
+gem5 started Aug 16 2011 00:29:05
+gem5 executing on nadc-0270
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -22,8 +24,6 @@ Processing sentences in batch mode
 Echoing of input sentence turned on.
 * as had expected the party to be a success , it was a success 
 info: Increasing stack size by one page.
-* do you know where John 's 
-* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor 
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
@@ -33,6 +33,8 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
+* do you know where John 's 
+* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor 
 * how fast the program is it 
 * I am wondering whether to invite to the party 
 * I gave him for his birthday it 
@@ -77,4 +79,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 589090583500 because target called exit()
+Exiting @ tick 580165782500 because target called exit()
index 8492a348f594882329aa468065617f50a88ac78c..c22ac27cad5166f0bdb7b5155afd5aac323abd7c 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.589091                       # Number of seconds simulated
-sim_ticks                                589090583500                       # Number of ticks simulated
+sim_seconds                                  0.580166                       # Number of seconds simulated
+sim_ticks                                580165782500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 136442                       # Simulator instruction rate (inst/s)
-host_tick_rate                               52568598                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 283504                       # Number of bytes of host memory used
-host_seconds                                 11206.13                       # Real time elapsed on the host
+host_inst_rate                                 108097                       # Simulator instruction rate (inst/s)
+host_tick_rate                               41016714                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308780                       # Number of bytes of host memory used
+host_seconds                                 14144.62                       # Real time elapsed on the host
 sim_insts                                  1528988756                       # Number of instructions simulated
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                       1178181168                       # number of cpu cycles simulated
+system.cpu.numCycles                       1160331566                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                273757612                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          273757612                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           16675490                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             263549330                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                242783379                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                262877499                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          262877499                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           16588311                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             253230639                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                234035375                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          225396448                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1479442200                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   273757612                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          242783379                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     481291859                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               151896780                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              310377154                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                81634                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        545852                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 210829668                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               3979752                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1150024679                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.401504                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.263971                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          220532012                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1432148870                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   262877499                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          234035375                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     466979630                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               149872263                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              313083903                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                89624                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        603590                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 207528533                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               4127463                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1131667315                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.364134                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.250724                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                673316754     58.55%     58.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 35917007      3.12%     61.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 42114185      3.66%     65.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 37411518      3.25%     68.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 23065397      2.01%     70.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 42495755      3.70%     74.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 50561785      4.40%     78.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 39840694      3.46%     82.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                205301584     17.85%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                669263525     59.14%     59.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 35214145      3.11%     62.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 41599455      3.68%     65.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 35436065      3.13%     69.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 23022634      2.03%     71.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 38989025      3.45%     74.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 50553577      4.47%     79.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 40375996      3.57%     82.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                197212893     17.43%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1150024679                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.232356                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.255700                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                295420539                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             258244810                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 403447597                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              60580001                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              132331732                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2687300789                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                    91                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              132331732                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                338940322                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                65400747                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          26711                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 418290382                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             195034785                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2631340918                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 26774                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               78955686                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents             100051710                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2450677467                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            6173942417                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       6173687801                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            254616                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1131667315                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.226554                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.234258                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                289661842                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             260659329                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 390102547                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              60865041                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              130378556                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2610869598                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   131                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              130378556                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                331750332                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                66732317                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          25404                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 406405842                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             196374864                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2558356966                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1635                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               80854908                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              99867012                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2379295437                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            6012229860                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       6011997427                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            232433                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1427299027                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps               1023378440                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               2752                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           2741                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 414898803                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            629493799                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           242177236                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         419306166                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        160446988                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2509527841                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               14260                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1981485394                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1148163                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       978984116                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1684574126                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          13707                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1150024679                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.722994                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.682548                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                951996410                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               2701                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           2688                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 416107098                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            617601057                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           240936819                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         418943952                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        163130234                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2450301589                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               13994                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1951160680                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1081088                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       913572800                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1588612926                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          13441                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1131667315                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.724147                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.660846                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           371543333     32.31%     32.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           234819653     20.42%     52.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           195395907     16.99%     69.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           160294263     13.94%     83.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           104067890      9.05%     92.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            52467268      4.56%     97.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            24318530      2.11%     99.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             6470622      0.56%     99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              647213      0.06%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           351347143     31.05%     31.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           244487319     21.60%     52.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           199318668     17.61%     70.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           156486661     13.83%     84.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            98199546      8.68%     92.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            52384868      4.63%     97.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            22871565      2.02%     99.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             5948232      0.53%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              623313      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1150024679                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1131667315                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1998808     14.58%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     14.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9206664     67.16%     81.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2503442     18.26%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2122690     14.73%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     14.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9149835     63.49%     78.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3139597     21.78%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2582418      0.13%      0.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1339368323     67.59%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            465740044     23.50%     91.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           173794609      8.77%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2537569      0.13%      0.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1320662421     67.69%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            454692889     23.30%     91.12% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           173267801      8.88%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1981485394                       # Type of FU issued
-system.cpu.iq.rate                           1.681817                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    13708914                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006919                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5127850850                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3491267144                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1932205417                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                1694                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              91886                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           39                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1992611139                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     751                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        130415085                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1951160680                       # Type of FU issued
+system.cpu.iq.rate                           1.681554                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    14412122                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.007386                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5049479785                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3366653123                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1905319344                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                2100                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              80588                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           69                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1963034295                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     938                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        129567465                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    245391639                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        85410                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation      2844591                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     93021151                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    233498897                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        89238                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation      2852385                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     91779636                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         2158                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads         2147                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              132331732                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                11601829                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               3101086                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2509542101                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            554188                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             629493799                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            242181336                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              14260                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                2636650                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 28899                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents        2844591                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       15755168                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      2389146                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             18144314                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1946393881                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             456999577                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          35091513                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles              130378556                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                11646448                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               3156259                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2450315583                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            538775                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             617601057                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            240939821                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              13994                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                2673819                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 46064                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents        2852385                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       15716124                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      2393307                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             18109431                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1917986142                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             447373751                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          33174538                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    625221823                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                178037998                       # Number of branches executed
-system.cpu.iew.exec_stores                  168222246                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.652033                       # Inst execution rate
-system.cpu.iew.wb_sent                     1940172676                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1932205456                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1494674926                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2239381826                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    614898275                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                178446647                       # Number of branches executed
+system.cpu.iew.exec_stores                  167524524                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.652964                       # Inst execution rate
+system.cpu.iew.wb_sent                     1912144867                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1905319413                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1473027655                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2208639649                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.639990                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.667450                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.642047                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.666939                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts     1528988756                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       980561731                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       921335872                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             553                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          16735567                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1017692947                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.502407                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.032730                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          16656646                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1001288759                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.527021                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.051909                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    426815196     41.94%     41.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    262847392     25.83%     67.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    100615569      9.89%     77.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     98071512      9.64%     87.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     37557703      3.69%     90.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     27347685      2.69%     93.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     11159718      1.10%     94.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      9457231      0.93%     95.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     43820941      4.31%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    413463578     41.29%     41.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    260152979     25.98%     67.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    102260608     10.21%     77.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     96065702      9.59%     87.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     36102182      3.61%     90.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     27003750      2.70%     93.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     11563952      1.15%     94.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     10101799      1.01%     95.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     44574209      4.45%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1017692947                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1001288759                       # Number of insts commited each cycle
 system.cpu.commit.count                    1528988756                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      533262345                       # Number of memory references committed
@@ -256,48 +256,48 @@ system.cpu.commit.branches                  149758588                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1528317614                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              43820941                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              44574209                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3483422493                       # The number of ROB reads
-system.cpu.rob.rob_writes                  5151578570                       # The number of ROB writes
-system.cpu.timesIdled                          664774                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        28156489                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3407039178                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5031819998                       # The number of ROB writes
+system.cpu.timesIdled                          660069                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        28664251                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1528988756                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1528988756                       # Number of Instructions Simulated
-system.cpu.cpi                               0.770562                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.770562                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.297754                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.297754                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3172016244                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1803001789                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        39                       # number of floating regfile reads
-system.cpu.misc_regfile_reads              1059991053                       # number of misc regfile reads
-system.cpu.icache.replacements                  11761                       # number of replacements
-system.cpu.icache.tagsinuse                991.921323                       # Cycle average of tags in use
-system.cpu.icache.total_refs                210553801                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  13257                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               15882.462171                       # Average number of references to valid blocks.
+system.cpu.cpi                               0.758888                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.758888                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.317717                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.317717                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3149568374                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1776891813                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        69                       # number of floating regfile reads
+system.cpu.misc_regfile_reads              1042858654                       # number of misc regfile reads
+system.cpu.icache.replacements                  11377                       # number of replacements
+system.cpu.icache.tagsinuse                999.208417                       # Cycle average of tags in use
+system.cpu.icache.total_refs                207257376                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  12873                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               16100.161268                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            991.921323                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.484337                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              210560938                       # number of ReadReq hits
-system.cpu.icache.demand_hits               210560938                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              210560938                       # number of overall hits
-system.cpu.icache.ReadReq_misses               268730                       # number of ReadReq misses
-system.cpu.icache.demand_misses                268730                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses               268730                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency     1804649500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency      1804649500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency     1804649500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          210829668                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           210829668                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          210829668                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.001275                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.001275                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.001275                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency  6715.474640                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency  6715.474640                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency  6715.474640                       # average overall miss latency
+system.cpu.icache.occ_blocks::0            999.208417                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.487895                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              207264369                       # number of ReadReq hits
+system.cpu.icache.demand_hits               207264369                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              207264369                       # number of overall hits
+system.cpu.icache.ReadReq_misses               264164                       # number of ReadReq misses
+system.cpu.icache.demand_misses                264164                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses               264164                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency     1771685500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency      1771685500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency     1771685500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          207528533                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           207528533                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          207528533                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.001273                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.001273                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.001273                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency  6706.763601                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency  6706.763601                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency  6706.763601                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -307,59 +307,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                       10                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              1466                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               1466                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              1466                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses          267264                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses           267264                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses          267264                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits              1449                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               1449                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              1449                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses          262715                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses           262715                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses          262715                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    965194500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    965194500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    965194500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    946409000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    946409000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    946409000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.001268                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.001268                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.001268                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  3611.389862                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  3611.389862                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  3611.389862                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.001266                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.001266                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.001266                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  3602.417068                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  3602.417068                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  3602.417068                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2529381                       # number of replacements
-system.cpu.dcache.tagsinuse               4088.837992                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                471314474                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2533477                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 186.034637                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             2156497000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4088.837992                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.998251                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              322454991                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             147504904                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               469959895                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              469959895                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              3024194                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1655297                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               4679491                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              4679491                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    48897826500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   39778871500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     88676698000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    88676698000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          325479185                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                2529282                       # number of replacements
+system.cpu.dcache.tagsinuse               4088.724472                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                462560130                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2533378                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 182.586306                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             2171355000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4088.724472                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.998224                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              313694284                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             147510138                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               461204422                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              461204422                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              3013642                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1650063                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               4663705                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              4663705                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    49018707500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   39546398000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     88565105500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    88565105500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          316707926                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses         149160201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           474639386                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          474639386                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.009292                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.011097                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.009859                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.009859                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 16168.878881                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 24031.259345                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 18950.073416                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 18950.073416                       # average overall miss latency
+system.cpu.dcache.demand_accesses           465868127                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          465868127                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.009516                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.011062                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.010011                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.010011                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 16265.604043                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 23966.598851                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 18990.288944                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 18990.288944                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -368,75 +368,75 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  2230882                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits           1262438                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           636311                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1898749                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1898749                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1761756                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses        1018986                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          2780742                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         2780742                       # number of overall MSHR misses
+system.cpu.dcache.writebacks                  2230730                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits           1251973                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           635644                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1887617                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1887617                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1761669                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses        1014419                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          2776088                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         2776088                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  14863304500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency  18590639000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  33453943500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  33453943500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  14862715000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  18460103000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  33322818000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  33322818000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.005413                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.006831                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.005859                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.005859                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8436.641907                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18244.253601                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 12030.581586                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 12030.581586                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.005562                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006801                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.005959                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.005959                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8436.723925                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18197.710216                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 12003.516459                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 12003.516459                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                576290                       # number of replacements
-system.cpu.l2cache.tagsinuse             21486.143740                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3192786                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                595434                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  5.362116                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          312361625000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          7744.013753                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         13742.129987                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.236329                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.419377                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               1431726                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             2230892                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits               1300                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits              527729                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                1959455                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               1959455                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses              339145                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses           252557                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses            247993                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               587138                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              587138                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   11583445500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency     11508500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   8495412000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency    20078857500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency   20078857500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1770871                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         2230892                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses         253857                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          775722                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            2546593                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           2546593                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.191513                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate      0.994879                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.319693                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.230558                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.230558                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34154.846747                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency    45.567931                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34256.660470                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34197.850420                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34197.850420                       # average overall miss latency
+system.cpu.l2cache.replacements                576428                       # number of replacements
+system.cpu.l2cache.tagsinuse             21465.975306                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3191905                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                595566                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.359448                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          303406560000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          7746.429717                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         13719.545589                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.236402                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.418687                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               1431199                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             2230740                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits               1291                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits              527665                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                1958864                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               1958864                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses              339288                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses           248403                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses            247962                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               587250                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              587250                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   11588417000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency     11435000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   8493856500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    20082273500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   20082273500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1770487                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         2230740                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses         249694                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          775627                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            2546114                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           2546114                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.191635                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate      0.994830                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.319692                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.230646                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.230646                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34155.104218                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency    46.034066                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34254.670070                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34197.145168                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34197.145168                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -448,28 +448,28 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.writebacks                  412302                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses         339145                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses       252557                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       247993                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          587138                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         587138                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses         339288                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses       248403                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       247962                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          587250                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         587250                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  10514861000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   7830102000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   7688785500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  18203646500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  18203646500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency  10519285000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency   7701348000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   7687301500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  18206586500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  18206586500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.191513                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.994879                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.319693                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.230558                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.230558                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.027776                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.306184                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31004.042453                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.033975                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.033975                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.191635                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.994830                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.319692                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.230646                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.230646                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31003.999552                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.441987                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.933764                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31003.127288                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31003.127288                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 49472bb38a91875a346d3edaa6c3c07f5868bb9b..c5767db8f6e139fc62acf6c58ddfc8f978d669d2 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:00:53
-gem5 started Jul  8 2011 16:09:26
+gem5 compiled Jul 15 2011 17:43:54
+gem5 started Jul 15 2011 18:05:51
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -11,4 +11,4 @@ info: Increasing stack size by one page.
 Eon, Version 1.1
 info: Increasing stack size by one page.
 OO-style eon Time= 0.083333
-Exiting @ tick 90884909500 because target called exit()
+Exiting @ tick 90508462500 because target called exit()
index 1cdac852378ceed7aaf9a17fcfcbdfeb59f47760..5bb546882ae70e0a3d7e3c5b689584ea601ac595 100644 (file)
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.090885                       # Number of seconds simulated
-sim_ticks                                 90884909500                       # Number of ticks simulated
+sim_seconds                                  0.090508                       # Number of seconds simulated
+sim_ticks                                 90508462500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  96810                       # Simulator instruction rate (inst/s)
-host_tick_rate                               23426991                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 252820                       # Number of bytes of host memory used
-host_seconds                                  3879.50                       # Real time elapsed on the host
+host_inst_rate                                 100669                       # Simulator instruction rate (inst/s)
+host_tick_rate                               24259753                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 252880                       # Number of bytes of host memory used
+host_seconds                                  3730.81                       # Real time elapsed on the host
 sim_insts                                   375574794                       # Number of instructions simulated
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    105630800                       # DTB read hits
-system.cpu.dtb.read_misses                     100510                       # DTB read misses
-system.cpu.dtb.read_acv                         48612                       # DTB read access violations
-system.cpu.dtb.read_accesses                105731310                       # DTB read accesses
-system.cpu.dtb.write_hits                    79936147                       # DTB write hits
-system.cpu.dtb.write_misses                      1547                       # DTB write misses
+system.cpu.dtb.read_hits                    105325909                       # DTB read hits
+system.cpu.dtb.read_misses                      93344                       # DTB read misses
+system.cpu.dtb.read_acv                         48634                       # DTB read access violations
+system.cpu.dtb.read_accesses                105419253                       # DTB read accesses
+system.cpu.dtb.write_hits                    79718162                       # DTB write hits
+system.cpu.dtb.write_misses                      1558                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                79937694                       # DTB write accesses
-system.cpu.dtb.data_hits                    185566947                       # DTB hits
-system.cpu.dtb.data_misses                     102057                       # DTB misses
-system.cpu.dtb.data_acv                         48612                       # DTB access violations
-system.cpu.dtb.data_accesses                185669004                       # DTB accesses
-system.cpu.itb.fetch_hits                    58326026                       # ITB hits
-system.cpu.itb.fetch_misses                       337                       # ITB misses
+system.cpu.dtb.write_accesses                79719720                       # DTB write accesses
+system.cpu.dtb.data_hits                    185044071                       # DTB hits
+system.cpu.dtb.data_misses                      94902                       # DTB misses
+system.cpu.dtb.data_acv                         48634                       # DTB access violations
+system.cpu.dtb.data_accesses                185138973                       # DTB accesses
+system.cpu.itb.fetch_hits                    58032693                       # ITB hits
+system.cpu.itb.fetch_misses                       351                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                58326363                       # ITB accesses
+system.cpu.itb.fetch_accesses                58033044                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -41,246 +41,246 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        181769821                       # number of cpu cycles simulated
+system.cpu.numCycles                        181016927                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 57225452                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           33446848                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            3610875                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              40879451                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 32187006                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 56908652                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           33128839                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            3549307                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              40569971                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 32137344                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                 10725194                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                1200                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           60337386                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      506200677                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    57225452                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           42912200                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      94142068                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                13173843                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               17624322                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  179                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          7572                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  58326026                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1118192                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          181648006                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.786712                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.242035                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                 10736279                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                1343                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           59988242                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      503999677                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    56908652                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           42873623                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      93805949                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                12846494                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               17811682                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  180                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          7687                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  58032693                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1098562                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          180895317                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.786140                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.241759                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 87505938     48.17%     48.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  8084169      4.45%     52.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  9812284      5.40%     58.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  6556715      3.61%     61.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 13799395      7.60%     69.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  9400037      5.17%     74.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5907170      3.25%     77.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3477374      1.91%     79.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 37104924     20.43%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 87089368     48.14%     48.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  8126413      4.49%     52.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  9953250      5.50%     58.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  6311167      3.49%     61.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 13618559      7.53%     69.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  9505792      5.25%     74.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5896466      3.26%     77.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3503145      1.94%     79.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 36891157     20.39%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            181648006                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.314824                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.784844                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 66587043                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              13622871                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  88021771                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3884112                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9532209                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             10337474                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  4322                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              494122650                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 12073                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                9532209                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 71008708                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4690007                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         394366                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  87374252                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               8648464                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              480990212                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     5                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  42769                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               7153610                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           312500874                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             630714726                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        332574792                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         298139934                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            180895317                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.314383                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.784268                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 66262768                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              13721794                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  87804231                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3829220                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9277304                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             10346731                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  4343                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              492360513                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 11994                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                9277304                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 70771279                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4688791                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         402464                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  87101855                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               8653624                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              479416177                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     6                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  50185                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               7149377                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           311562327                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             628686073                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        332583088                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         296102985                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259532319                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 52968555                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              38325                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            292                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  23912108                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            111095455                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            85873017                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          14526105                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          8463039                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  435543273                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 257                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 420425800                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1773859                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        58536245                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     32877731                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             42                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     181648006                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.314508                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.994579                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 52030008                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              38365                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            280                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  23740235                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            110658167                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            85526614                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          15465988                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         10430696                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  434355597                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 252                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 419519707                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1756806                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        57360180                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     32293778                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             37                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     180895317                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.319130                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.993104                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            45216412     24.89%     24.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            30232996     16.64%     41.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            28617209     15.75%     57.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            25676408     14.14%     71.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            23156698     12.75%     84.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            15699012      8.64%     92.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             7807681      4.30%     97.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3971496      2.19%     99.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1270094      0.70%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            44820498     24.78%     24.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            29979430     16.57%     41.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            28846817     15.95%     57.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            25627519     14.17%     71.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            22480714     12.43%     83.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            15907163      8.79%     92.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             8306052      4.59%     97.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3747889      2.07%     99.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1179235      0.65%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       181648006                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       180895317                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  135221      1.15%      1.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      1.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                 39442      0.34%      1.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                  7017      0.06%      1.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                 13904      0.12%      1.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult              2001949     17.09%     18.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                880826      7.52%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     26.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5776712     49.33%     75.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2855706     24.39%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   69354      0.60%      0.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      0.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                 38404      0.33%      0.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                  5709      0.05%      0.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                 19332      0.17%      1.15% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult              2037444     17.66%     18.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                875919      7.59%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     26.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5719458     49.56%     75.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2774394     24.04%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             33581      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             164795138     39.20%     39.21% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2124451      0.51%     39.71% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     39.71% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            34088388      8.11%     47.82% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             8064196      1.92%     49.74% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             3086941      0.73%     50.47% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult           16853454      4.01%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv             1579988      0.38%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            108302425     25.76%     80.62% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            81497238     19.38%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             164900286     39.31%     39.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2243051      0.53%     39.85% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     39.85% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            33844550      8.07%     47.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             7897710      1.88%     49.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2993735      0.71%     50.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult           16825521      4.01%     54.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv             1580906      0.38%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.90% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            107841565     25.71%     80.61% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            81358802     19.39%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              420425800                       # Type of FU issued
-system.cpu.iq.rate                           2.312957                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    11710777                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.027855                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          685991050                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         291244200                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    242469849                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           349993192                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          202862270                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    165589366                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              253586541                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               178516455                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         13913922                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              419519707                       # Type of FU issued
+system.cpu.iq.rate                           2.317572                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    11540014                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.027508                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          685462958                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         291219348                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    242560611                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           347768593                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          200512633                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    164917620                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              253759021                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               177267119                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         14283738                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     16340969                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       171857                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        26790                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     12352289                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     15903681                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       169313                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        15968                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     12005886                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       176199                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked             2                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       213972                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             3                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9532209                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 2220194                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                306578                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           461167180                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           2274758                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             111095455                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             85873017                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                257                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    130                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                9277304                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2317535                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                350843                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           460018539                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           2425230                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             110658167                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             85526614                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                252                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    132                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                    14                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          26790                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3503569                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       569738                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              4073307                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             411738121                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             105779948                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           8687679                       # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents          15968                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3438704                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       545017                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              3983721                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             411016170                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             105467950                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           8503537                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      25623650                       # number of nop insts executed
-system.cpu.iew.exec_refs                    185717662                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 48391334                       # Number of branches executed
-system.cpu.iew.exec_stores                   79937714                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.265162                       # Inst execution rate
-system.cpu.iew.wb_sent                      409282340                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     408059215                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 198971045                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 279819296                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      25662690                       # number of nop insts executed
+system.cpu.iew.exec_refs                    185187689                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 48286737                       # Number of branches executed
+system.cpu.iew.exec_stores                   79719739                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.270595                       # Inst execution rate
+system.cpu.iew.wb_sent                      408658291                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     407478231                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 198809248                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 280006771                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.244923                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.711070                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.251050                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.710016                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      398664569                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        62502516                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        61360500                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           3606605                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    172115797                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.316258                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.838436                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           3545034                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    171618013                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.322976                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.832511                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     71294232     41.42%     41.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     26334848     15.30%     56.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15061233      8.75%     65.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     13435550      7.81%     73.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8560921      4.97%     78.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      6120977      3.56%     81.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      5034670      2.93%     84.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3342912      1.94%     86.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     22930454     13.32%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     70646303     41.16%     41.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     26006834     15.15%     56.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15503557      9.03%     65.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     13282401      7.74%     73.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      8794833      5.12%     78.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      6427011      3.74%     81.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      5152706      3.00%     84.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2862149      1.67%     86.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     22942219     13.37%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    172115797                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    171618013                       # Number of insts commited each cycle
 system.cpu.commit.count                     398664569                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      168275214                       # Number of memory references committed
@@ -290,50 +290,50 @@ system.cpu.commit.branches                   44587530                       # Nu
 system.cpu.commit.fp_insts                  155295106                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 316365825                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              8007752                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              22930454                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              22942219                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    610349451                       # The number of ROB reads
-system.cpu.rob.rob_writes                   931879411                       # The number of ROB writes
-system.cpu.timesIdled                            2704                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          121815                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    608697886                       # The number of ROB reads
+system.cpu.rob.rob_writes                   929339596                       # The number of ROB writes
+system.cpu.timesIdled                            2701                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          121610                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   375574794                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             375574794                       # Number of Instructions Simulated
-system.cpu.cpi                               0.483978                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.483978                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               2.066211                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         2.066211                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                410939724                       # number of integer regfile reads
-system.cpu.int_regfile_writes               176360806                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 160541736                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                106688075                       # number of floating regfile writes
+system.cpu.cpi                               0.481973                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.481973                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.074805                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.074805                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                410790761                       # number of integer regfile reads
+system.cpu.int_regfile_writes               176550359                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 159677516                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                106247961                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                  350572                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.icache.replacements                   2140                       # number of replacements
-system.cpu.icache.tagsinuse               1834.625402                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 58320710                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   4067                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               14339.982788                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                   2105                       # number of replacements
+system.cpu.icache.tagsinuse               1832.667923                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 58027410                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   4031                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               14395.289010                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1834.625402                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.895813                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               58320710                       # number of ReadReq hits
-system.cpu.icache.demand_hits                58320710                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               58320710                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 5316                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  5316                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 5316                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      168223000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       168223000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      168223000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           58326026                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            58326026                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           58326026                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0           1832.667923                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.894857                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               58027410                       # number of ReadReq hits
+system.cpu.icache.demand_hits                58027410                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               58027410                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 5283                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  5283                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 5283                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      167989000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       167989000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      167989000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           58032693                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            58032693                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           58032693                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000091                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate           0.000091                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate          0.000091                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 31644.657637                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 31644.657637                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 31644.657637                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 31798.031422                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 31798.031422                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 31798.031422                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -343,132 +343,132 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              1249                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               1249                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              1249                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            4067                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             4067                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            4067                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits              1252                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               1252                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              1252                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            4031                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             4031                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            4031                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    123582000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    123582000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    123582000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    123392000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    123392000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    123392000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000070                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000070                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000070                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 30386.525695                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 30386.525695                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 30386.525695                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000069                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000069                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000069                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 30610.766559                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 30610.766559                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 30610.766559                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                    788                       # number of replacements
-system.cpu.dcache.tagsinuse               3295.374104                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                165040256                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                   4187                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               39417.304992                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                    787                       # number of replacements
+system.cpu.dcache.tagsinuse               3295.378268                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                164327794                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   4186                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               39256.520306                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           3295.374104                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.804535                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               91538987                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              73501262                       # number of WriteReq hits
+system.cpu.dcache.occ_blocks::0           3295.378268                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.804536                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               90826520                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              73501267                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits                7                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits               165040249                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              165040249                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                 1683                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses               19466                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                 21149                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                21149                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       56075000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency     568706500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency       624781500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      624781500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           91540670                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits               164327787                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              164327787                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                 1669                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses               19461                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                 21130                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                21130                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       56052000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     568707000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency       624759000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      624759000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           90828189                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses          73520728                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses            7                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           165061398                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          165061398                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses           164348917                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          164348917                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate          0.000018                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate         0.000265                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.000128                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000128                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 33318.478907                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 29215.375527                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 29541.893234                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 29541.893234                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         5000                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate           0.000129                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000129                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 33584.182145                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 29222.907353                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 29567.392333                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 29567.392333                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         7500                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs         2500                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks                      662                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits               689                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits            16273                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits              16962                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits             16962                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             994                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits               676                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits            16268                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits              16944                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits             16944                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             993                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses           3193                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             4187                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            4187                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses             4186                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            4186                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     31676000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency    113165000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency    144841000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency    144841000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency     31737500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency    113123500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    144861000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    144861000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000011                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000043                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31867.203219                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35441.590980                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 34593.026033                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 34593.026033                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31961.228600                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35428.593799                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34606.067845                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34606.067845                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                    10                       # number of replacements
-system.cpu.l2cache.tagsinuse              4007.918811                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                     828                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                  4847                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.170827                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                    11                       # number of replacements
+system.cpu.l2cache.tagsinuse              4003.203107                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                     792                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  4846                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.163434                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          3630.264414                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1           377.654397                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.110787                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          3625.567893                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           377.635214                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.110644                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::1            0.011525                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                   755                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits                   719                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits                 662                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits                  62                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                    817                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                   817                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                4306                       # number of ReadReq misses
+system.cpu.l2cache.demand_hits                    781                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                   781                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                4305                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses              3131                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 7437                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                7437                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     148211500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency    108422000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      256633500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     256633500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses              5061                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.demand_misses                 7436                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                7436                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     148172000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency    108394500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      256566500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     256566500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              5024                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses             662                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses            3193                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses               8254                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses              8254                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.850820                       # miss rate for ReadReq accesses
+system.cpu.l2cache.demand_accesses               8217                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              8217                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.856887                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate       0.980583                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.901018                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.901018                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34419.763121                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34628.553178                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34507.664381                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34507.664381                       # average overall miss latency
+system.cpu.l2cache.demand_miss_rate          0.904953                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.904953                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34418.583043                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34619.770042                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34503.294782                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34503.294782                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -480,24 +480,24 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           4306                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses           4305                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses         3131                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            7437                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           7437                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses            7436                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           7436                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    134349000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     98553500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    232902500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    232902500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency    134317500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     98537000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    232854500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    232854500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.850820                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.856887                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.980583                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.901018                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.901018                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31200.418021                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31476.684765                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31316.727175                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31316.727175                       # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate     0.904953                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.904953                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31200.348432                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31471.414883                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31314.483593                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31314.483593                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index fb668f921b893ac224bddde51b6c09d55c69b406..93d8a89077f7ae5b7b1b5cd0106267c809a95b4f 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:18:43
-gem5 started Jul  9 2011 02:03:43
+gem5 compiled Jul 15 2011 18:02:03
+gem5 started Jul 16 2011 01:50:03
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -13,4 +13,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 OO-style eon Time= 0.100000
-Exiting @ tick 108112565000 because target called exit()
+Exiting @ tick 107583551000 because target called exit()
index 467f5453a5ee60c105b88ae015207e54c25125ec..460dc03fb4903cb138a74deb2511ec9573ac4ee6 100644 (file)
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.108113                       # Number of seconds simulated
-sim_ticks                                108112565000                       # Number of ticks simulated
+sim_seconds                                  0.107584                       # Number of seconds simulated
+sim_ticks                                107583551000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  68175                       # Simulator instruction rate (inst/s)
-host_tick_rate                               21114970                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 266872                       # Number of bytes of host memory used
-host_seconds                                  5120.19                       # Real time elapsed on the host
-sim_insts                                   349066124                       # Number of instructions simulated
+host_inst_rate                                  75407                       # Simulator instruction rate (inst/s)
+host_tick_rate                               23240692                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 266760                       # Number of bytes of host memory used
+host_seconds                                  4629.10                       # Real time elapsed on the host
+sim_insts                                   349066079                       # Number of instructions simulated
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -51,106 +51,105 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        216225131                       # number of cpu cycles simulated
+system.cpu.numCycles                        215167103                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 38871530                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           21265030                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            3261176                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              27909151                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 21653043                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 38866864                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           21264408                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            3266019                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              27927226                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 21684401                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  7689864                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               61658                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           44557213                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      344579360                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    38871530                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           29342907                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      80636459                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                11681756                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               82619379                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   15                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.BPredUnit.usedRAS                  7691210                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               61222                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           44512335                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      344276425                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    38866864                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           29375611                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      80511733                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                11473489                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               81944021                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   14                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           192                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  42088076                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                916191                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          216112788                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.095569                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.185948                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  42084770                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                964630                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          215054786                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.101541                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.187737                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                136175266     63.01%     63.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  9565429      4.43%     67.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  6238703      2.89%     70.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  6748883      3.12%     73.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  5364932      2.48%     75.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4989535      2.31%     78.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  3875216      1.79%     80.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  4307528      1.99%     82.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 38847296     17.98%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                135247820     62.89%     62.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  9581431      4.46%     67.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  6200382      2.88%     70.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  6701216      3.12%     73.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  5378029      2.50%     75.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5062390      2.35%     78.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3862872      1.80%     80.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4305787      2.00%     82.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 38714859     18.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            216112788                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.179773                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.593614                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 53033788                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              77116773                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  73749422                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3985890                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                8226915                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              7647714                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 72935                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              439814331                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                207402                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                8226915                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 61196526                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 1203573                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       59638529                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  69748798                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              16098447                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              424223689                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     3                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  22825                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               9278494                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents               99                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           462213475                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2492907388                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1378161419                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups        1114745969                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             384568743                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 77644727                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            3986897                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        4043470                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  51924156                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            109846529                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            95332472                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          14399866                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         29809960                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  399729408                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             3865767                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 378419662                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1473555                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        54144389                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    177169340                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         310299                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     216112788                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.751029                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.895618                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            215054786                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.180636                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.600042                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 53002613                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              76469979                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  73518908                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               4049306                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                8013980                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              7649180                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 72848                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              438661628                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                207176                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                8013980                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 61218599                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 1131550                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       59029634                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  69546972                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              16114051                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              422574228                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                  21742                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               9279237                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents               90                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           460656766                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2485118171                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1371103048                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups        1114015123                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             384568671                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 76088090                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            3987530                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        4043809                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  51974950                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            109318735                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            94590139                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          14520284                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         31851289                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  397726769                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             3866008                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 377532932                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1512344                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        52097300                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    169247595                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         310549                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     215054786                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.755520                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.897504                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            82036681     37.96%     37.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            39071702     18.08%     56.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            28236809     13.07%     69.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            20423013      9.45%     78.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            23529038     10.89%     89.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            13145418      6.08%     95.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             6683366      3.09%     98.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             2232223      1.03%     99.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              754538      0.35%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            81920022     38.09%     38.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            36703261     17.07%     55.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            30740641     14.29%     69.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            20223146      9.40%     78.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            22465672     10.45%     89.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            12916056      6.01%     95.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             7162460      3.33%     98.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             2127001      0.99%     99.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              796527      0.37%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       216112788                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       215054786                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                    2198      0.02%      0.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                    2050      0.02%      0.02% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                   5043      0.04%      0.06% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.06% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.06% # attempts to use FU when none available
@@ -170,181 +169,181 @@ system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.06% # at
 system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.06% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.06% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd              9996      0.08%      0.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp              2604      0.02%      0.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt               194      0.00%      0.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 2      0.00%      0.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc           114242      0.95%      1.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult              418      0.00%      1.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc        276715      2.30%      3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                7458735     61.87%     65.28% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4186007     34.72%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd              2503      0.02%      0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp              2378      0.02%      0.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt               190      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 3      0.00%      0.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc            64374      0.52%      0.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult              754      0.01%      0.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc        176929      1.43%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                7674311     61.94%     63.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4460810     36.01%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             130620873     34.52%     34.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2147251      0.57%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                   20      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     35.08% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         6800768      1.80%     36.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         8475274      2.24%     39.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         3501119      0.93%     40.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv         1584837      0.42%     40.47% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       21128819      5.58%     46.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult        7289356      1.93%     47.98% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc      7313976      1.93%     49.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt         175288      0.05%     49.95% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            102741469     27.15%     77.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            86640612     22.90%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             130144108     34.47%     34.47% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2147204      0.57%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                   13      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     35.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         6800428      1.80%     36.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.84% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         8468997      2.24%     39.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         3502516      0.93%     40.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv         1584629      0.42%     40.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       21129824      5.60%     46.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult        7288599      1.93%     47.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc      7314719      1.94%     49.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     49.94% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            102477963     27.14%     77.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            86498646     22.91%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              378419662                       # Type of FU issued
-system.cpu.iq.rate                           1.750119                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    12056154                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.031859                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          736575285                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         322046718                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    251010826                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           249906536                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          135772025                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    118653498                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              262435143                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               128040673                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          5198793                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              377532932                       # Type of FU issued
+system.cpu.iq.rate                           1.754603                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    12389345                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.032817                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          734704408                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         318594849                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    250322854                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           249317931                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          135263376                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    118611889                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              262229500                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               127692777                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          5202175                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     15197510                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         2287                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       168315                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     12956623                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     14669725                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         2212                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       168200                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     12214299                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads          309                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads          529                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked           117                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                8226915                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                   19822                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                   465                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           403642432                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           2591477                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             109846529                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             95332472                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            3854525                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                     52                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   191                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         168315                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3199953                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       312751                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              3512704                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             372398400                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             101298405                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           6021262                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                8013980                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                   40240                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                   528                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           401640096                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           2868954                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             109318735                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             94590139                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            3854778                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     56                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   263                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         168200                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3197943                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       311714                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              3509657                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             371554186                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             101007931                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           5978746                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         47257                       # number of nop insts executed
-system.cpu.iew.exec_refs                    186410418                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 32413413                       # Number of branches executed
-system.cpu.iew.exec_stores                   85112013                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.722272                       # Inst execution rate
-system.cpu.iew.wb_sent                      370241650                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     369664324                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 175377527                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 344318453                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         47319                       # number of nop insts executed
+system.cpu.iew.exec_refs                    186146804                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 32387035                       # Number of branches executed
+system.cpu.iew.exec_stores                   85138873                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.726817                       # Inst execution rate
+system.cpu.iew.wb_sent                      369518278                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     368934743                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 175105740                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 344287199                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.709627                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.509347                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.714643                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.508604                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      349066736                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        54571176                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         3555468                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           3230397                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    207885874                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.679127                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.249386                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts      349066691                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        52570633                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         3555459                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           3235349                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    207040807                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.685980                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.257361                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     88802662     42.72%     42.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     47260336     22.73%     65.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     19727320      9.49%     74.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     15331284      7.37%     82.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     11254360      5.41%     87.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      7570851      3.64%     91.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      3388756      1.63%     93.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3248763      1.56%     94.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11301542      5.44%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     88545688     42.77%     42.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     46881849     22.64%     65.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     18621860      8.99%     74.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     16226218      7.84%     82.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     12168634      5.88%     88.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      6395519      3.09%     91.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3322513      1.60%     92.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3352949      1.62%     94.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     11525577      5.57%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    207885874                       # Number of insts commited each cycle
-system.cpu.commit.count                     349066736                       # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total    207040807                       # Number of insts commited each cycle
+system.cpu.commit.count                     349066691                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      177024867                       # Number of memory references committed
-system.cpu.commit.loads                      94649018                       # Number of loads committed
+system.cpu.commit.refs                      177024849                       # Number of memory references committed
+system.cpu.commit.loads                      94649009                       # Number of loads committed
 system.cpu.commit.membars                       11033                       # Number of memory barriers committed
-system.cpu.commit.branches                   30521897                       # Number of branches committed
+system.cpu.commit.branches                   30521888                       # Number of branches committed
 system.cpu.commit.fp_insts                  114216705                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 279586001                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 279585965                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              6225114                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              11301542                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              11525577                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    600219721                       # The number of ROB reads
-system.cpu.rob.rob_writes                   815506085                       # The number of ROB writes
-system.cpu.timesIdled                            2585                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          112343                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   349066124                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             349066124                       # Number of Instructions Simulated
-system.cpu.cpi                               0.619439                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.619439                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.614364                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.614364                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1775936880                       # number of integer regfile reads
-system.cpu.int_regfile_writes               235580324                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 189945628                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                134544688                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              1009447373                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               34422229                       # number of misc regfile writes
-system.cpu.icache.replacements                  14157                       # number of replacements
-system.cpu.icache.tagsinuse               1842.318723                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 42071371                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  16032                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                2624.212263                       # Average number of references to valid blocks.
+system.cpu.rob.rob_reads                    597150031                       # The number of ROB reads
+system.cpu.rob.rob_writes                   811292092                       # The number of ROB writes
+system.cpu.timesIdled                            2574                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          112317                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   349066079                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             349066079                       # Number of Instructions Simulated
+system.cpu.cpi                               0.616408                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.616408                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.622302                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.622302                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1772094610                       # number of integer regfile reads
+system.cpu.int_regfile_writes               234878865                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 189976866                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                134506188                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              1008752840                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               34422211                       # number of misc regfile writes
+system.cpu.icache.replacements                  14169                       # number of replacements
+system.cpu.icache.tagsinuse               1843.995192                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 42068048                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  16047                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                2621.552190                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1842.318723                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.899570                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               42071371                       # number of ReadReq hits
-system.cpu.icache.demand_hits                42071371                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               42071371                       # number of overall hits
-system.cpu.icache.ReadReq_misses                16705                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 16705                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                16705                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      202344500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       202344500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      202344500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           42088076                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            42088076                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           42088076                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0           1843.995192                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.900388                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               42068048                       # number of ReadReq hits
+system.cpu.icache.demand_hits                42068048                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               42068048                       # number of overall hits
+system.cpu.icache.ReadReq_misses                16722                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 16722                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                16722                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      202514000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       202514000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      202514000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           42084770                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            42084770                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           42084770                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000397                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate           0.000397                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate          0.000397                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 12112.810536                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 12112.810536                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 12112.810536                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 12110.632699                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 12110.632699                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 12110.632699                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -354,142 +353,142 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               669                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                669                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               669                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           16036                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            16036                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           16036                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits               670                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                670                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               670                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           16052                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            16052                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           16052                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    136366000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    136366000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    136366000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    136437000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    136437000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    136437000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000381                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000381                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate     0.000381                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  8503.741581                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  8503.741581                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  8503.741581                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  8499.688512                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  8499.688512                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  8499.688512                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                   1406                       # number of replacements
-system.cpu.dcache.tagsinuse               3100.332801                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                178043182                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                   4595                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               38747.156039                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                   1411                       # number of replacements
+system.cpu.dcache.tagsinuse               3103.063494                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                177743721                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   4602                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               38623.146675                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           3100.332801                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.756917                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               95986293                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              82033252                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits            12491                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits             11132                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits               178019545                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              178019545                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                 3385                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses               19442                       # number of WriteReq misses
+system.cpu.dcache.occ_blocks::0           3103.063494                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.757584                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               95687864                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              82033242                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            11477                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             11123                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               177721106                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              177721106                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                 3405                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses               19452                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses                 22827                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                22827                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency      112128500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency     646930500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses                 22857                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                22857                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency      112607000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     646340500                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency        76000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency       759059000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      759059000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           95989678                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency       758947500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      758947500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           95691269                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses          82052694                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses        12493                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses         11132                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           178042372                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          178042372                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000035                       # miss rate for ReadReq accesses
+system.cpu.dcache.LoadLockedReq_accesses        11479                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         11123                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           177743963                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          177743963                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000036                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate         0.000237                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.000160                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.000128                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000128                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 33125.110783                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33274.894558                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_miss_rate     0.000174                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.000129                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000129                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 33071.071953                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 33227.457331                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency        38000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 33252.683226                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 33252.683226                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency 33204.160651                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 33204.160651                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       308500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       306500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              11                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 28045.454545                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 27863.636364                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                     1025                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits              1630                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits            16598                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks                     1029                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits              1641                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits            16609                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits              18228                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits             18228                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses            1755                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           2844                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             4599                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            4599                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_hits              18250                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits             18250                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses            1764                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           2843                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             4607                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            4607                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     53650500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency    101058500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency    154709000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency    154709000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency     53753000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency    100987000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency    154740000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency    154740000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000018                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000035                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate      0.000026                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate     0.000026                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30570.085470                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35533.931083                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 33639.704284                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 33639.704284                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30472.222222                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35521.280338                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 33588.018233                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 33588.018233                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                    59                       # number of replacements
-system.cpu.l2cache.tagsinuse              3910.187993                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   13367                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                  5367                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  2.490591                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                    61                       # number of replacements
+system.cpu.l2cache.tagsinuse              3912.978440                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   13386                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  5372                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.491809                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          3537.549748                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1           372.638245                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.107957                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.011372                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                 13284                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits                1025                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                  17                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                  13301                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                 13301                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                4501                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses                4                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses              2824                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 7325                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                7325                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     154458500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency     97367500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      251826000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     251826000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses             17785                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses            1025                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses              4                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            2841                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses              20626                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses             20626                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.253078                       # miss rate for ReadReq accesses
+system.cpu.l2cache.occ_blocks::0          3537.285650                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1           375.692790                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.107949                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.011465                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 13302                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                1029                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                  18                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                  13320                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 13320                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                4505                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses                5                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses              2821                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 7326                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                7326                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     154534500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     97281500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      251816000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     251816000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses             17807                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses            1029                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses              5                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            2839                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses              20646                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses             20646                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.252990                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.994016                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.355134                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.355134                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34316.485226                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34478.576487                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34378.976109                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34378.976109                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate       0.993660                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.354839                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.354839                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34302.885683                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34484.757178                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34372.918373                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34372.918373                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -499,31 +498,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits               54                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits                54                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits               54                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           4447                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses            4                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         2824                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_hits               55                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                55                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits               55                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           4450                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses            5                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         2821                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses            7271                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses           7271                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    138555000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency       124000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     88338500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    226893500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    226893500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency    138648500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency       155000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     88253500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    226902000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    226902000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250042                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.249902                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.994016                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.352516                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.352516                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31156.959748                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.993660                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.352175                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.352175                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31156.966292                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31281.338527                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.267501                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.267501                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31284.473591                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.436529                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.436529                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 973e6058bd607e7b8387a26db9c9667af2dbe44b..3c76f760a617d21e129f30b95a15c2991f3cc833 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:00:53
-gem5 started Jul  8 2011 16:14:22
+gem5 compiled Jul 15 2011 17:43:54
+gem5 started Jul 15 2011 18:12:11
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -1385,4 +1385,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 643278327500 because target called exit()
+Exiting @ tick 643295961000 because target called exit()
index 9f87a64abd50d5fce3d6ff1e780f30346c5f7631..75c67bd68bd0a7367234c8d6ff8a6aa7a392f8cd 100644 (file)
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.643278                       # Number of seconds simulated
-sim_ticks                                643278327500                       # Number of ticks simulated
+sim_seconds                                  0.643296                       # Number of seconds simulated
+sim_ticks                                643295961000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  72554                       # Simulator instruction rate (inst/s)
-host_tick_rate                               25601460                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 253232                       # Number of bytes of host memory used
-host_seconds                                 25126.63                       # Real time elapsed on the host
+host_inst_rate                                  85106                       # Simulator instruction rate (inst/s)
+host_tick_rate                               30031356                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253300                       # Number of bytes of host memory used
+host_seconds                                 21420.81                       # Real time elapsed on the host
 sim_insts                                  1823043370                       # Number of instructions simulated
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    519966765                       # DTB read hits
-system.cpu.dtb.read_misses                     661962                       # DTB read misses
+system.cpu.dtb.read_hits                    519970160                       # DTB read hits
+system.cpu.dtb.read_misses                     661937                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                520628727                       # DTB read accesses
-system.cpu.dtb.write_hits                   283803273                       # DTB write hits
-system.cpu.dtb.write_misses                     53019                       # DTB write misses
+system.cpu.dtb.read_accesses                520632097                       # DTB read accesses
+system.cpu.dtb.write_hits                   283803087                       # DTB write hits
+system.cpu.dtb.write_misses                     53073                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               283856292                       # DTB write accesses
-system.cpu.dtb.data_hits                    803770038                       # DTB hits
-system.cpu.dtb.data_misses                     714981                       # DTB misses
+system.cpu.dtb.write_accesses               283856160                       # DTB write accesses
+system.cpu.dtb.data_hits                    803773247                       # DTB hits
+system.cpu.dtb.data_misses                     715010                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                804485019                       # DTB accesses
-system.cpu.itb.fetch_hits                   398172437                       # ITB hits
-system.cpu.itb.fetch_misses                       227                       # ITB misses
+system.cpu.dtb.data_accesses                804488257                       # DTB accesses
+system.cpu.itb.fetch_hits                   398201591                       # ITB hits
+system.cpu.itb.fetch_misses                       218                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               398172664                       # ITB accesses
+system.cpu.itb.fetch_accesses               398201809                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -41,105 +41,105 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   39                       # Number of system calls
-system.cpu.numCycles                       1286556656                       # number of cpu cycles simulated
+system.cpu.numCycles                       1286591923                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                402336394                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          266883320                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           28923526                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             333487818                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                271623617                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                402332344                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          266882286                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           28927707                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             333469369                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                271602812                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                 61006515                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                1123                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          414972341                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     3352664907                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   402336394                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          332630132                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     645381442                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               165705235                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               89720860                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  148                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          4171                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 398172437                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes              11167265                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1286425438                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.606187                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.132190                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                 61007476                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                1110                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          415001255                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3352758055                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   402332344                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          332610288                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     645375042                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               165723588                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               89718349                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  142                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          4131                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 398201591                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes              11171919                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1286459621                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.606190                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.132201                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                641043996     49.83%     49.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 57060222      4.44%     54.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 45200815      3.51%     57.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 74446189      5.79%     63.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                134854552     10.48%     74.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 43347618      3.37%     77.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 44933428      3.49%     80.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  8201322      0.64%     81.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                237337296     18.45%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                641084579     49.83%     49.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 57052665      4.43%     54.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 45174311      3.51%     57.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 74426993      5.79%     63.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                134875527     10.48%     74.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 43375843      3.37%     77.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 44931784      3.49%     80.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  8199590      0.64%     81.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                237338329     18.45%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1286425438                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.312723                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.605921                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                450744873                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              71473924                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 619092915                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               8779214                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              136334512                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             30672233                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12086                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3254497888                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 45897                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              136334512                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                481076883                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                28014325                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          24661                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 596193290                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              44781767                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3152490171                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   251                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 750331                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              37577847                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2105819344                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3700266531                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3588526705                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         111739826                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1286459621                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.312712                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.605922                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                450770421                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              71474392                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 619091022                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               8775043                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              136348743                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             30660300                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 12096                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3254572128                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 45923                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              136348743                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                481111559                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                28021350                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          24247                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 596178127                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              44775595                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3152541087                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   298                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 750385                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              37569615                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2105877603                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3700324633                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3588590949                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         111733684                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1384969070                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                720850274                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               2943                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             84                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 124041279                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            733340932                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           346031420                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          95137569                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         27633179                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2644257175                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  78                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2155824179                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          16126742                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       820828364                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    783816601                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             39                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1286425438                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.675825                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.770169                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                720908533                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               2940                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             82                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 124038053                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            733381291                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           346041020                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          96533451                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         26209909                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2644326551                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  76                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2155830788                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          16155123                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       820898525                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    783895996                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             37                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1286459621                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.675786                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.770072                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           467246309     36.32%     36.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           226022267     17.57%     53.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           245197843     19.06%     72.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           131574377     10.23%     83.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           102243605      7.95%     91.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            70385882      5.47%     96.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            25434522      1.98%     98.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            15392931      1.20%     99.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             2927702      0.23%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           467272561     36.32%     36.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           226031192     17.57%     53.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           245053970     19.05%     72.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           131827206     10.25%     83.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           102136676      7.94%     91.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            70412736      5.47%     96.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            25404830      1.97%     98.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            15392926      1.20%     99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             2927524      0.23%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1286425438                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1286459621                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   16153      0.06%      0.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   17442      0.06%      0.06% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      0.06% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.06% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.06% # attempts to use FU when none available
@@ -168,17 +168,17 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.06% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.06% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.06% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               21369886     75.29%     75.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               6999064     24.66%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               21373822     75.29%     75.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               6999070     24.65%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2752      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1238199555     57.44%     57.44% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                16604      0.00%     57.44% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1238197742     57.43%     57.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                16606      0.00%     57.44% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            27850923      1.29%     58.73% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             8254691      0.38%     59.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             7204648      0.33%     59.44% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            27850913      1.29%     58.73% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             8254688      0.38%     59.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             7204646      0.33%     59.44% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.44% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.44% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.44% # Type of FU issued
@@ -202,85 +202,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.44% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.44% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.44% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            584881936     27.13%     86.58% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           289413066     13.42%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            584891416     27.13%     86.58% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           289412021     13.42%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2155824179                       # Type of FU issued
-system.cpu.iq.rate                           1.675654                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    28385103                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.013167                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5494149121                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3387002536                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1990375209                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           148436520                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           78085554                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     72618270                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2108584760                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                75621770                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         67562501                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2155830788                       # Type of FU issued
+system.cpu.iq.rate                           1.675613                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    28390334                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.013169                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5494230331                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3387151672                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1990359564                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           148436323                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           78075979                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     72618245                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2108598639                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                75619731                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         67436970                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    222270906                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         2427                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         2537                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    135236524                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    222311265                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         1810                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         3927                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    135246124                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         5770                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            18                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         5766                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            21                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              136334512                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 3822943                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                203706                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          3007852435                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           2742591                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             733340932                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            346031420                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 78                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 131030                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  4921                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           2537                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       30744167                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       897447                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             31641614                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2065462954                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             520628814                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          90361225                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles              136348743                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 3855288                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                208511                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          3007924408                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           2746136                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             733381291                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            346041020                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 76                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 131081                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  4887                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           3927                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       30747465                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       896385                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             31643850                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2065446597                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             520632193                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          90384191                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     363595182                       # number of nop insts executed
-system.cpu.iew.exec_refs                    804485830                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                279503743                       # Number of branches executed
-system.cpu.iew.exec_stores                  283857016                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.605419                       # Inst execution rate
-system.cpu.iew.wb_sent                     2064970542                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2062993479                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1176781433                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1743261069                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     363597781                       # number of nop insts executed
+system.cpu.iew.exec_refs                    804489057                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                279489807                       # Number of branches executed
+system.cpu.iew.exec_stores                  283856864                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.605363                       # Inst execution rate
+system.cpu.iew.wb_sent                     2064951145                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2062977809                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1176793581                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1743269600                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.603500                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.675046                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.603444                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.675050                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts     2008987604                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       982155641                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       982229195                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              39                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          28911563                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1150090926                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.746808                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.513435                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          28915749                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1150110878                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.746777                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.513451                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    542926028     47.21%     47.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    216885753     18.86%     66.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    119710361     10.41%     76.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     61150951      5.32%     81.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     44124600      3.84%     85.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     24943285      2.17%     87.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     19289585      1.68%     89.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     16206963      1.41%     90.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8    104853400      9.12%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    542947178     47.21%     47.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    216893273     18.86%     66.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    119702794     10.41%     76.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     61150627      5.32%     81.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     44132968      3.84%     85.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     24929340      2.17%     87.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     19288154      1.68%     89.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     16202986      1.41%     90.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8    104863558      9.12%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1150090926                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1150110878                       # Number of insts commited each cycle
 system.cpu.commit.count                    2008987604                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      721864922                       # Number of memory references committed
@@ -290,50 +290,50 @@ system.cpu.commit.branches                  266706457                       # Nu
 system.cpu.commit.fp_insts                   71824891                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1778941351                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             39955347                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events             104853400                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events             104863558                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   4030744361                       # The number of ROB reads
-system.cpu.rob.rob_writes                  6118806810                       # The number of ROB writes
-system.cpu.timesIdled                            3658                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          131218                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   4030827709                       # The number of ROB reads
+system.cpu.rob.rob_writes                  6118968242                       # The number of ROB writes
+system.cpu.timesIdled                            3723                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          132302                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1823043370                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1823043370                       # Number of Instructions Simulated
-system.cpu.cpi                               0.705719                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.705719                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.416994                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.416994                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2630024814                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1492719850                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  77822488                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 52815654                       # number of floating regfile writes
+system.cpu.cpi                               0.705739                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.705739                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.416955                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.416955                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2630015105                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1492715832                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  77822469                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 52813999                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.icache.replacements                   8249                       # number of replacements
-system.cpu.icache.tagsinuse               1648.525353                       # Cycle average of tags in use
-system.cpu.icache.total_refs                398161333                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   9955                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               39996.115821                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                   8239                       # number of replacements
+system.cpu.icache.tagsinuse               1650.299578                       # Cycle average of tags in use
+system.cpu.icache.total_refs                398190502                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   9946                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               40035.240499                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1648.525353                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.804944                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              398161333                       # number of ReadReq hits
-system.cpu.icache.demand_hits               398161333                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              398161333                       # number of overall hits
-system.cpu.icache.ReadReq_misses                11104                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 11104                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                11104                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      182797500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       182797500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      182797500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          398172437                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           398172437                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          398172437                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0           1650.299578                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.805810                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              398190502                       # number of ReadReq hits
+system.cpu.icache.demand_hits               398190502                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              398190502                       # number of overall hits
+system.cpu.icache.ReadReq_misses                11089                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 11089                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                11089                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      182267000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       182267000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      182267000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          398201591                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           398201591                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          398201591                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000028                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate           0.000028                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate          0.000028                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 16462.310879                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 16462.310879                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 16462.310879                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 16436.739111                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 16436.739111                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 16436.739111                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -343,170 +343,170 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              1148                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               1148                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              1148                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            9956                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             9956                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            9956                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits              1142                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               1142                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              1142                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            9947                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             9947                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            9947                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    119908500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    119908500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    119908500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    119594000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    119594000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    119594000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12043.842909                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12043.842909                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12043.842909                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 12023.122550                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 12023.122550                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 12023.122550                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1526943                       # number of replacements
-system.cpu.dcache.tagsinuse               4095.108553                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                660714952                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1531039                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 431.546781                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              256550000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4095.108553                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999782                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              450471495                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             210243448                       # number of WriteReq hits
+system.cpu.dcache.replacements                1526949                       # number of replacements
+system.cpu.dcache.tagsinuse               4095.114036                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                660843701                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1531045                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 431.629182                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              255450000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4095.114036                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999784                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              450600382                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             210243310                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits                9                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits               660714943                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              660714943                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              1926978                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              551448                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses              3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses               2478426                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2478426                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    71403545500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   20877102491                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency        92500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency     92280647991                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    92280647991                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          452398473                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits               660843692                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              660843692                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              1927019                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              551586                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses               2478605                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2478605                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    71403632500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   20879059491                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency        59000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency     92282691991                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    92282691991                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          452527401                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses         210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses           12                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           663193369                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          663193369                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.004259                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.002616                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.250000                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_accesses           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           663322297                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          663322297                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.004258                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.002617                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.181818                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate           0.003737                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate          0.003737                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 37054.676026                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 37858.696543                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 30833.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 37233.570012                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 37233.570012                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        73500                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        17000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                13                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency 37053.932784                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 37852.772715                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency        29500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 37231.705734                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 37231.705734                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        79500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        20500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                14                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  5653.846154                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets        17000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  5678.571429                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        20500                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   107355                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            467583                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           479805                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits             947388                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits            947388                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1459395                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks                   107353                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            467618                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           479943                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits            1                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits             947561                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits            947561                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1459401                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses          71643                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1531038                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1531038                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses          1531044                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1531044                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  49913534500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   2493312500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  49913659500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   2493461000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency        35000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  52406847000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  52406847000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  52407120500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  52407120500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.003226                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.003225                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000340                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.083333                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.002309                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.002309                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34201.524947                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34801.899697                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.090909                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.002308                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.002308                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34201.469987                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34803.972475                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency        35000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 34229.618729                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 34229.618729                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34229.663223                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34229.663223                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements               1480567                       # number of replacements
-system.cpu.l2cache.tagsinuse             31934.538641                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   62997                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs               1513254                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.041630                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements               1480560                       # number of replacements
+system.cpu.l2cache.tagsinuse             31934.298723                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   62999                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               1513247                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.041632                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0         28868.809118                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          3065.729523                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.881006                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.093559                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                 55380                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              107355                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                4788                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                  60168                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                 60168                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses             1413972                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             66855                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses              1480827                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses             1480827                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   48486615500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   2348963000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency    50835578500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency   50835578500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1469352                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          107355                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.occ_blocks::0         28867.873331                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          3066.425392                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.880978                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.093580                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 55386                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              107353                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                4785                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                  60171                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 60171                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             1413963                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             66858                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses              1480821                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             1480821                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   48486744500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2349128500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    50835873000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   50835873000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1469349                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          107353                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses           71643                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            1540995                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           1540995                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.962310                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.933169                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.960955                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.960955                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34291.071888                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 35135.188094                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34329.181262                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34329.181262                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs        33000                       # number of cycles access was blocked
+system.cpu.l2cache.demand_accesses            1540992                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           1540992                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.962306                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.933211                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.960953                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.960953                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34291.381387                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.086931                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34329.519233                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34329.519233                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs        37500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                6                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                5                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs         5500                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs         7500                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks                   66898                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses        1413972                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        66855                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses         1480827                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses        1480827                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses        1413963                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        66858                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         1480821                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        1480821                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  43834352500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2147649000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  45982001500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  45982001500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency  43834024500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2147795500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  45981820000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  45981820000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.962310                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.933169                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.960955                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.960955                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.863171                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32123.984743                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.568819                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.568819                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.962306                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.933211                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.960953                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.960953                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.828522                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32124.734512                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.572067                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.572067                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 48d5b0b7ad0562f5bade1c76a6dffda64bbc8cc1..9abe7d9304dc2b4281fb3cf41af8d18195b7c299 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:18:43
-gem5 started Jul  9 2011 02:34:35
+gem5 compiled Jul 15 2011 18:02:03
+gem5 started Jul 16 2011 02:25:07
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -1385,4 +1385,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 744105966500 because target called exit()
+Exiting @ tick 774804895000 because target called exit()
index bce6cbb055adbd610540323835fbe621d40aa046..e5f49a16abc286c9e2aaad11dacd7b6253a29912 100644 (file)
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.744106                       # Number of seconds simulated
-sim_ticks                                744105966500                       # Number of ticks simulated
+sim_seconds                                  0.774805                       # Number of seconds simulated
+sim_ticks                                774804895000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  75556                       # Simulator instruction rate (inst/s)
-host_tick_rate                               29820362                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  78044                       # Simulator instruction rate (inst/s)
+host_tick_rate                               32073308                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 264164                       # Number of bytes of host memory used
-host_seconds                                 24952.95                       # Real time elapsed on the host
-sim_insts                                  1885342016                       # Number of instructions simulated
+host_seconds                                 24157.31                       # Real time elapsed on the host
+sim_insts                                  1885341976                       # Number of instructions simulated
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -51,299 +51,300 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1411                       # Number of system calls
-system.cpu.numCycles                       1488211934                       # number of cpu cycles simulated
+system.cpu.numCycles                       1549609791                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                518896793                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          400040732                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           32908651                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             412694566                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                290043770                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                528720404                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          405201149                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           32899214                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             420084737                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                301658852                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                 65454853                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect             2848873                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          431006584                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2627710278                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   518896793                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          355498623                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     704801435                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               227434994                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              113516280                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  240                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          5111                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 399257672                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               8382302                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1436630001                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.536830                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.149737                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                 69231604                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect             2844202                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          441882986                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2652302812                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   528720404                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          370890456                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     718660047                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               237987325                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              141427708                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  230                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          5060                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 410572411                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes              11240316                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1497398135                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.463229                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.115993                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                731865766     50.94%     50.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 52278672      3.64%     54.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                109951004      7.65%     62.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 64331025      4.48%     66.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 92104513      6.41%     73.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 55434190      3.86%     76.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 39408243      2.74%     79.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 32778762      2.28%     82.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                258477826     17.99%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                778775531     52.01%     52.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 50816086      3.39%     55.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                117376582      7.84%     63.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 64268768      4.29%     67.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 98483271      6.58%     74.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 55328075      3.69%     77.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 42969714      2.87%     80.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 33373173      2.23%     82.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                256006935     17.10%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1436630001                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.348671                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.765683                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                474703889                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              92089695                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 671736516                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              10812998                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              187286903                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             70416009                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 13639                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3539876246                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 23440                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              187286903                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                514963010                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                29220198                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles        3511276                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 640788708                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              60859906                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3412725631                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    46                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                4123400                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              48521988                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          3397910620                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups           16198267301                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups      15450730698                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         747536603                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1993166767                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps               1404743848                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             278280                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         278424                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 178635722                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads           1114561414                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           545702989                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         154567236                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        147667095                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 3238356442                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded              281581                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2642482384                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           5796308                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined      1352960304                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   3645177300                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          70016                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1436630001                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.839362                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.852230                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1497398135                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.341196                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.711594                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                490492895                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             110799689                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 685856855                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              14839948                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              195408748                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             70149015                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 13528                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3592611687                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 23480                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              195408748                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                532538328                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                41527455                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles        3530778                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 657203589                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              67189237                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3464582939                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    83                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                4053070                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              53839616                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents               15                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          3447136427                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups           16419760198                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups      15673686759                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         746073439                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1993166703                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps               1453969719                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             280977                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         281142                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 192553677                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads           1121958053                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           549497958                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         186141114                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        133678303                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 3274000051                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded              286918                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2696986204                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          15942313                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined      1388610041                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   3416788899                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          75361                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1497398135                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.801115                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.821957                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           506457907     35.25%     35.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           223599177     15.56%     50.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           229642094     15.98%     66.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           172448421     12.00%     78.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           157180454     10.94%     89.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            90857048      6.32%     96.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            40453427      2.82%     98.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            11405646      0.79%     99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             4585827      0.32%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           520879280     34.79%     34.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           250662816     16.74%     51.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           249981874     16.69%     68.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           183430350     12.25%     80.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           145558199      9.72%     90.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            90126006      6.02%     96.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            37572713      2.51%     98.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            15725690      1.05%     99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             3461207      0.23%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1436630001                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1497398135                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1185558      1.85%      1.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  23950      0.04%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               40505203     63.35%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              22224408     34.76%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  466158      0.65%      0.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  23952      0.03%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               43631235     60.82%     61.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              27621714     38.50%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1237165385     46.82%     46.82% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult             11226668      0.42%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                 8630      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.24% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.05%     47.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         6876475      0.26%     47.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         6142371      0.23%     47.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       24460385      0.93%     48.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     48.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.71% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     48.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            896605446     33.93%     82.64% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           458621735     17.36%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1249934524     46.35%     46.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult             15347152      0.57%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                 8678      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     46.91% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.05%     46.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     46.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         6876474      0.25%     47.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         5502225      0.20%     47.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.42% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       24546538      0.91%     48.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     48.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     48.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            926115609     34.34%     82.67% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           467279715     17.33%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2642482384                       # Type of FU issued
-system.cpu.iq.rate                           1.775609                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    63939119                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.024197                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         6661297580                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        4469277070                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2420670942                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           130032616                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          124010144                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     59075392                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2641405327                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                65016176                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         73114963                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2696986204                       # Type of FU issued
+system.cpu.iq.rate                           1.740429                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    71743059                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.026601                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6850131362                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        4543112182                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2499696981                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           128924553                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          123913779                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     57056788                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2702891798                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                65837465                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         68903819                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    483170898                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        99011                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation      3650929                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    268704359                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    490567545                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        34373                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation      5468301                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    272499336                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads           94                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads           85                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked            25                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              187286903                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                16548451                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1477546                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          3238703739                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts          11872283                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts            1114561414                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            545702989                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             268887                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1475433                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   305                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents        3650929                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       36090139                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8517669                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             44607808                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2538548253                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             842723322                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts         103934131                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles              195408748                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                16548936                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1477418                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          3274352719                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           7542599                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts            1121958053                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            549497958                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             274197                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1475285                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   266                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents        5468301                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       35960500                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8891555                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             44852055                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2594017984                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             869263464                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts         102968220                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         65716                       # number of nop insts executed
-system.cpu.iew.exec_refs                   1272992998                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                351489842                       # Number of branches executed
-system.cpu.iew.exec_stores                  430269676                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.705771                       # Inst execution rate
-system.cpu.iew.wb_sent                     2508384244                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2479746334                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1467036313                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2710651250                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         65750                       # number of nop insts executed
+system.cpu.iew.exec_refs                   1311874105                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                351627111                       # Number of branches executed
+system.cpu.iew.exec_stores                  442610641                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.673981                       # Inst execution rate
+system.cpu.iew.wb_sent                     2572992074                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2556753769                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1518871802                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2751373427                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.666259                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.541212                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.649934                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.552041                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts     1885353032                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts      1353312364                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          211565                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          38431023                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1249343100                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.509075                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.191779                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts     1885352992                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts      1388961384                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          211557                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          38421689                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1301989389                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.448056                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.137383                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    548617532     43.91%     43.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    340979538     27.29%     71.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    105479188      8.44%     79.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     77201400      6.18%     85.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     51871134      4.15%     89.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     18884009      1.51%     91.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     20943022      1.68%     93.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      8690011      0.70%     93.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     76677266      6.14%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    590521474     45.36%     45.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    345830520     26.56%     71.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    113709906      8.73%     80.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     73638275      5.66%     86.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     53779351      4.13%     90.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     24377206      1.87%     92.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     19730682      1.52%     93.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      7415491      0.57%     94.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     72986484      5.61%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1249343100                       # Number of insts commited each cycle
-system.cpu.commit.count                    1885353032                       # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total   1301989389                       # Number of insts commited each cycle
+system.cpu.commit.count                    1885352992                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      908389145                       # Number of memory references committed
-system.cpu.commit.loads                     631390515                       # Number of loads committed
+system.cpu.commit.refs                      908389129                       # Number of memory references committed
+system.cpu.commit.loads                     631390507                       # Number of loads committed
 system.cpu.commit.membars                        9986                       # Number of memory barriers committed
-system.cpu.commit.branches                  291351878                       # Number of branches committed
+system.cpu.commit.branches                  291351870                       # Number of branches committed
 system.cpu.commit.fp_insts                   52289415                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                1653712207                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                1653712175                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             41577833                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              76677266                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              72986484                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   4411312885                       # The number of ROB reads
-system.cpu.rob.rob_writes                  6664635759                       # The number of ROB writes
-system.cpu.timesIdled                         1344981                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        51581933                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                  1885342016                       # Number of Instructions Simulated
-system.cpu.committedInsts_total            1885342016                       # Number of Instructions Simulated
-system.cpu.cpi                               0.789359                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.789359                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.266850                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.266850                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads              12578509945                       # number of integer regfile reads
-system.cpu.int_regfile_writes              2395231974                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  70809202                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 51453484                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              4059454744                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               13779568                       # number of misc regfile writes
-system.cpu.icache.replacements                  25817                       # number of replacements
-system.cpu.icache.tagsinuse               1640.813432                       # Cycle average of tags in use
-system.cpu.icache.total_refs                399229379                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  27501                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               14516.904076                       # Average number of references to valid blocks.
+system.cpu.rob.rob_reads                   4503298936                       # The number of ROB reads
+system.cpu.rob.rob_writes                  6744049642                       # The number of ROB writes
+system.cpu.timesIdled                         1345030                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        52211656                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1885341976                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1885341976                       # Number of Instructions Simulated
+system.cpu.cpi                               0.821925                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.821925                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.216656                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.216656                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads              12929172445                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2454347411                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  68793732                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 50170083                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              4128169598                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               13779552                       # number of misc regfile writes
+system.cpu.icache.replacements                  25756                       # number of replacements
+system.cpu.icache.tagsinuse               1635.277334                       # Cycle average of tags in use
+system.cpu.icache.total_refs                410544180                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  27432                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               14965.885827                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1640.813432                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.801178                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              399229380                       # number of ReadReq hits
-system.cpu.icache.demand_hits               399229380                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              399229380                       # number of overall hits
-system.cpu.icache.ReadReq_misses                28292                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 28292                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                28292                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      269405500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       269405500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      269405500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          399257672                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           399257672                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          399257672                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000071                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000071                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000071                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency  9522.320797                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency  9522.320797                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency  9522.320797                       # average overall miss latency
+system.cpu.icache.occ_blocks::0           1635.277334                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.798475                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              410544181                       # number of ReadReq hits
+system.cpu.icache.demand_hits               410544181                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              410544181                       # number of overall hits
+system.cpu.icache.ReadReq_misses                28230                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 28230                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                28230                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      268370000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       268370000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      268370000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          410572411                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           410572411                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          410572411                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000069                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000069                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000069                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency  9506.553312                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency  9506.553312                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency  9506.553312                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -353,143 +354,143 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               785                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                785                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               785                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           27507                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            27507                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           27507                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits               792                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                792                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               792                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           27438                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            27438                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           27438                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    166096000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    166096000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    166096000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    164813000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    164813000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    164813000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000069                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000069                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000069                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  6038.317519                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  6038.317519                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  6038.317519                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000067                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000067                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000067                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  6006.742474                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  6006.742474                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  6006.742474                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1531025                       # number of replacements
-system.cpu.dcache.tagsinuse               4094.846671                       # Cycle average of tags in use
-system.cpu.dcache.total_refs               1028461825                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1535121                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 669.954893                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              306448000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4094.846671                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999718                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              752304344                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             276127089                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits            17060                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits             13318                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits              1028431433                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits             1028431433                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              1932486                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              808589                       # number of WriteReq misses
+system.cpu.dcache.replacements                1531422                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.889747                       # Cycle average of tags in use
+system.cpu.dcache.total_refs               1060675603                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1535518                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 690.760775                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              306953000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4094.889747                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999729                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              784517362                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             276127149                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            17768                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             13310                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits              1060644511                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits             1060644511                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              1932656                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              808529                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses              3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses               2741075                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2741075                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    69636872500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   28315241500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses               2741185                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2741185                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    69641234000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   28315172500                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency       108500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency     97952114000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    97952114000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          754236830                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency     97956406500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    97956406500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          786450018                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses         276935678                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses        17063                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses         13318                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses          1031172508                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses         1031172508                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.002562                       # miss rate for ReadReq accesses
+system.cpu.dcache.LoadLockedReq_accesses        17771                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         13310                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses          1063385696                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses         1063385696                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.002457                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate         0.002920                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.000176                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.002658                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.002658                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 36034.865194                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 35018.088918                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_miss_rate     0.000169                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.002578                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.002578                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 36033.952240                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 35020.602229                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 35734.926626                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 35734.926626                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency 35735.058560                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 35735.058560                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        59000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        59500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets        14750                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        14875                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   106614                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            470081                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           735866                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks                   106530                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            469858                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           735802                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1205947                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1205947                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1462405                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses          72723                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1535128                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1535128                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_hits            1205660                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1205660                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1462798                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses          72727                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          1535525                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1535525                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  50067282500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   2361289000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  52428571500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  52428571500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  50071553500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   2361380000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  52432933500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  52432933500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001939                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001860                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000263                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.001489                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.001489                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34236.263210                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32469.631341                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 34152.573271                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 34152.573271                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate      0.001444                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.001444                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34229.984933                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32469.096759                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34146.584067                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34146.584067                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements               1479866                       # number of replacements
-system.cpu.l2cache.tagsinuse             31973.633477                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   82869                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs               1512586                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.054786                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements               1479883                       # number of replacements
+system.cpu.l2cache.tagsinuse             31974.412351                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   83096                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               1512603                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.054936                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0         29008.320334                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          2965.313143                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.885264                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.090494                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                 74752                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              106614                       # number of Writeback hits
+system.cpu.l2cache.occ_blocks::0         29007.598549                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1          2966.813802                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.885242                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.090540                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 75017                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              106530                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits                  2                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits                6636                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                  81388                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                 81388                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses             1415154                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_hits                6638                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                  81655                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 81655                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             1415213                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses                4                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses             66081                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses              1481235                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses             1481235                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   48603615500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   2279719000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency    50883334500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency   50883334500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1489906                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          106614                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_misses             66083                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses              1481296                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             1481296                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   48605841000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2279788500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    50885629500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   50885629500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1490230                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          106530                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses              6                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses           72717                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            1562623                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           1562623                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.949828                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_accesses           72721                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            1562951                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           1562951                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.949661                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate      0.666667                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.908742                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.947916                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.947916                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34345.106964                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.857463                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34351.966096                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34351.966096                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate       0.908720                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.947756                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.947756                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34345.247676                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.865064                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34352.100796                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34352.100796                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -499,31 +500,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks                   66099                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits               27                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits                27                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits               27                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses        1415127                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_hits               24                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                24                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits               24                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses        1415189                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses            4                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        66081                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses         1481208                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses        1481208                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        66083                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         1481272                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        1481272                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  44021028500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency  44022928500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency       124000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2048574500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  46069603000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  46069603000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   2048636000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  46071564500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  46071564500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.949810                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.949645                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.666667                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.908742                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.947899                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.947899                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31107.475513                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.908720                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.947741                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.947741                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31107.455259                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.960942                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.723588                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.723588                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.953347                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.703960                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.703960                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 524033226dbddbe1abc1f5ae2d97e2842849d3b3..50848dbffe3a61c7721c76b2a0194b48db6497e2 100755 (executable)
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:00:53
-gem5 started Jul  8 2011 17:12:27
+gem5 compiled Jul 15 2011 17:43:54
+gem5 started Jul 15 2011 19:00:26
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 24044597000 because target called exit()
+Exiting @ tick 22743377000 because target called exit()
index 1270e888715606ec7bc7db4929e242bf940b342f..f7387c5fb141ffac7030f5a5f3e8161d4380364a 100644 (file)
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.024045                       # Number of seconds simulated
-sim_ticks                                 24044597000                       # Number of ticks simulated
+sim_seconds                                  0.022743                       # Number of seconds simulated
+sim_ticks                                 22743377000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  91114                       # Simulator instruction rate (inst/s)
-host_tick_rate                               27525458                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 256064                       # Number of bytes of host memory used
-host_seconds                                   873.54                       # Real time elapsed on the host
+host_inst_rate                                  91653                       # Simulator instruction rate (inst/s)
+host_tick_rate                               26189824                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 255808                       # Number of bytes of host memory used
+host_seconds                                   868.41                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     23266854                       # DTB read hits
-system.cpu.dtb.read_misses                     225542                       # DTB read misses
-system.cpu.dtb.read_acv                            45                       # DTB read access violations
-system.cpu.dtb.read_accesses                 23492396                       # DTB read accesses
-system.cpu.dtb.write_hits                    16036454                       # DTB write hits
-system.cpu.dtb.write_misses                     32845                       # DTB write misses
-system.cpu.dtb.write_acv                           10                       # DTB write access violations
-system.cpu.dtb.write_accesses                16069299                       # DTB write accesses
-system.cpu.dtb.data_hits                     39303308                       # DTB hits
-system.cpu.dtb.data_misses                     258387                       # DTB misses
-system.cpu.dtb.data_acv                            55                       # DTB access violations
-system.cpu.dtb.data_accesses                 39561695                       # DTB accesses
-system.cpu.itb.fetch_hits                    15336941                       # ITB hits
-system.cpu.itb.fetch_misses                     33582                       # ITB misses
+system.cpu.dtb.read_hits                     21751129                       # DTB read hits
+system.cpu.dtb.read_misses                     175370                       # DTB read misses
+system.cpu.dtb.read_acv                            31                       # DTB read access violations
+system.cpu.dtb.read_accesses                 21926499                       # DTB read accesses
+system.cpu.dtb.write_hits                    15297508                       # DTB write hits
+system.cpu.dtb.write_misses                     26341                       # DTB write misses
+system.cpu.dtb.write_acv                            6                       # DTB write access violations
+system.cpu.dtb.write_accesses                15323849                       # DTB write accesses
+system.cpu.dtb.data_hits                     37048637                       # DTB hits
+system.cpu.dtb.data_misses                     201711                       # DTB misses
+system.cpu.dtb.data_acv                            37                       # DTB access violations
+system.cpu.dtb.data_accesses                 37250348                       # DTB accesses
+system.cpu.itb.fetch_hits                    14100005                       # ITB hits
+system.cpu.itb.fetch_misses                     36420                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                15370523                       # ITB accesses
+system.cpu.itb.fetch_accesses                14136425                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -41,246 +41,246 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                         48089197                       # number of cpu cycles simulated
+system.cpu.numCycles                         45486755                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 18361326                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           11820514                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             546274                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              16009789                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  9688195                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 16901328                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           10975275                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             456849                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              14797141                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  8724675                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  2216159                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               37765                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           16493376                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      115096464                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    18361326                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           11904354                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      22748230                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3321567                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                5575284                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 7555                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        339871                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  15336941                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                325972                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           47646209                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.415648                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.066102                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                  2018610                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               35075                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           15142621                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      107619262                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16901328                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           10743285                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      20909720                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2286025                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                6121858                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                13576                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        358341                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  14100005                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                211722                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           44264196                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.431294                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.090704                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 24897979     52.26%     52.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2453036      5.15%     57.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1946901      4.09%     61.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2330257      4.89%     66.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4220177      8.86%     75.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2180283      4.58%     79.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   821973      1.73%     81.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1319930      2.77%     84.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  7475673     15.69%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 23354476     52.76%     52.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2087705      4.72%     57.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1683152      3.80%     61.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2128946      4.81%     66.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3922871      8.86%     74.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1978801      4.47%     79.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   718343      1.62%     81.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1236348      2.79%     83.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  7153554     16.16%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             47646209                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.381818                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.393395                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 17905619                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               5001845                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  21498707                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                855219                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2384819                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              4163553                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 99872                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              112485204                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                269698                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2384819                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 18579816                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 2454161                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          95593                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  21627471                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               2504349                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              110486741                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   205                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  26203                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               2324239                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands            66683343                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             133326137                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        132820452                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            505685                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             44264196                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.371566                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.365947                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 16625814                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               5350938                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  19481362                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1184271                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1621811                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3792639                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 98494                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              105768441                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                262977                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1621811                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 17249190                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 1859026                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          92496                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  19962312                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               3479361                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              104444741                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   108                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  62263                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               3183210                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands            62854370                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             126007838                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        125513406                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            494432                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 14136462                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               5422                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           5420                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   5146770                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             24822811                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            17209754                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           6587978                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          5178123                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   97041243                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                5374                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  92467963                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            130783                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        16243425                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      8385088                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            791                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      47646209                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.940720                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.968352                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 10307489                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               5394                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           5392                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   7022840                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             23585547                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16625780                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          13013966                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         10091747                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   92564607                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                5349                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  87311286                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             89819                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        12800874                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      8559564                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            766                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      44264196                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.972504                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.848460                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            15463365     32.45%     32.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             9039378     18.97%     51.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7091354     14.88%     66.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5453112     11.45%     77.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4876639     10.24%     87.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2621564      5.50%     93.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1784714      3.75%     97.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              964783      2.02%     99.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              351300      0.74%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            12024331     27.16%     27.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             9739894     22.00%     49.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7505625     16.96%     66.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5587744     12.62%     78.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4605636     10.40%     89.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2526104      5.71%     94.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1401834      3.17%     98.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              651382      1.47%     99.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              221646      0.50%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        47646209                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        44264196                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  124763      7.84%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 734633     46.19%     54.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                731207     45.97%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  145655     11.21%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 556077     42.81%     54.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                597272     45.98%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              52052276     56.29%     56.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                44017      0.05%     56.34% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     56.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              126208      0.14%     56.48% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  89      0.00%     56.48% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt              127891      0.14%     56.61% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 54      0.00%     56.61% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv               38663      0.04%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.66% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             23785526     25.72%     82.38% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            16293239     17.62%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49414746     56.60%     56.60% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                43477      0.05%     56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              125010      0.14%     56.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  88      0.00%     56.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt              125425      0.14%     56.93% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 51      0.00%     56.93% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv               38600      0.04%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             22113935     25.33%     82.30% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            15449954     17.70%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               92467963                       # Type of FU issued
-system.cpu.iq.rate                           1.922843                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1590603                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.017202                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          233677952                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         112998578                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     89931166                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              625569                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             496845                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       303653                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               93745634                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  312932                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1274888                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               87311286                       # Type of FU issued
+system.cpu.iq.rate                           1.919488                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1299004                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014878                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          219655218                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         104890132                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     85660866                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              620373                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             492550                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       303658                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               88299901                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  310389                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1470541                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4546173                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        15179                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       214045                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2596377                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3308909                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         2159                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        11951                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2012403                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         1708                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            34                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         1474                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            23                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2384819                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1408212                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 65481                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           106909939                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            348634                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              24822811                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             17209754                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               5373                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  47651                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  1257                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         214045                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         396366                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       133925                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               530291                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              91241048                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23498667                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1226915                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1621811                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  650255                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 46881                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           102207113                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            299211                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              23585547                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16625780                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5349                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  10530                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  7811                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          11951                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         297237                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       113949                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               411186                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              86536224                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              21928950                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            775062                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       9863322                       # number of nop insts executed
-system.cpu.iew.exec_refs                     39568381                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 15970661                       # Number of branches executed
-system.cpu.iew.exec_stores                   16069714                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.897329                       # Inst execution rate
-system.cpu.iew.wb_sent                       90664382                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      90234819                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  34760730                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  45726026                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       9637157                       # number of nop insts executed
+system.cpu.iew.exec_refs                     37253187                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15011802                       # Number of branches executed
+system.cpu.iew.exec_stores                   15324237                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.902449                       # Inst execution rate
+system.cpu.iew.wb_sent                       86279934                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      85964524                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  34688342                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  46291790                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.876405                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.760196                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.889880                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.749341                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts       88340672                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        15596601                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        11023437                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            449200                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     45261390                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.951789                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.640164                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            360580                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     42642385                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.071663                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.676209                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     20510945     45.32%     45.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      8049130     17.78%     63.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4022759      8.89%     71.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2704759      5.98%     77.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2151725      4.75%     82.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1309190      2.89%     85.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1156461      2.56%     88.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       811237      1.79%     89.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      4545184     10.04%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     17681432     41.46%     41.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      8356070     19.60%     61.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3960782      9.29%     70.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2934126      6.88%     77.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1908842      4.48%     81.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1271711      2.98%     84.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1063495      2.49%     87.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       841649      1.97%     89.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4624278     10.84%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     45261390                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     42642385                       # Number of insts commited each cycle
 system.cpu.commit.count                      88340672                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       34890015                       # Number of memory references committed
@@ -290,50 +290,50 @@ system.cpu.commit.branches                   13754477                       # Nu
 system.cpu.commit.fp_insts                     267754                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                  77942044                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1661057                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               4545184                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               4624278                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    143336137                       # The number of ROB reads
-system.cpu.rob.rob_writes                   210280269                       # The number of ROB writes
-system.cpu.timesIdled                           17593                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          442988                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    136064874                       # The number of ROB reads
+system.cpu.rob.rob_writes                   200355381                       # The number of ROB writes
+system.cpu.timesIdled                           41664                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         1222559                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
 system.cpu.committedInsts_total              79591756                       # Number of Instructions Simulated
-system.cpu.cpi                               0.604198                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.604198                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.655086                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.655086                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                120263319                       # number of integer regfile reads
-system.cpu.int_regfile_writes                59810170                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    254298                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   248799                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                   38083                       # number of misc regfile reads
+system.cpu.cpi                               0.571501                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.571501                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.749779                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.749779                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                114385631                       # number of integer regfile reads
+system.cpu.int_regfile_writes                57104236                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    255197                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   247532                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                   38059                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.icache.replacements                  89120                       # number of replacements
-system.cpu.icache.tagsinuse               1938.678415                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 15241390                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  91168                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                 167.179164                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            19910148000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1938.678415                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.946620                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               15241390                       # number of ReadReq hits
-system.cpu.icache.demand_hits                15241390                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               15241390                       # number of overall hits
-system.cpu.icache.ReadReq_misses                95551                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 95551                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                95551                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      914249000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       914249000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      914249000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           15336941                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            15336941                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           15336941                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.006230                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.006230                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.006230                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency  9568.178250                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency  9568.178250                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency  9568.178250                       # average overall miss latency
+system.cpu.icache.replacements                  89406                       # number of replacements
+system.cpu.icache.tagsinuse               1932.641583                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 14004218                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  91454                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                 153.128545                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            18957437000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1932.641583                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.943673                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               14004218                       # number of ReadReq hits
+system.cpu.icache.demand_hits                14004218                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               14004218                       # number of overall hits
+system.cpu.icache.ReadReq_misses                95787                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 95787                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                95787                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      913804000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       913804000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      913804000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           14100005                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            14100005                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           14100005                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.006793                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.006793                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.006793                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency  9539.958449                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency  9539.958449                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency  9539.958449                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -343,132 +343,132 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              4382                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               4382                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              4382                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           91169                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            91169                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           91169                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits              4332                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               4332                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              4332                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           91455                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            91455                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           91455                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    543344000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    543344000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    543344000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    543662500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    543662500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    543662500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.005944                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.005944                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.005944                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  5959.745089                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  5959.745089                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  5959.745089                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.006486                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.006486                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.006486                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  5944.590236                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  5944.590236                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  5944.590236                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 201407                       # number of replacements
-system.cpu.dcache.tagsinuse               4078.388125                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 35317915                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 205503                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 171.860824                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              157900000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4078.388125                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.995700                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               21738841                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              13579023                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits               51                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits                35317864                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               35317864                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               251339                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1034354                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               1285693                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              1285693                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     8138657000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   33935878000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     42074535000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    42074535000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           21990180                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                 201138                       # number of replacements
+system.cpu.dcache.tagsinuse               4077.454255                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 33705391                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 205234                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 164.229080                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              157412000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4077.454255                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.995472                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               20126386                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              13578957                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits               48                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits                33705343                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               33705343                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               152658                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1034420                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               1187078                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1187078                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     4522200000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   33957528000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     38479728000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    38479728000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           20279044                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses          14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses           51                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            36603557                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           36603557                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.011430                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.070781                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.035125                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.035125                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 32381.194323                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 32808.765664                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 32725.180117                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 32725.180117                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        35000                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses           48                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            34892421                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           34892421                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.007528                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.070786                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.034021                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.034021                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 29623.079039                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 32827.601941                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 32415.500919                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 32415.500919                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        24500                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets        27000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                12                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 9                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  2916.666667                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  2722.222222                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets        27000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   161690                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            189291                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           890899                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1080190                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1080190                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses           62048                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         143455                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           205503                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          205503                       # number of overall MSHR misses
+system.cpu.dcache.writebacks                   161549                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits             90911                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits           890933                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits             981844                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits            981844                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses           61747                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         143487                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           205234                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          205234                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1276790500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   4734659000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   6011449500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   6011449500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   1261220000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   4731766000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   5992986000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   5992986000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.002822                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.009817                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.005614                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.005614                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20577.464221                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33004.489213                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 29252.368579                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 29252.368579                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.003045                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.009819                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.005882                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.005882                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20425.607722                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32976.966554                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 29200.746465                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 29200.746465                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                149093                       # number of replacements
-system.cpu.l2cache.tagsinuse             19055.908605                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  137732                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                174459                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.789481                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                148998                       # number of replacements
+system.cpu.l2cache.tagsinuse             18953.465492                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  137682                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                174354                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.789669                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          3306.185097                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15749.723508                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.100897                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.480643                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                109176                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              161690                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               12067                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 121243                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                121243                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               44033                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            131396                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               175429                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              175429                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1515312500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   4525725000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     6041037500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    6041037500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            153209                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          161690                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          143463                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             296672                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            296672                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.287405                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.915888                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.591323                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.591323                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34413.110622                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34443.400104                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34435.797388                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34435.797388                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::0          3229.937002                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15723.528490                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.098570                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.479844                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                109274                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              161549                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits               12075                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 121349                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                121349                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               43926                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses            131414                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               175340                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              175340                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1500006000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   4522435500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     6022441500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    6022441500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            153200                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          161549                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          143489                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             296689                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            296689                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.286723                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.915847                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.590989                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.590989                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34148.476984                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34413.650753                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34347.219687                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34347.219687                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -480,24 +480,24 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.writebacks                  120514                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          44033                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       131396                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          175429                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         175429                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses          43926                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       131414                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          175340                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         175340                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1366746000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   4118762500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   5485508500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   5485508500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1363479000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   4116799500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   5480278500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   5480278500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.287405                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.915888                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.591323                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.591323                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31039.129744                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31346.178727                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31269.108870                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31269.108870                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.286723                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.915847                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.590989                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.590989                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.363338                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31326.947662                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31255.152846                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31255.152846                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 02f7c240f8c826145eadaa05d191770dfe5bae4a..6d7c0bcb0187ef57852ef0f43f8c80289f808037 100644 (file)
@@ -499,7 +499,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
index e55995a7b72627b620747f50075c8414b9a60196..46c2d059175f37e39007cd7c73f92855766b2de7 100755 (executable)
@@ -1,11 +1,13 @@
+Redirecting stdout to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  6 2011 16:04:36
-gem5 started Aug  6 2011 16:04:41
-gem5 executing on burrito
+gem5 compiled Aug 16 2011 09:57:35
+gem5 started Aug 16 2011 10:08:58
+gem5 executing on nadc-0270
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 36244602000 because target called exit()
+Exiting @ tick 36358325000 because target called exit()
index bf47534bc229d5b334a30f2fa35f1432ac0b38f9..95c5d6049d2dd21d2fb55d8c24d7a903dcc938b5 100644 (file)
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.036245                       # Number of seconds simulated
-sim_ticks                                 36244602000                       # Number of ticks simulated
+sim_seconds                                  0.036358                       # Number of seconds simulated
+sim_ticks                                 36358325000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  65776                       # Simulator instruction rate (inst/s)
-host_tick_rate                               23690223                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 246996                       # Number of bytes of host memory used
-host_seconds                                  1529.94                       # Real time elapsed on the host
-sim_insts                                   100633890                       # Number of instructions simulated
+host_inst_rate                                 119827                       # Simulator instruction rate (inst/s)
+host_tick_rate                               43292688                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 272264                       # Number of bytes of host memory used
+host_seconds                                   839.83                       # Real time elapsed on the host
+sim_insts                                   100633775                       # Number of instructions simulated
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -51,300 +51,300 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                         72489205                       # number of cpu cycles simulated
+system.cpu.numCycles                         72716651                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 18012293                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           11774570                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             831874                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              15324494                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  9861947                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 18013375                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           11772112                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             832376                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              15327252                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  9900840                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  1962775                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect              178630                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           13228591                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       90356599                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    18012293                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           11824722                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      23464914                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3236872                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               32247240                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   76                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1180                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  12447619                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                228695                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           71274246                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.770512                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.958690                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                  1964037                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect              178584                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           13247418                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       90436613                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    18013375                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           11864877                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      23481643                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 3251985                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               32424598                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   56                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1373                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  12458457                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                221175                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           71500308                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.766045                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.955660                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 47826012     67.10%     67.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2503425      3.51%     70.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2625051      3.68%     74.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2508744      3.52%     77.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1756176      2.46%     80.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1729968      2.43%     82.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1023399      1.44%     84.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1314592      1.84%     85.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  9986879     14.01%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 48035418     67.18%     67.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2508903      3.51%     70.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2594650      3.63%     74.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2541855      3.56%     77.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1760239      2.46%     80.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1724167      2.41%     82.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1024110      1.43%     84.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1345153      1.88%     86.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  9965813     13.94%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             71274246                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.248482                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.246484                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 15570258                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              30538007                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  21052115                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1880159                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2233707                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3555145                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                100131                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              123096705                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                322054                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2233707                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 17831809                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 3189949                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       20082985                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  20587918                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               7347878                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              119869132                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     4                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 121794                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               5771428                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              352                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           121512131                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             551578616                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        551477586                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            101030                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              99143893                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 22368233                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             776347                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         776986                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  18154637                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             30367199                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            22985654                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          18156398                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         16040246                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  114470256                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded              775996                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 107895564                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            172091                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        14439119                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     40080699                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          74965                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      71274246                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.513809                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.644216                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total             71500308                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.247720                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.243685                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 15629487                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              30668783                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  20991644                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1963924                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2246470                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3557308                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                100615                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              123225405                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                322834                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2246470                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 17904325                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 3174295                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       20084450                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  20590055                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               7500713                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              119940984                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     3                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 135288                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               5895117                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              346                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           121539560                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             551911893                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        551809859                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            102034                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              99143709                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 22395801                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             778680                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         778694                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  18433689                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             30390382                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            23021081                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          18365996                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         16439244                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  114579507                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded              778229                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 107939670                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            154653                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        14553196                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     40300795                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          77221                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      71500308                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.509639                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.632123                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            25395561     35.63%     35.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            17825654     25.01%     60.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            10968613     15.39%     76.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7406584     10.39%     86.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             5364631      7.53%     93.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2359706      3.31%     97.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1195437      1.68%     98.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              581224      0.82%     99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              176836      0.25%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            25383976     35.50%     35.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            17917807     25.06%     60.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            11054386     15.46%     76.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7575334     10.59%     86.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             5467314      7.65%     94.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2200256      3.08%     97.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1169231      1.64%     98.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              554865      0.78%     99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              177139      0.25%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        71274246                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        71500308                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  116212      6.09%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1547826     81.16%     87.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                243196     12.75%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  116974      6.43%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1491133     81.95%     88.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                211505     11.62%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              57756459     53.53%     53.53% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                87061      0.08%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  21      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    2      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     53.61% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             28748786     26.65%     80.26% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21303228     19.74%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              57828785     53.58%     53.58% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                87098      0.08%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  50      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    3      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     53.66% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             28711971     26.60%     80.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21311756     19.74%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              107895564                       # Type of FU issued
-system.cpu.iq.rate                           1.488436                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1907234                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.017677                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          289144535                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         129693775                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    105980229                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 164                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                164                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           71                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              109802715                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                      83                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1086375                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              107939670                       # Type of FU issued
+system.cpu.iq.rate                           1.484387                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1819612                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.016858                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          289353682                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         129921210                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    106049922                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 224                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                300                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           90                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              109759169                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     113                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1061783                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3058688                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         1951                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         8954                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2428515                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3081882                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         2255                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        10977                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2463953                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads           42                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads           46                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked            45                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2233707                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1028781                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 38378                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           115325010                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            602761                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              30367199                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             22985654                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             758781                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   5441                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  5622                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           8954                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         689500                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       204403                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               893903                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             106692633                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              28420136                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1202931                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                2246470                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1025437                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 38382                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           115436550                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            596020                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              30390382                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             23021081                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             761032                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   4943                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  5670                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          10977                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         689404                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       204972                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               894376                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             106732644                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              28388861                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1207019                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         78758                       # number of nop insts executed
-system.cpu.iew.exec_refs                     49527893                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14765827                       # Number of branches executed
-system.cpu.iew.exec_stores                   21107757                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.471842                       # Inst execution rate
-system.cpu.iew.wb_sent                      106228536                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     105980300                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  55087780                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 106077595                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         78814                       # number of nop insts executed
+system.cpu.iew.exec_refs                     49502432                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14773493                       # Number of branches executed
+system.cpu.iew.exec_stores                   21113571                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.467788                       # Inst execution rate
+system.cpu.iew.wb_sent                      106273270                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     106050012                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  55103842                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 106001150                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.462015                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.519316                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.458401                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.519842                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      100639442                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        14606204                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          701031                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            796162                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     69040540                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.457686                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.138867                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts      100639327                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        14717021                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          701008                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            796431                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     69253839                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.453195                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.128132                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     30680365     44.44%     44.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     19612880     28.41%     72.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4794365      6.94%     79.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4311364      6.24%     86.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3142866      4.55%     90.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1355731      1.96%     92.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       737162      1.07%     93.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       515807      0.75%     94.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3890000      5.63%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     30742933     44.39%     44.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     19764540     28.54%     72.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4768337      6.89%     79.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4180096      6.04%     85.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3349632      4.84%     90.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1422305      2.05%     92.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       712095      1.03%     93.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       496006      0.72%     94.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3817895      5.51%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     69040540                       # Number of insts commited each cycle
-system.cpu.commit.count                     100639442                       # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total     69253839                       # Number of insts commited each cycle
+system.cpu.commit.count                     100639327                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       47865649                       # Number of memory references committed
-system.cpu.commit.loads                      27308510                       # Number of loads committed
+system.cpu.commit.refs                       47865603                       # Number of memory references committed
+system.cpu.commit.loads                      27308487                       # Number of loads committed
 system.cpu.commit.membars                       15920                       # Number of memory barriers committed
-system.cpu.commit.branches                   13670029                       # Number of branches committed
+system.cpu.commit.branches                   13670006                       # Number of branches committed
 system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  91478391                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                  91478299                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               3890000                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               3817895                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    180370887                       # The number of ROB reads
-system.cpu.rob.rob_writes                   232731383                       # The number of ROB writes
-system.cpu.timesIdled                           61980                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         1214959                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   100633890                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             100633890                       # Number of Instructions Simulated
-system.cpu.cpi                               0.720326                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.720326                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.388260                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.388260                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                512693420                       # number of integer regfile reads
-system.cpu.int_regfile_writes               104594221                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       142                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      118                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               148024846                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                  34642                       # number of misc regfile writes
-system.cpu.icache.replacements                  27879                       # number of replacements
-system.cpu.icache.tagsinuse               1824.272942                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 12416599                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  29916                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                 415.048770                       # Average number of references to valid blocks.
+system.cpu.rob.rob_reads                    180766993                       # The number of ROB reads
+system.cpu.rob.rob_writes                   232965550                       # The number of ROB writes
+system.cpu.timesIdled                           61914                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         1216343                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   100633775                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             100633775                       # Number of Instructions Simulated
+system.cpu.cpi                               0.722587                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.722587                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.383917                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.383917                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                512803523                       # number of integer regfile reads
+system.cpu.int_regfile_writes               104642569                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       286                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      254                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               148108878                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                  34596                       # number of misc regfile writes
+system.cpu.icache.replacements                  27541                       # number of replacements
+system.cpu.icache.tagsinuse               1822.972635                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 12427797                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  29578                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                 420.170295                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1824.272942                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.890758                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               12416599                       # number of ReadReq hits
-system.cpu.icache.demand_hits                12416599                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               12416599                       # number of overall hits
-system.cpu.icache.ReadReq_misses                31020                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 31020                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                31020                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      368970500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       368970500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      368970500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           12447619                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            12447619                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           12447619                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.002492                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.002492                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.002492                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 11894.600258                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 11894.600258                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 11894.600258                       # average overall miss latency
+system.cpu.icache.occ_blocks::0           1822.972635                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.890123                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               12427797                       # number of ReadReq hits
+system.cpu.icache.demand_hits                12427797                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               12427797                       # number of overall hits
+system.cpu.icache.ReadReq_misses                30660                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 30660                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                30660                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      366375500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       366375500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      366375500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           12458457                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            12458457                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           12458457                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.002461                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.002461                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.002461                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 11949.624918                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 11949.624918                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 11949.624918                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -354,143 +354,143 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              1093                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               1093                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              1093                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           29927                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            29927                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           29927                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits              1075                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               1075                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              1075                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           29585                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            29585                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           29585                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    251359000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    251359000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    251359000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    250083000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    250083000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    250083000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.002404                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.002404                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.002404                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  8399.071073                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  8399.071073                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  8399.071073                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.002375                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.002375                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.002375                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  8453.033632                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  8453.033632                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  8453.033632                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 157559                       # number of replacements
-system.cpu.dcache.tagsinuse               4075.605702                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 45320510                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 161655                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 280.353283                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              305781000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4075.605702                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.995021                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               26986553                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              18297687                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits            18928                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits             17320                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits                45284240                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               45284240                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               104970                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1552214                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses             31                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses               1657184                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              1657184                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     2340452000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   51751426000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency       435500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency     54091878000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    54091878000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           27091523                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                 157556                       # number of replacements
+system.cpu.dcache.tagsinuse               4075.680070                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 45321004                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 161652                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 280.361542                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              307509000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4075.680070                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.995039                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               26986530                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              18297810                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            19355                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             17297                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                45284340                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               45284340                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               104939                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             1552091                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses             27                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses               1657030                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              1657030                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     2337604500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   51739462000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency       386500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency     54077066500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    54077066500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           27091469                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses          19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses        18959                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses         17320                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            46941424                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           46941424                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.003875                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.078198                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.001635                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.035303                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.035303                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 22296.389445                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33340.393786                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 14048.387097                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 32640.840124                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 32640.840124                       # average overall miss latency
+system.cpu.dcache.LoadLockedReq_accesses        19382                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         17297                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            46941370                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           46941370                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.003874                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.078191                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.001393                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.035300                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.035300                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 22275.841203                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 33335.327632                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 14314.814815                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 32634.935095                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 32634.935095                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       165500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       166000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               9                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 18388.888889                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 18444.444444                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   123328                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits             50205                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1445313                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits           31                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1495518                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1495518                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses           54765                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         106901                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           161666                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          161666                       # number of overall MSHR misses
+system.cpu.dcache.writebacks                   123342                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits             50191                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          1445181                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits           27                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1495372                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1495372                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses           54748                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         106910                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           161658                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          161658                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1030429000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   3652589000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   4683018000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   4683018000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   1029521500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   3652232000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   4681753500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   4681753500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.002021                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.005385                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.005386                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate      0.003444                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate     0.003444                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18815.466082                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34167.959140                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 28967.241102                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 28967.241102                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18804.732593                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34161.743523                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 28960.852541                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 28960.852541                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                114936                       # number of replacements
-system.cpu.l2cache.tagsinuse             18374.970937                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   73734                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                133792                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.551109                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                114899                       # number of replacements
+system.cpu.l2cache.tagsinuse             18376.822812                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   73444                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                133749                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.549118                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          2397.195703                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15977.775235                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.073157                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.487603                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                 51991                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              123328                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits                  4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits                4303                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                  56294                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                 56294                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               32686                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses                7                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses            102588                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               135274                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              135274                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1117376500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   3525779000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     4643155500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    4643155500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses             84677                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          123328                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses             11                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          106891                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             191568                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            191568                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.386008                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate      0.636364                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.959744                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.706141                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.706141                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34185.171021                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.337427                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34324.079276                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34324.079276                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::0          2396.199422                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15980.623390                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.073126                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.487690                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                 51683                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              123342                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits                  2                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits                4309                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                  55992                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                 55992                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               32640                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses                4                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses            102597                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               135237                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              135237                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1115857000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   3525923000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     4641780000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    4641780000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses             84323                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          123342                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses              6                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          106906                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             191229                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            191229                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.387083                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate      0.666667                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.959694                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.707199                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.707199                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34186.795343                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.726123                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34323.299097                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34323.299097                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -499,32 +499,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   88452                       # number of writebacks
+system.cpu.l2cache.writebacks                   88453                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits               81                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits                81                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits               81                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          32605                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses            7                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       102588                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          135193                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         135193                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses          32559                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses            4                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       102597                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          135156                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         135156                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1012653500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency       217000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   3200382500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   4213036000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   4213036000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1011231500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency       124000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   3200947000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   4212178500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   4212178500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.385051                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.636364                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.959744                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.705718                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.705718                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31058.227266                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.386122                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.666667                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.959694                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.706776                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.706776                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31058.432384                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31196.460600                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.122351                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.122351                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31199.226098                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31165.308976                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31165.308976                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index ffc7fc25394583bfaef12a6d282e09848a4e6388..634bd1ef53f6da7f6618a34c8ff6b45732e91a8a 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:00:53
-gem5 started Jul  8 2011 17:16:45
+gem5 compiled Jul 15 2011 17:43:54
+gem5 started Jul 15 2011 19:08:37
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -23,4 +23,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 635013348500 because target called exit()
+Exiting @ tick 630794322500 because target called exit()
index dda3428780814391eb5d0e2af77d5ac73b78a273..612ce5ecb903662947c34e4fbdea961d98b0071b 100644 (file)
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.635013                       # Number of seconds simulated
-sim_ticks                                635013348500                       # Number of ticks simulated
+sim_seconds                                  0.630794                       # Number of seconds simulated
+sim_ticks                                630794322500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  68058                       # Simulator instruction rate (inst/s)
-host_tick_rate                               24894495                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 246392                       # Number of bytes of host memory used
-host_seconds                                 25508.18                       # Real time elapsed on the host
+host_inst_rate                                  76362                       # Simulator instruction rate (inst/s)
+host_tick_rate                               27746395                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 246464                       # Number of bytes of host memory used
+host_seconds                                 22734.28                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    603338361                       # DTB read hits
-system.cpu.dtb.read_misses                   10295627                       # DTB read misses
+system.cpu.dtb.read_hits                    603175408                       # DTB read hits
+system.cpu.dtb.read_misses                   10382155                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                613633988                       # DTB read accesses
-system.cpu.dtb.write_hits                   208599183                       # DTB write hits
-system.cpu.dtb.write_misses                   6680918                       # DTB write misses
+system.cpu.dtb.read_accesses                613557563                       # DTB read accesses
+system.cpu.dtb.write_hits                   207486280                       # DTB write hits
+system.cpu.dtb.write_misses                   6703729                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               215280101                       # DTB write accesses
-system.cpu.dtb.data_hits                    811937544                       # DTB hits
-system.cpu.dtb.data_misses                   16976545                       # DTB misses
+system.cpu.dtb.write_accesses               214190009                       # DTB write accesses
+system.cpu.dtb.data_hits                    810661688                       # DTB hits
+system.cpu.dtb.data_misses                   17085884                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                828914089                       # DTB accesses
-system.cpu.itb.fetch_hits                   391544242                       # ITB hits
-system.cpu.itb.fetch_misses                        36                       # ITB misses
+system.cpu.dtb.data_accesses                827747572                       # DTB accesses
+system.cpu.itb.fetch_hits                   389142997                       # ITB hits
+system.cpu.itb.fetch_misses                        38                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               391544278                       # ITB accesses
+system.cpu.itb.fetch_accesses               389143035                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -41,246 +41,246 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       1270026698                       # number of cpu cycles simulated
+system.cpu.numCycles                       1261588646                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                374312464                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          289169438                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           19496445                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             340941395                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                334345011                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                372091723                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          287344410                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           19482025                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             339026759                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                332564866                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                 24666648                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                1937                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          404704037                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     3147798119                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   374312464                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          359011659                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     616794499                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               137998027                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              125668111                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   27                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.BPredUnit.usedRAS                 24521483                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                1913                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          401603290                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3128927097                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   372091723                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          357086349                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     613258490                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               135586269                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              127041969                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   26                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           951                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 391544242                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               8927962                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1258617999                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.500996                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.012045                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                 389142997                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               9519109                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1250962446                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.501216                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.011577                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                641823500     50.99%     50.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 53319636      4.24%     55.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 35799554      2.84%     58.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 54964384      4.37%     62.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                137079474     10.89%     73.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 75209346      5.98%     79.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 52974044      4.21%     83.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 43807155      3.48%     87.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                163640906     13.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                637703956     50.98%     50.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 53070188      4.24%     55.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 35635977      2.85%     58.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 54551976      4.36%     62.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                136343152     10.90%     73.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 75070366      6.00%     79.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 52403227      4.19%     83.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 43683605      3.49%     87.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                162499999     12.99%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1258617999                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.294728                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.478529                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                434225808                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             112156946                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 585871640                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              14914010                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              111449595                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             58364893                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   867                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3066482661                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  1948                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              111449595                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                456759816                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                64512146                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           4249                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 576631270                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              49260923                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2982899565                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                509098                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                7685931                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              38326944                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2232338965                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3854814610                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3853783957                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1030653                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1250962446                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.294939                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.480148                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                431101199                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             113892603                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 582711633                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              14200214                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              109056797                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             57497676                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  1028                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3047130030                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2024                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              109056797                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                453766318                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                66152638                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           4489                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 572459547                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              49522657                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2962251585                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                509472                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                8488964                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              37728922                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2215831278                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3828352305                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3827339752                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1012553                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                856136002                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                193                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            190                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 103200080                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            676333170                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           252017068                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         107962644                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         56514638                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2687392423                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 179                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2469741583                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1752104                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       940434860                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    416211296                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            150                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1258617999                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.962265                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.926131                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                839628315                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                266                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            263                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 102105357                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            670128900                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           250448120                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          97927277                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         62674140                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2669873432                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 219                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2466087969                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1699054                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       923450677                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    397988094                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            190                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1250962446                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.971353                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.922762                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           411515074     32.70%     32.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           202456949     16.09%     48.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           202249342     16.07%     64.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           156364195     12.42%     77.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           139152023     11.06%     88.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            73667183      5.85%     94.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            48795801      3.88%     98.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            19364904      1.54%     99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             5052528      0.40%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           403537577     32.26%     32.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           206908557     16.54%     48.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           196272095     15.69%     64.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           156883452     12.54%     77.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           140843033     11.26%     88.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            74249795      5.94%     94.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            49611438      3.97%     98.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            17556861      1.40%     99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             5099638      0.41%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1258617999                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1250962446                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 3576452     24.84%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     24.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9406298     65.33%     90.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               1415397      9.83%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 3929936     26.79%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     26.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9164613     62.47%     89.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               1575877     10.74%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1617611726     65.50%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                   92      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 252      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  20      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                 146      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 18      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                  24      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            631548427     25.57%     91.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           220580878      8.93%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1614368204     65.46%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                   93      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 252      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  20      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                 149      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 19      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                  24      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            631861651     25.62%     91.08% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           219857557      8.92%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2469741583                       # Type of FU issued
-system.cpu.iq.rate                           1.944638                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    14398147                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.005830                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         6212471762                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3627257196                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2370962102                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             1779654                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            1040695                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       834376                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2483251910                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  887820                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         52535371                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2466087969                       # Type of FU issued
+system.cpu.iq.rate                           1.954748                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    14670426                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.005949                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6197744460                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3592745886                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2365749940                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             1763404                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            1020600                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       828073                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2479878842                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  879553                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         54119833                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    231737507                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       276679                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       497053                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     91288566                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    225533237                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       274653                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       443666                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     89719618                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads           59                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        156775                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads           53                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        162300                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              111449595                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                23764552                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1337877                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2830649403                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts          12818049                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             676333170                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            252017068                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                179                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 569958                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 21987                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         497053                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       20334660                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      2042240                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             22376900                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2418005225                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             613634241                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          51736358                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles              109056797                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                23925138                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1338311                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2811874535                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts          12833381                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             670128900                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            250448120                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                219                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 545828                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 18223                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         443666                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       20334836                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      2010249                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             22345085                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2412233933                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             613557757                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          53854036                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     143256801                       # number of nop insts executed
-system.cpu.iew.exec_refs                    828914361                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                295415710                       # Number of branches executed
-system.cpu.iew.exec_stores                  215280120                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.903901                       # Inst execution rate
-system.cpu.iew.wb_sent                     2397586638                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2371796478                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1365189773                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1727887810                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     142000884                       # number of nop insts executed
+system.cpu.iew.exec_refs                    827747782                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                295599123                       # Number of branches executed
+system.cpu.iew.exec_stores                  214190025                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.912061                       # Inst execution rate
+system.cpu.iew.wb_sent                     2392748648                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2366578013                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1358866108                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1719778019                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.867517                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.790092                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.875871                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.790140                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts     1819780126                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       780151578                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       759617769                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          19495666                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1147168404                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.586323                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.463059                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          19481102                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1141905649                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.593634                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.464996                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    609653045     53.14%     53.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    194676784     16.97%     70.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     91786029      8.00%     78.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     52706326      4.59%     82.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     37714625      3.29%     86.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     27440530      2.39%     88.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     24523987      2.14%     90.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     21129390      1.84%     92.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     87537688      7.63%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    604531379     52.94%     52.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    194846854     17.06%     70.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     88590760      7.76%     77.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     56412510      4.94%     82.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     37294667      3.27%     85.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     28799723      2.52%     88.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     22448338      1.97%     90.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     21204433      1.86%     92.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     87776985      7.69%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1147168404                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1141905649                       # Number of insts commited each cycle
 system.cpu.commit.count                    1819780126                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      605324165                       # Number of memory references committed
@@ -290,50 +290,50 @@ system.cpu.commit.branches                  214632552                       # Nu
 system.cpu.commit.fp_insts                     805525                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1718967519                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             16767440                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              87537688                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              87776985                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3573783220                       # The number of ROB reads
-system.cpu.rob.rob_writes                  5311487808                       # The number of ROB writes
-system.cpu.timesIdled                          516531                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        11408699                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3547747359                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5268048666                       # The number of ROB writes
+system.cpu.timesIdled                          494946                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        10626200                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1736043781                       # Number of Instructions Simulated
-system.cpu.cpi                               0.731564                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.731564                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.366935                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.366935                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3252607111                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1898786107                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                     15156                       # number of floating regfile reads
+system.cpu.cpi                               0.726703                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.726703                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.376078                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.376078                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3245673408                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1894558271                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                     13236                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                      507                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.icache.replacements                      1                       # number of replacements
-system.cpu.icache.tagsinuse                750.127276                       # Cycle average of tags in use
-system.cpu.icache.total_refs                391542886                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    943                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               415209.847296                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                755.752117                       # Cycle average of tags in use
+system.cpu.icache.total_refs                389141650                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    944                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               412226.324153                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            750.127276                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.366273                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              391542886                       # number of ReadReq hits
-system.cpu.icache.demand_hits               391542886                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              391542886                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1356                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1356                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1356                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       47427000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        47427000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       47427000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          391544242                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           391544242                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          391544242                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0            755.752117                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.369020                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              389141650                       # number of ReadReq hits
+system.cpu.icache.demand_hits               389141650                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              389141650                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1347                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1347                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1347                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       47225000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        47225000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       47225000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          389142997                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           389142997                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          389142997                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000003                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate           0.000003                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate          0.000003                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 34975.663717                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 34975.663717                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 34975.663717                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 35059.391240                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35059.391240                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35059.391240                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -343,169 +343,169 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               413                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                413                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               413                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             943                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              943                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             943                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits               403                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                403                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               403                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             944                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              944                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             944                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     33462000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     33462000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     33462000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     33492000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     33492000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     33492000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35484.623542                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35484.623542                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35484.623542                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35478.813559                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35478.813559                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35478.813559                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                9159383                       # number of replacements
-system.cpu.dcache.tagsinuse               4087.248136                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                696439531                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                9163479                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  76.001651                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             5155151000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4087.248136                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.997863                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              540576764                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             155862765                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits                2                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits               696439529                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              696439529                       # number of overall hits
-system.cpu.dcache.ReadReq_misses             10153388                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             4865737                       # number of WriteReq misses
+system.cpu.dcache.replacements                9159626                       # number of replacements
+system.cpu.dcache.tagsinuse               4087.185824                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                694644975                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                9163722                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  75.803803                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             5155515000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4087.185824                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997848                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              538784960                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             155860012                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits                3                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits               694644972                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              694644972                       # number of overall hits
+system.cpu.dcache.ReadReq_misses             10193496                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             4868490                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses              1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses              15019125                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses             15019125                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency   168572903500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency  135364757471                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses              15061986                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses             15061986                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency   169402977500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency  135886448359                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency        38500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency    303937660971                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency   303937660971                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          550730152                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency    305289425859                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency   305289425859                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          548978456                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses            3                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           711458654                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          711458654                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.018436                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.030273                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.333333                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.021110                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.021110                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 16602.625990                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 27819.990573                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_accesses            4                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           709706958                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          709706958                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.018568                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.030290                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.250000                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.021223                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.021223                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 16618.731935                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 27911.415728                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency        38500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 20236.708928                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 20236.708928                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs    117209937                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets   2148380000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             37031                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           65114                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  3165.184224                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 32994.133366                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency 20268.869315                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 20268.869315                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs    119358733                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets   2148382000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             37827                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           65115                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  3155.384593                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 32993.657375                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  3077410                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits           2875087                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          2980560                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            5855647                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           5855647                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         7278301                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses        1885177                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks                  3077546                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits           2914965                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          2983300                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            5898265                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           5898265                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         7278531                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses        1885190                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          9163478                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         9163478                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses          9163721                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         9163721                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  80739671500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency  38395339625                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  80729480000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  38630501513                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency        35500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 119135011125                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 119135011125                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 119359981513                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 119359981513                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.013216                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.013258                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.011729                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.333333                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.012880                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.012880                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11093.203139                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20366.967996                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.250000                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.012912                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.012912                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11091.452382                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20491.569292                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency        35500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 13001.069149                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 13001.069149                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 13025.274505                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 13025.274505                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements               2693761                       # number of replacements
-system.cpu.l2cache.tagsinuse             26701.570875                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 7632488                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs               2718396                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  2.807717                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          128397458500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0         15961.645382                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         10739.925493                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.487111                       # Average percentage of cache occupancy
+system.cpu.l2cache.replacements               2693791                       # number of replacements
+system.cpu.l2cache.tagsinuse             26705.078667                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7632821                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               2718423                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.807812                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          127919553500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0         15965.123035                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         10739.955632                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.487217                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::1            0.327757                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               5458441                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             3077410                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits             1001668                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                6460109                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               6460109                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses             1820800                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            883513                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses              2704313                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses             2704313                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   62491098500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency  30447807000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency    92938905500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency   92938905500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           7279241                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         3077410                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses         1885181                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            9164422                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           9164422                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.250136                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.468662                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.295088                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.295088                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34320.682392                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34462.205989                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34366.918881                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34366.918881                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs     17342500                       # number of cycles access was blocked
+system.cpu.l2cache.ReadReq_hits               5458638                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             3077546                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits             1001691                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                6460329                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               6460329                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             1820833                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses            883504                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses              2704337                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             2704337                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   62507649000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency  30451140500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    92958789500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   92958789500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           7279471                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         3077546                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses         1885195                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            9164666                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           9164666                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.250133                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.468654                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.295083                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.295083                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34329.149900                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34466.330090                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34373.966521                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34373.966521                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs     17593500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs             1668                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs             1703                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10397.182254                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10330.886671                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                 1171800                       # number of writebacks
+system.cpu.l2cache.writebacks                 1171811                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses        1820800                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       883513                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses         2704313                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses        2704313                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses        1820833                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       883504                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         2704337                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        2704337                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  56720900500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  27626952000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  84347852500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  84347852500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency  56722118000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency  27628606500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  84350724500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  84350724500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250136                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.468662                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.295088                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.295088                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31151.636918                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31269.434632                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31190.122038                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31190.122038                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250133                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.468654                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.295083                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.295083                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31151.740989                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31271.625822                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31190.907235                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31190.907235                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index fe3177229c83f65c499a38a4a9b723fd9c1e1ceb..30a5002e0e1a3dbbc8794db51cefa020eec12795 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:18:43
-gem5 started Jul  9 2011 03:49:53
+gem5 compiled Jul 15 2011 18:02:03
+gem5 started Jul 16 2011 03:24:30
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -24,4 +24,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 524441606000 because target called exit()
+Exiting @ tick 520816837000 because target called exit()
index f09bdc94a8631d02a33b4f7782c378934dce50ee..efe6a8ef11cd48ca3e857a7063a1a19278d2f58e 100644 (file)
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.524442                       # Number of seconds simulated
-sim_ticks                                524441606000                       # Number of ticks simulated
+sim_seconds                                  0.520817                       # Number of seconds simulated
+sim_ticks                                520816837000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 101251                       # Simulator instruction rate (inst/s)
-host_tick_rate                               30817067                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 257952                       # Number of bytes of host memory used
-host_seconds                                 17017.90                       # Real time elapsed on the host
-sim_insts                                  1723073904                       # Number of instructions simulated
+host_inst_rate                                 106291                       # Simulator instruction rate (inst/s)
+host_tick_rate                               32127421                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257992                       # Number of bytes of host memory used
+host_seconds                                 16210.98                       # Real time elapsed on the host
+sim_insts                                  1723073899                       # Number of instructions simulated
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -51,300 +51,300 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       1048883213                       # number of cpu cycles simulated
+system.cpu.numCycles                       1041633675                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                317450426                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          259852467                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           18436703                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             279904663                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                254677721                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                316759816                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          259210728                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           18340703                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             279172110                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                252354125                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                 20220648                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                4428                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          315501768                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2280935015                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   317450426                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          274898369                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     509081814                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               103935328                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              124227879                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                    9                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           270                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 303015456                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6379891                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1031116877                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.459992                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.013809                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                 20423833                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                3592                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          314505496                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2269650018                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   316759816                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          272777958                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     507209823                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               102718581                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              118023116                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   13                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           378                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 301735103                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6341301                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1020560450                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.475963                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.020968                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                522035116     50.63%     50.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 37818104      3.67%     54.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 65533745      6.36%     60.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 69512456      6.74%     67.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 53414736      5.18%     72.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 61047606      5.92%     78.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 57075579      5.54%     84.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 19670108      1.91%     85.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                145009427     14.06%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                513350682     50.30%     50.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 37274170      3.65%     53.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 66826624      6.55%     60.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 71750061      7.03%     67.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 48900197      4.79%     72.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 61148306      5.99%     78.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 56009489      5.49%     83.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 19114722      1.87%     85.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                146186199     14.32%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1031116877                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.302656                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.174632                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                346461175                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             106173290                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 477865699                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              18312225                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               82304488                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             48528259                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   664                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             2473135818                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  2289                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               82304488                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                368931509                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                50902781                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          20077                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 472181274                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              56776748                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2411760057                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 18939                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                5901279                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              44092765                       # Number of times rename has blocked due to LSQ full
+system.cpu.fetch.rateDist::total           1020560450                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.304099                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.178933                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                345277471                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             100386253                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 476244724                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              17831036                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               80820966                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             48621536                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   684                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             2461002046                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2293                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               80820966                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                367852317                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                46560982                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          20161                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 470070702                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              55235322                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2399093241                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 19112                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                7084037                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              41612105                       # Number of times rename has blocked due to LSQ full
 system.cpu.rename.FullRegisterEvents                5                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          2386823429                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups           11134835710                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups      11134834246                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              1464                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1706320039                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                680503385                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                855                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            848                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 119214990                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            651763451                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           230362141                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         123114303                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        108844207                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2285934828                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 851                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2067906375                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3040241                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       557691684                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1352307582                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            383                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1031116877                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.005501                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.810247                       # Number of insts issued each cycle
+system.cpu.rename.RenamedOperands          2375633121                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups           11077295262                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups      11077294016                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              1246                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1706320031                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                669313040                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                859                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            852                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 115610874                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            649413230                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           228367203                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         119305836                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        109745450                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2270974746                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 855                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2053846795                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           4950214                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       542412841                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1352419496                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            388                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1020560450                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.012470                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.816171                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           302093175     29.30%     29.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           161453829     15.66%     44.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           185974655     18.04%     62.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           152722281     14.81%     77.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           122859599     11.92%     89.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            63855935      6.19%     95.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            30343304      2.94%     98.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            10954294      1.06%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              859805      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           295638482     28.97%     28.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           162908535     15.96%     44.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           186570916     18.28%     63.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           146485651     14.35%     77.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           124092307     12.16%     89.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            60745284      5.95%     95.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            32474390      3.18%     98.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             9761593      0.96%     99.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1883292      0.18%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1031116877                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1020560450                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  735734      3.76%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                    145      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               17865428     91.35%     95.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                956298      4.89%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1886665      8.33%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                    129      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               20021118     88.41%     96.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                736661      3.25%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1267972738     61.32%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              1165735      0.06%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               9      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              9      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            605808033     29.30%     90.67% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           192959848      9.33%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1258507909     61.28%     61.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              1049624      0.05%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               6      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            601998559     29.31%     90.64% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           192290687      9.36%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2067906375                       # Type of FU issued
-system.cpu.iq.rate                           1.971532                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    19557605                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.009458                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5189527225                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2846700346                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1993811028                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 248                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                266                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          105                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2087463854                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     126                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         48700640                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2053846795                       # Type of FU issued
+system.cpu.iq.rate                           1.971755                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22644573                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.011025                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5155848613                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2816902201                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1979021508                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 207                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                208                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           87                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2076491261                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     107                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         49405456                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    165836668                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       182984                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation      3082033                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     55515084                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    163486436                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       194823                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation      3514757                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     53520135                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads            3                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        451401                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads            2                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        451218                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               82304488                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                22549936                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1320929                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2286019853                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           6521602                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             651763451                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            230362141                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                777                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 333118                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 65136                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents        3082033                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       18892989                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      1847041                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             20740030                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2026288483                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             583345448                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          41617892                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               80820966                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                21846614                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1532145                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2271045706                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           6454862                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             649413230                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            228367203                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                782                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 463327                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 64846                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents        3514757                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       18903388                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      1825622                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             20729010                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2013025353                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             580460904                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          40821435                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         84174                       # number of nop insts executed
-system.cpu.iew.exec_refs                    773137523                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                241378100                       # Number of branches executed
-system.cpu.iew.exec_stores                  189792075                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.931853                       # Inst execution rate
-system.cpu.iew.wb_sent                     2004592772                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1993811133                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1313765556                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2094642495                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         70105                       # number of nop insts executed
+system.cpu.iew.exec_refs                    769390557                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                240046376                       # Number of branches executed
+system.cpu.iew.exec_stores                  188929653                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.932566                       # Inst execution rate
+system.cpu.iew.wb_sent                     1991598100                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1979021595                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1304894020                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2076228305                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.900890                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.627203                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.899921                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.628493                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts     1723073922                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       563083903                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls             468                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          18443845                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    948812390                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.816032                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.570732                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts     1723073917                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       548129621                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls             467                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          18348258                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    939739485                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.833566                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.580985                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    421119309     44.38%     44.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    219659546     23.15%     67.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     84920332      8.95%     76.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     40130029      4.23%     80.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     24924955      2.63%     83.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     30334777      3.20%     86.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     23612661      2.49%     89.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     12752294      1.34%     90.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     91358487      9.63%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    417784524     44.46%     44.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    209332361     22.28%     66.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     89117008      9.48%     76.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     41409082      4.41%     80.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     23428101      2.49%     83.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     30586895      3.25%     86.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     22243111      2.37%     88.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     15532475      1.65%     90.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     90305928      9.61%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    948812390                       # Number of insts commited each cycle
-system.cpu.commit.count                    1723073922                       # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total    939739485                       # Number of insts commited each cycle
+system.cpu.commit.count                    1723073917                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      660773839                       # Number of memory references committed
-system.cpu.commit.loads                     485926782                       # Number of loads committed
+system.cpu.commit.refs                      660773837                       # Number of memory references committed
+system.cpu.commit.loads                     485926781                       # Number of loads committed
 system.cpu.commit.membars                          62                       # Number of memory barriers committed
-system.cpu.commit.branches                  213462376                       # Number of branches committed
+system.cpu.commit.branches                  213462375                       # Number of branches committed
 system.cpu.commit.fp_insts                         36                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                1536941897                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                1536941893                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             13665177                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              91358487                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              90305928                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3143611129                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4654874733                       # The number of ROB writes
-system.cpu.timesIdled                          997575                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        17766336                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                  1723073904                       # Number of Instructions Simulated
-system.cpu.committedInsts_total            1723073904                       # Number of Instructions Simulated
-system.cpu.cpi                               0.608728                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.608728                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.642770                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.642770                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads              10134733413                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1980533280                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        92                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       35                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              3028358925                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                    148                       # number of misc regfile writes
-system.cpu.icache.replacements                      9                       # number of replacements
-system.cpu.icache.tagsinuse                611.010403                       # Cycle average of tags in use
-system.cpu.icache.total_refs                303014437                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    739                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               410033.067659                       # Average number of references to valid blocks.
+system.cpu.rob.rob_reads                   3120636496                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4623496698                       # The number of ROB writes
+system.cpu.timesIdled                          989897                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        21073225                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1723073899                       # Number of Instructions Simulated
+system.cpu.committedInsts_total            1723073899                       # Number of Instructions Simulated
+system.cpu.cpi                               0.604521                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.604521                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.654203                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.654203                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads              10072525015                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1968285521                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        75                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       31                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              3013509835                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                    146                       # number of misc regfile writes
+system.cpu.icache.replacements                     13                       # number of replacements
+system.cpu.icache.tagsinuse                614.807125                       # Cycle average of tags in use
+system.cpu.icache.total_refs                301734075                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    749                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               402849.232310                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            611.010403                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.298345                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              303014437                       # number of ReadReq hits
-system.cpu.icache.demand_hits               303014437                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              303014437                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1019                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1019                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1019                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       35224000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        35224000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       35224000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          303015456                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           303015456                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          303015456                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0            614.807125                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.300199                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              301734075                       # number of ReadReq hits
+system.cpu.icache.demand_hits               301734075                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              301734075                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1028                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1028                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1028                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       35478500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        35478500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       35478500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          301735103                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           301735103                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          301735103                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000003                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate           0.000003                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate          0.000003                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 34567.222767                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 34567.222767                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 34567.222767                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 34512.159533                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 34512.159533                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 34512.159533                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -354,169 +354,176 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               280                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                280                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               280                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             739                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              739                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             739                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits               277                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                277                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               277                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             751                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              751                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             751                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     25462500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     25462500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     25462500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     25803000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     25803000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     25803000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34455.345061                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34455.345061                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34455.345061                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34358.189081                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34358.189081                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34358.189081                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                9572098                       # number of replacements
-system.cpu.dcache.tagsinuse               4088.159469                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                687277052                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                9576194                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  71.769333                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             3603059000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4088.159469                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.998086                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              519599165                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             167677732                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits               82                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits                73                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits               687276897                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              687276897                       # number of overall hits
-system.cpu.dcache.ReadReq_misses             10430920                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             4908315                       # number of WriteReq misses
+system.cpu.dcache.replacements                9571252                       # number of replacements
+system.cpu.dcache.tagsinuse               4088.168167                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                683613233                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                9575348                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  71.393043                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             3571196000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4088.168167                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.998088                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              515943773                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             167669303                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits               81                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits                72                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits               683613076                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              683613076                       # number of overall hits
+system.cpu.dcache.ReadReq_misses             10432910                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses             4916744                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses              3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses              15339235                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses             15339235                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency   181621482000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency  122280886057                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses              15349654                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses             15349654                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency   181536100500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency  122414115127                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency       113500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency    303902368057                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency   303902368057                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          530030085                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency    303950215627                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency   303950215627                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          526376683                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses         172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses           85                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses            73                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           702616132                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          702616132                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.019680                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.028440                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.035294                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.021832                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.021832                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 17411.837307                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 24913.007021                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_accesses           84                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses            72                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses           698962730                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          698962730                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.019820                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.028489                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.035714                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.021961                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.021961                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 17400.332266                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 24897.394521                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 19812.094153                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 19812.094153                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs    267003640                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       196000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             90682                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               9                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  2944.395139                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 21777.777778                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency 19801.763325                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 19801.763325                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs    267203110                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       176500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             90930                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               8                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  2938.558342                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 22062.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  3128448                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits           2747497                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          3015544                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks                  3128377                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits           2750280                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits          3024025                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            5763041                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           5763041                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         7683423                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses        1892771                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          9576194                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         9576194                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_hits            5774305                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           5774305                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         7682630                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses        1892719                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          9575349                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         9575349                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  90753159500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency  45245223293                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 135998382793                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 135998382793                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  90548331000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  45239706866                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 135788037866                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 135788037866                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.014496                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.014595                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.010967                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.013629                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.013629                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11811.553197                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23904.224702                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 14201.715503                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 14201.715503                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate      0.013699                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.013699                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11786.111136                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23901.966888                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 14181.001430                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 14181.001430                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements               2927988                       # number of replacements
-system.cpu.l2cache.tagsinuse             26803.816569                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 7852126                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs               2955312                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  2.656953                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          105427800500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0         15979.704689                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         10824.111881                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.487662                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.330326                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               5656220                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             3128448                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              980310                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                6636530                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               6636530                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses             2027940                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            912463                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses              2940403                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses             2940403                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   69613457000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency  31659273500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency   101272730500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency  101272730500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           7684160                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         3128448                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses         1892773                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            9576933                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           9576933                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.263912                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.482077                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.307030                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.307030                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34327.177826                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34696.501118                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34441.785871                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34441.785871                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs     56425500                       # number of cycles access was blocked
+system.cpu.l2cache.replacements               2927724                       # number of replacements
+system.cpu.l2cache.tagsinuse             26806.292865                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 7851539                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               2955046                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.656994                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          103976307500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0         15984.419596                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         10821.873269                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.487806                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.330257                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               5655745                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             3128377                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              980223                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                6635968                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               6635968                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses             2027633                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses            912497                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses              2940130                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses             2940130                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   69565462000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency  31656932500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency   101222394500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency  101222394500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           7683378                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         3128377                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses         1892720                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            9576098                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           9576098                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.263899                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.482109                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.307028                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.307028                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34308.704780                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34692.642825                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34427.863564                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34427.863564                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs     56270500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs             6606                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs             6598                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  8541.553134                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  8528.417702                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                 1217599                       # number of writebacks
+system.cpu.l2cache.writebacks                 1217507                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits               12                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits                12                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits               12                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses        2027928                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       912463                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses         2940391                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses        2940391                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses        2027621                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       912497                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses         2940118                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses        2940118                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  63193895000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  28814819500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  92008714500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  92008714500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency  63172977500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency        32000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency  28814369500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  91987347000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  91987347000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.263910                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.482077                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.307028                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.307028                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31161.804068                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31579.164854                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31291.319590                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31291.319590                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.263897                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.482109                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.307027                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.307027                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31156.205967                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        32000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31577.495049                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31286.957530                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31286.957530                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index ba1de823895ce91aba472048401f02afa1dc70c4..cae861e0e9ac57ebc1a89a44a5799a5d11913cb7 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:00:53
-gem5 started Jul  8 2011 18:07:05
+gem5 compiled Jul 15 2011 17:43:54
+gem5 started Jul 15 2011 19:50:53
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
 Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav
@@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 32092296500 because target called exit()
+122 123 124 Exiting @ tick 33574995000 because target called exit()
index 5aa0ca1ff8c9489d85ef4e4dc05c2c9ce9f55135..9b4ccbc947464cb949d070cb74c426c51efcf265 100644 (file)
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.032092                       # Number of seconds simulated
-sim_ticks                                 32092296500                       # Number of ticks simulated
+sim_seconds                                  0.033575                       # Number of seconds simulated
+sim_ticks                                 33574995000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  73581                       # Simulator instruction rate (inst/s)
-host_tick_rate                               28051508                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 250560                       # Number of bytes of host memory used
-host_seconds                                  1144.05                       # Real time elapsed on the host
+host_inst_rate                                  75399                       # Simulator instruction rate (inst/s)
+host_tick_rate                               30072740                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 250632                       # Number of bytes of host memory used
+host_seconds                                  1116.46                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     25665074                       # DTB read hits
-system.cpu.dtb.read_misses                     532377                       # DTB read misses
+system.cpu.dtb.read_hits                     25910068                       # DTB read hits
+system.cpu.dtb.read_misses                     487884                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 26197451                       # DTB read accesses
-system.cpu.dtb.write_hits                     7413229                       # DTB write hits
-system.cpu.dtb.write_misses                      1159                       # DTB write misses
-system.cpu.dtb.write_acv                            5                       # DTB write access violations
-system.cpu.dtb.write_accesses                 7414388                       # DTB write accesses
-system.cpu.dtb.data_hits                     33078303                       # DTB hits
-system.cpu.dtb.data_misses                     533536                       # DTB misses
-system.cpu.dtb.data_acv                             5                       # DTB access violations
-system.cpu.dtb.data_accesses                 33611839                       # DTB accesses
-system.cpu.itb.fetch_hits                    19743768                       # ITB hits
-system.cpu.itb.fetch_misses                        86                       # ITB misses
+system.cpu.dtb.read_accesses                 26397952                       # DTB read accesses
+system.cpu.dtb.write_hits                     7442430                       # DTB write hits
+system.cpu.dtb.write_misses                       947                       # DTB write misses
+system.cpu.dtb.write_acv                            1                       # DTB write access violations
+system.cpu.dtb.write_accesses                 7443377                       # DTB write accesses
+system.cpu.dtb.data_hits                     33352498                       # DTB hits
+system.cpu.dtb.data_misses                     488831                       # DTB misses
+system.cpu.dtb.data_acv                             1                       # DTB access violations
+system.cpu.dtb.data_accesses                 33841329                       # DTB accesses
+system.cpu.itb.fetch_hits                    20391081                       # ITB hits
+system.cpu.itb.fetch_misses                        82                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                19743854                       # ITB accesses
+system.cpu.itb.fetch_accesses                20391163                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -41,246 +41,246 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                         64184594                       # number of cpu cycles simulated
+system.cpu.numCycles                         67149991                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 19638238                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           14616795                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1934317                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              16315844                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 12540710                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 20043424                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           14890335                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1886616                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              16546187                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 12995160                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  1821712                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                2747                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           21008427                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      166538758                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    19638238                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           14362422                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      30824536                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 9451370                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                4886757                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   49                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1819                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  19743768                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                631936                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           64091521                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.598452                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.236190                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                  1876944                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                2472                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           21676746                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      172437485                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    20043424                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           14872104                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      31892042                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                10307497                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                5295116                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   48                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1817                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  20391081                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                650323                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           67056836                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.571512                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.236226                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 33266985     51.91%     51.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3147764      4.91%     56.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2102748      3.28%     60.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  3556460      5.55%     65.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4397921      6.86%     72.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1522590      2.38%     74.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1866548      2.91%     77.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1731844      2.70%     80.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 12498661     19.50%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 35164794     52.44%     52.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3176485      4.74%     57.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2538345      3.79%     60.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  3535941      5.27%     66.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4282691      6.39%     72.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1574198      2.35%     74.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1997484      2.98%     77.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1705355      2.54%     80.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 13081543     19.51%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             64091521                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.305965                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.594684                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 23134324                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               3873003                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  28813163                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                914553                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                7356478                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3062607                       # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total             67056836                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.298487                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.567945                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 23902898                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               4218142                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  29787412                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                970752                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                8177632                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3156419                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                 13804                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              160619110                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 43067                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                7356478                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 24847542                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 1029661                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           6037                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  27972484                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               2879319                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              153930695                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     5                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 698435                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               1852837                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           113010867                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             199187244                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        187702425                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          11484819                       # Number of floating rename lookups
+system.cpu.decode.DecodedInsts              166261756                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 43031                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                8177632                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 25731687                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 1160543                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           6023                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  28902105                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               3078846                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              159343297                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     6                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 846266                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               1904805                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           117303281                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             206166674                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        193984489                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          12182185                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              68427361                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 44583506                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                529                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            520                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   7678386                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             31845410                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             9896316                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           6196134                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1567027                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  129169470                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 502                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 107327436                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            534587                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        44082208                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     35410789                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            113                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      64091521                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.674596                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.788065                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 48875920                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                523                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            516                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   8753950                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             33541628                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10395963                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           7223070                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2102878                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  134779237                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 499                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 107642256                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            461690                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        49489496                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     42823427                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            110                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      67056836                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.605239                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.754849                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            23013905     35.91%     35.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            13200417     20.60%     56.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             9655349     15.06%     71.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7236543     11.29%     82.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             5456935      8.51%     91.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2848092      4.44%     95.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1848148      2.88%     98.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              707452      1.10%     99.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              124680      0.19%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            24956395     37.22%     37.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14036514     20.93%     58.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            10136000     15.12%     73.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7177120     10.70%     83.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             5400162      8.05%     92.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2788229      4.16%     96.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1798139      2.68%     98.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              642461      0.96%     99.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              121816      0.18%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        64091521                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        67056836                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  206408     12.63%     12.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     12.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     12.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                   196      0.01%     12.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     12.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                  6500      0.40%     13.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                 5851      0.36%     13.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                847321     51.84%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     65.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 476077     29.13%     94.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                 91992      5.63%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  201993     12.31%     12.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     12.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     12.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                   250      0.02%     12.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     12.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                  6175      0.38%     12.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                 5518      0.34%     13.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                850319     51.81%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 486670     29.65%     94.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                 90238      5.50%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 7      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              65553727     61.08%     61.08% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               486899      0.45%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             2819079      2.63%     64.16% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp              115045      0.11%     64.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2427572      2.26%     66.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult             312395      0.29%     66.82% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv              763362      0.71%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.53% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             27299077     25.44%     92.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             7549954      7.03%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              65718321     61.05%     61.05% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               491419      0.46%     61.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2837753      2.64%     64.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp              114927      0.11%     64.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2460943      2.29%     66.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult             308030      0.29%     66.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv              776022      0.72%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                318      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.55% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             27323056     25.38%     92.93% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             7611460      7.07%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              107327436                       # Type of FU issued
-system.cpu.iq.rate                           1.672168                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1634345                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.015228                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          265519684                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         162160015                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     94997457                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            15395641                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           11288937                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      7141397                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              100830916                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 8130858                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1254132                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              107642256                       # Type of FU issued
+system.cpu.iq.rate                           1.603012                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1641163                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.015246                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          268833280                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         171996090                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     95630473                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            15610921                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           12638151                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      7243335                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              101046338                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 8237074                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1306070                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     11849212                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         9154                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       349266                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      3395213                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     13545430                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         9202                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       431066                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      3894860                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        10688                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads        10948                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             1                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                7356478                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                   94659                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 31189                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           141503695                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            872227                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              31845410                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              9896316                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                502                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  12366                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    32                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         349266                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1814664                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       342809                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              2157473                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             104568587                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              26198042                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2758849                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                8177632                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  205335                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                131722                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           147421220                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            680146                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              33541628                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10395963                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                498                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  98656                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    38                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         431066                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1771181                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       338775                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              2109956                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             105130467                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              26398523                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2511789                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      12333723                       # number of nop insts executed
-system.cpu.iew.exec_refs                     33612538                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 13292388                       # Number of branches executed
-system.cpu.iew.exec_stores                    7414496                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.629185                       # Inst execution rate
-system.cpu.iew.wb_sent                      103278074                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     102138854                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  68941212                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95281048                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      12641484                       # number of nop insts executed
+system.cpu.iew.exec_refs                     33841971                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 13292827                       # Number of branches executed
+system.cpu.iew.exec_stores                    7443448                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.565607                       # Inst execution rate
+system.cpu.iew.wb_sent                      103975635                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     102873808                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  69418102                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  96250402                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.591330                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.723556                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.532000                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.721224                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts       91903055                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        49602328                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        55519927                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1920862                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     56735043                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.619864                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.379821                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1873181                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     58879204                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.560875                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.342568                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     26448220     46.62%     46.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     12595125     22.20%     68.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      5584191      9.84%     78.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2979320      5.25%     83.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1760489      3.10%     87.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1489209      2.62%     89.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       769969      1.36%     91.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       774387      1.36%     92.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      4334133      7.64%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     27960283     47.49%     47.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     13480171     22.89%     70.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      5538232      9.41%     79.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2736120      4.65%     84.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1795830      3.05%     87.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1555437      2.64%     90.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       775440      1.32%     91.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       776613      1.32%     92.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4261078      7.24%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     56735043                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     58879204                       # Number of insts commited each cycle
 system.cpu.commit.count                      91903055                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       26497301                       # Number of memory references committed
@@ -290,50 +290,50 @@ system.cpu.commit.branches                   10240685                       # Nu
 system.cpu.commit.fp_insts                    6862061                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                  79581076                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1029620                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               4334133                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               4261078                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    193905253                       # The number of ROB reads
-system.cpu.rob.rob_writes                   290432006                       # The number of ROB writes
-system.cpu.timesIdled                            2283                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           93073                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    202040068                       # The number of ROB reads
+system.cpu.rob.rob_writes                   303073761                       # The number of ROB writes
+system.cpu.timesIdled                            2271                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           93155                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
 system.cpu.committedInsts_total              84179709                       # Number of Instructions Simulated
-system.cpu.cpi                               0.762471                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.762471                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.311525                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.311525                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                141097992                       # number of integer regfile reads
-system.cpu.int_regfile_writes                77269821                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   6208793                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  6125599                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                  715479                       # number of misc regfile reads
+system.cpu.cpi                               0.797698                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.797698                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.253607                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.253607                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                141776374                       # number of integer regfile reads
+system.cpu.int_regfile_writes                77917804                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   6238511                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  6227605                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                  722508                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.icache.replacements                   8662                       # number of replacements
-system.cpu.icache.tagsinuse               1591.987817                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 19731988                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  10590                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                1863.266100                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                   8679                       # number of replacements
+system.cpu.icache.tagsinuse               1593.583704                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 20379337                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  10611                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                1920.585901                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1591.987817                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.777338                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               19731988                       # number of ReadReq hits
-system.cpu.icache.demand_hits                19731988                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               19731988                       # number of overall hits
-system.cpu.icache.ReadReq_misses                11780                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 11780                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                11780                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      187835000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       187835000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      187835000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           19743768                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            19743768                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           19743768                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000597                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000597                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000597                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 15945.246180                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 15945.246180                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 15945.246180                       # average overall miss latency
+system.cpu.icache.occ_blocks::0           1593.583704                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.778117                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               20379337                       # number of ReadReq hits
+system.cpu.icache.demand_hits                20379337                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               20379337                       # number of overall hits
+system.cpu.icache.ReadReq_misses                11744                       # number of ReadReq misses
+system.cpu.icache.demand_misses                 11744                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                11744                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      187534500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       187534500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      187534500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           20391081                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            20391081                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           20391081                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000576                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000576                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000576                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 15968.537125                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 15968.537125                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 15968.537125                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -343,65 +343,65 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              1190                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               1190                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              1190                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           10590                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            10590                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           10590                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits              1133                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               1133                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              1133                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses           10611                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses            10611                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses           10611                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    124617500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    124617500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    124617500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    124781500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    124781500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    124781500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000536                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000536                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000536                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11767.469311                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11767.469311                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11767.469311                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000520                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000520                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000520                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11759.636227                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11759.636227                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11759.636227                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                    159                       # number of replacements
-system.cpu.dcache.tagsinuse               1458.064990                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 30892362                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                   2241                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               13785.078983                       # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse               1459.306327                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 31085202                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   2242                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               13864.942908                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           1458.064990                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.355973                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               24399260                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits               6493052                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits               50                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits                30892312                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               30892312                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  942                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                8051                       # number of WriteReq misses
+system.cpu.dcache.occ_blocks::0           1459.306327                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.356276                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               24592075                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits               6493081                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits               46                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits                31085156                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               31085156                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  927                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                8022                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses              1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses                  8993                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 8993                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       28111000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency     289250500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses                  8949                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 8949                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       28002000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     288506000                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency        38000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency       317361500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      317361500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           24400202                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency       316508000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      316508000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           24593002                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses           51                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            30901305                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           30901305                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000039                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.001238                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.019608                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.000291                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000291                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 29841.825902                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 35927.276115                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_accesses           47                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            31094105                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           31094105                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000038                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.001234                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.021277                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.000288                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000288                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 30207.119741                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 35964.348043                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency        38000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 35289.836540                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 35289.836540                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency 35367.974075                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 35367.974075                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs         2500                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
@@ -411,72 +411,72 @@ system.cpu.dcache.avg_blocked_cycles::no_targets     no_value
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks                      108                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits               435                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits             6318                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits               6753                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits              6753                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             507                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           1733                       # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits               418                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits             6290                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits               6708                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits              6708                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             509                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1732                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             2240                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            2240                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses             2241                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            2241                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     16260000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency     61635000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency     16310000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     61526000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency        35000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency     77895000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency     77895000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     77836000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     77836000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000021                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000267                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.019608                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000266                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.021277                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_mshr_miss_rate      0.000072                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate     0.000072                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32071.005917                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35565.493364                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32043.222004                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35523.094688                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency        35000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 34774.553571                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 34774.553571                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34732.708612                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34732.708612                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              2392.328540                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    7626                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                  3548                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  2.149380                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              2396.251917                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    7647                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3552                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.152872                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          2374.739172                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1            17.589369                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.072471                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2378.668231                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1            17.583686                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.072591                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::1            0.000537                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                  7618                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits                  7636                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits                 108                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                  26                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                   7644                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                  7644                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                3480                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses              1707                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 5187                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                5187                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     119535500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency     59266000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      178801500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     178801500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses             11098                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_hits                  25                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                   7661                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  7661                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                3484                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses              1708                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 5192                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                5192                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     119676500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     59253000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      178929500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     178929500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses             11120                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses             108                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses            1733                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses              12831                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses             12831                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.313570                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.984997                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.404255                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.404255                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34349.281609                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34719.390744                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34471.081550                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34471.081550                       # average overall miss latency
+system.cpu.l2cache.demand_accesses              12853                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses             12853                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.313309                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.985574                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.403952                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.403952                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34350.315729                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34691.451991                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34462.538521                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34462.538521                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -488,24 +488,24 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           3480                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         1707                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            5187                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           5187                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses           3484                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1708                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            5192                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           5192                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    108240500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     53874500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    162115000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    162115000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency    108359500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     53860000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    162219500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    162219500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.313570                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.984997                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.404255                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.404255                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.591954                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31560.925600                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31254.096780                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31254.096780                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.313309                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.985574                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.403952                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.403952                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31102.037887                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31533.957845                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31244.125578                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31244.125578                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index b0302ff58d565330267f9d157c94664b57249c44..e55be2152fb0c0862802fd68329403fc5a902fdc 100755 (executable)
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:18:43
-gem5 started Jul  9 2011 04:18:32
+gem5 compiled Jul 15 2011 18:02:03
+gem5 started Jul 16 2011 04:01:57
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sav
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -21,4 +23,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 110281184000 because target called exit()
+122 123 124 Exiting @ tick 109591303500 because target called exit()
index 0fe4beed8e9fb71320b9801f5e7617c5a164d1cd..9acd1c20e5f3c4b8e4df3a28a722ddf647ee3208 100644 (file)
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.110281                       # Number of seconds simulated
-sim_ticks                                110281184000                       # Number of ticks simulated
+sim_seconds                                  0.109591                       # Number of seconds simulated
+sim_ticks                                109591303500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  65382                       # Simulator instruction rate (inst/s)
-host_tick_rate                               38217412                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 261804                       # Number of bytes of host memory used
-host_seconds                                  2885.63                       # Real time elapsed on the host
-sim_insts                                   188667677                       # Number of instructions simulated
+host_inst_rate                                  60659                       # Simulator instruction rate (inst/s)
+host_tick_rate                               35235152                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 261736                       # Number of bytes of host memory used
+host_seconds                                  3110.28                       # Real time elapsed on the host
+sim_insts                                   188667697                       # Number of instructions simulated
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -51,299 +51,299 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        220562369                       # number of cpu cycles simulated
+system.cpu.numCycles                        219182608                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                104258409                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           82362571                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            9936095                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              86105898                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 80445450                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                103745786                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           81976338                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            9943224                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              85671159                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 80219991                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  4758962                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect              112969                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           46358647                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      433367935                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   104258409                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           85204412                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     111822484                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                35665794                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               36992864                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   15                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           834                       # Number of stall cycles due to pending traps
+system.cpu.BPredUnit.usedRAS                  4756853                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect              113204                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           46114245                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      429912188                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   103745786                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           84976844                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     111330567                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                35270728                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               36699969                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   16                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           813                       # Number of stall cycles due to pending traps
 system.cpu.fetch.PendingQuiesceStallCycles            1                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.CacheLines                  42110119                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2232853                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          220504638                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.132131                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.672325                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  41935754                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2246100                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          219124425                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.128247                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.665143                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                108888253     49.38%     49.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4953673      2.25%     51.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 33070296     15.00%     66.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 18447401      8.37%     74.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  9377183      4.25%     79.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 12785261      5.80%     85.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  8550568      3.88%     88.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  4486115      2.03%     90.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 19945888      9.05%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                108000297     49.29%     49.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  5031394      2.30%     51.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 33002073     15.06%     66.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 18529573      8.46%     75.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  9301462      4.24%     79.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 12648515      5.77%     85.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  8577033      3.91%     89.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4456570      2.03%     91.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 19577508      8.93%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            220504638                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.472694                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.964832                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 55339748                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              35376598                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 103212898                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1403307                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               25172087                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             14322485                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                170339                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              440125451                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                696276                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               25172087                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 64672455                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                  776963                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       29575154                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  95204893                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               5103086                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              403993606                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                  69868                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               2710880                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           687477122                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1728388844                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1709997227                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          18391617                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             298062016                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                389415097                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2865354                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2816189                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  26097925                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             51690689                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            18730866                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           8573671                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          5359744                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  346939727                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2374386                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 267717167                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            907172                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       158256505                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    384971202                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         738758                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     220504638                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.214111                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.476414                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            219124425                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.473330                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.961434                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 55048245                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              35099276                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 102750817                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1404892                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               24821195                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             14312217                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                170214                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              436500086                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                694588                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               24821195                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 64323611                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                  816730                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       29228849                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  94788839                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               5145201                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              401098755                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                  70910                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               2783871                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           682579390                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1716423376                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1698124875                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          18298501                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             298062048                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                384517342                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2790601                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2741243                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  25505966                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             51358732                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            18498661                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           9149940                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          5397480                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  344257456                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2323720                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 266454796                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            912087                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       155278627                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    378105702                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         688088                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     219124425                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.215998                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.473523                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           103384796     46.89%     46.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            39397520     17.87%     64.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            35187917     15.96%     80.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            23179085     10.51%     91.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            11803879      5.35%     96.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4771097      2.16%     98.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2229685      1.01%     99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              447825      0.20%     99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              102834      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           102187705     46.63%     46.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            39549888     18.05%     64.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            35231696     16.08%     80.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            23077585     10.53%     91.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            11566082      5.28%     96.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4775373      2.18%     98.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2189017      1.00%     99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              443166      0.20%     99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              103913      0.05%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       220504638                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       219124425                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  341650     17.75%     17.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   6050      0.31%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                35      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 4      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc               93      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1226198     63.72%     81.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                350464     18.21%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  343002     18.52%     18.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   6054      0.33%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                31      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 2      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc               95      0.01%     18.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1162999     62.81%     81.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                339535     18.34%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             208615296     77.92%     77.92% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               925342      0.35%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                 6202      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.27% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd           33026      0.01%     78.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp          166299      0.06%     78.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt          260522      0.10%     78.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv           76108      0.03%     78.47% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         471200      0.18%     78.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult         207528      0.08%     78.73% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc        71629      0.03%     78.75% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt            327      0.00%     78.75% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             42633393     15.92%     94.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            14250295      5.32%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             207547424     77.89%     77.89% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               926133      0.35%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                 6207      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd           33019      0.01%     78.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp          166254      0.06%     78.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt          259347      0.10%     78.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv           76101      0.03%     78.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         470014      0.18%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult         207509      0.08%     78.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc        71627      0.03%     78.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt            324      0.00%     78.72% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             42377903     15.90%     94.63% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            14312934      5.37%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              267717167                       # Type of FU issued
-system.cpu.iq.rate                           1.213793                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1924494                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.007189                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          754979573                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         505620151                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    248098864                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             3791065                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            2339721                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      1843061                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              267732701                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1908960                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1050657                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              266454796                       # Type of FU issued
+system.cpu.iq.rate                           1.215675                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1851718                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006949                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          751012737                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         499908383                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    246985878                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             3785085                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            2315100                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      1843098                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              266401517                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1904997                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1061099                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     21838970                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         7625                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       472350                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6083999                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     21507010                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         7624                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       380760                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      5851790                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads           11                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads           22                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             1                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               25172087                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                   44760                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                  3320                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           349368262                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           3978827                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              51690689                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             18730866                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            2350473                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    564                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  2427                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         472350                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       10008076                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      1698961                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             11707037                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             254915521                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              40541135                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          12801646                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               24821195                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                   25209                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                  3025                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           346635263                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           3972949                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              51358732                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             18498661                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            2299792                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    339                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  2453                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         380760                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       10016813                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      1701165                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             11717978                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             253656328                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              40286910                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          12798468                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         54149                       # number of nop insts executed
-system.cpu.iew.exec_refs                     54377446                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 53214768                       # Number of branches executed
-system.cpu.iew.exec_stores                   13836311                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.155753                       # Inst execution rate
-system.cpu.iew.wb_sent                      251638468                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     249941925                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 151812393                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 254020317                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         54087                       # number of nop insts executed
+system.cpu.iew.exec_refs                     54182001                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 53130827                       # Number of branches executed
+system.cpu.iew.exec_stores                   13895091                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.157283                       # Inst execution rate
+system.cpu.iew.wb_sent                      250510965                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     248828976                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 151533747                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 253038401                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.133203                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.597639                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.135259                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.598857                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      188682065                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       160676887                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1635628                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           9797761                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    195332552                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.965953                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.628775                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts      188682085                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       157943841                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1635632                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           9804994                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    194303231                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.971070                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.635692                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    109939001     56.28%     56.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     42858902     21.94%     78.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     20127469     10.30%     88.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8563678      4.38%     92.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      5111696      2.62%     95.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2060801      1.06%     96.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1694385      0.87%     97.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       852868      0.44%     97.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      4123752      2.11%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    109217628     56.21%     56.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     42594648     21.92%     78.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     19958113     10.27%     88.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8663175      4.46%     92.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      5049927      2.60%     95.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2103639      1.08%     96.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1719455      0.88%     97.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       826115      0.43%     97.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4170531      2.15%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    195332552                       # Number of insts commited each cycle
-system.cpu.commit.count                     188682065                       # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total    194303231                       # Number of insts commited each cycle
+system.cpu.commit.count                     188682085                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       42498585                       # Number of memory references committed
-system.cpu.commit.loads                      29851718                       # Number of loads committed
+system.cpu.commit.refs                       42498593                       # Number of memory references committed
+system.cpu.commit.loads                      29851722                       # Number of loads committed
 system.cpu.commit.membars                       22408                       # Number of memory barriers committed
-system.cpu.commit.branches                   40283916                       # Number of branches committed
+system.cpu.commit.branches                   40283920                       # Number of branches committed
 system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 150115157                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 150115173                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               4123752                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               4170531                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    540562551                       # The number of ROB reads
-system.cpu.rob.rob_writes                   723954086                       # The number of ROB writes
-system.cpu.timesIdled                            1712                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           57731                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   188667677                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             188667677                       # Number of Instructions Simulated
-system.cpu.cpi                               1.169052                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.169052                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.855394                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.855394                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1139481673                       # number of integer regfile reads
-system.cpu.int_regfile_writes               415646596                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   2922802                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2492399                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               524104390                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 824502                       # number of misc regfile writes
-system.cpu.icache.replacements                   1939                       # number of replacements
-system.cpu.icache.tagsinuse               1330.149475                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 42105837                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   3648                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               11542.170230                       # Average number of references to valid blocks.
+system.cpu.rob.rob_reads                    536753425                       # The number of ROB reads
+system.cpu.rob.rob_writes                   718144719                       # The number of ROB writes
+system.cpu.timesIdled                            1719                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           58183                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   188667697                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             188667697                       # Number of Instructions Simulated
+system.cpu.cpi                               1.161739                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.161739                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.860779                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.860779                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1134129060                       # number of integer regfile reads
+system.cpu.int_regfile_writes               413088145                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   2922495                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2493955                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               519944359                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 824510                       # number of misc regfile writes
+system.cpu.icache.replacements                   1926                       # number of replacements
+system.cpu.icache.tagsinuse               1331.949680                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 41931510                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   3631                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               11548.198843                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1330.149475                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.649487                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               42105837                       # number of ReadReq hits
-system.cpu.icache.demand_hits                42105837                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               42105837                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 4282                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  4282                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 4282                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      102623500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       102623500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      102623500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           42110119                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            42110119                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           42110119                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000102                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000102                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000102                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 23966.254087                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 23966.254087                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 23966.254087                       # average overall miss latency
+system.cpu.icache.occ_blocks::0           1331.949680                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.650366                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               41931510                       # number of ReadReq hits
+system.cpu.icache.demand_hits                41931510                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               41931510                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 4244                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  4244                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 4244                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      101763500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       101763500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      101763500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           41935754                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            41935754                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           41935754                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000101                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000101                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000101                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 23978.204524                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 23978.204524                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 23978.204524                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -353,67 +353,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               634                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                634                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               634                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            3648                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             3648                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            3648                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits               613                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                613                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               613                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            3631                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             3631                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            3631                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     74999500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     74999500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     74999500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     74668500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     74668500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     74668500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000087                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000087                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate     0.000087                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 20559.073465                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 20559.073465                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 20559.073465                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 20564.169650                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 20564.169650                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 20564.169650                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                     53                       # number of replacements
-system.cpu.dcache.tagsinuse               1408.348450                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 51108076                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                   1850                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               27625.987027                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                     54                       # number of replacements
+system.cpu.dcache.tagsinuse               1407.375528                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 50844385                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1848                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               27513.195346                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           1408.348450                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.343835                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               38699028                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              12356747                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits            27661                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits             24640                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits                51055775                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               51055775                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                 1814                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                7540                       # number of WriteReq misses
+system.cpu.dcache.occ_blocks::0           1407.375528                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.343598                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               38435222                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              12356746                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            27773                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             24644                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                50791968                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               50791968                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                 1795                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                7541                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses                  9354                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 9354                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       59541500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency     236790000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses                  9336                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 9336                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       59271500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     236699500                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency        63500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency       296331500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      296331500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           38700842                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency       295971000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      295971000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           38437017                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses          12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses        27663                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses         24640                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            51065129                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           51065129                       # number of overall (read+write) accesses
+system.cpu.dcache.LoadLockedReq_accesses        27775                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         24644                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            50801304                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           50801304                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate          0.000047                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate         0.000610                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate     0.000072                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.000183                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000183                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 32823.318633                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 31404.509284                       # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate           0.000184                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000184                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 33020.334262                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 31388.343721                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency        31750                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 31679.655762                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 31679.655762                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency 31702.120823                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 31702.120823                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets        20000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -423,69 +423,69 @@ system.cpu.dcache.avg_blocked_cycles::no_targets        20000
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks                       17                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits              1053                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits             6451                       # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits              1035                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits             6453                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits               7504                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits              7504                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             761                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           1089                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             1850                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            1850                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_hits               7488                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits              7488                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             760                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1088                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             1848                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            1848                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     24275500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency     38318500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency     62594000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency     62594000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency     24279500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     38244500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     62524000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     62524000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000020                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000088                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate      0.000036                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate     0.000036                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31899.474376                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35186.868687                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 33834.594595                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 33834.594595                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31946.710526                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35151.194853                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 33833.333333                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 33833.333333                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              1929.340531                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    1711                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                  2692                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.635587                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              1932.871986                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    1702                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  2683                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.634365                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1926.279074                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1             3.061457                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.058785                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          1929.817883                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             3.054103                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.058893                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::1            0.000093                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                  1711                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits                  1702                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits                  17                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                   8                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                   1719                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                  1719                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                2698                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses              1081                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 3779                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                3779                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      92484500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency     37157500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      129642000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     129642000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses              4409                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_hits                   9                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                   1711                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  1711                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                2689                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses              1079                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 3768                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                3768                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency      92183000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     37080500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      129263500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     129263500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              4391                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses              17                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            1089                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses               5498                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses              5498                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.611930                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.992654                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.687341                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.687341                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34278.910304                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34373.265495                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34305.901032                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34305.901032                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_accesses            1088                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses               5479                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              5479                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.612389                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.991728                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.687717                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.687717                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34281.517293                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34365.616311                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34305.599788                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34305.599788                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -495,27 +495,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits               15                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits                15                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits               15                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           2683                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         1081                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            3764                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           3764                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_hits               14                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                14                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits               14                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           2675                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1079                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            3754                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           3754                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     83387000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     33564500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    116951500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    116951500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency     83139500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     33503500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    116643000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    116643000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.608528                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.992654                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.684613                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.684613                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.761461                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31049.491212                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31071.068013                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31071.068013                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.609201                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.991728                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.685162                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.685162                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.186916                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31050.509731                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31071.656899                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31071.656899                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 13ca7132181ebb4f521a373c8a1576ecc652f63c..fbdea3a95fceb7a7d1b3fb60b87fd2e2067dc33e 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:18:15
-gem5 started Jul  9 2011 00:22:05
+gem5 compiled Jul 15 2011 18:01:24
+gem5 started Jul 15 2011 23:50:22
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
 Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav
@@ -24,4 +24,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 105045070000 because target called exit()
+122 123 124 Exiting @ tick 105044494000 because target called exit()
index 05846252dff1905596461dc80ef8d7dc61d3fbfa..b774063aab134178c767bb1fd7ed734618e024de 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.105045                       # Number of seconds simulated
-sim_ticks                                105045070000                       # Number of ticks simulated
+sim_seconds                                  0.105044                       # Number of seconds simulated
+sim_ticks                                105044494000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  49247                       # Simulator instruction rate (inst/s)
-host_tick_rate                               23369426                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 262348                       # Number of bytes of host memory used
-host_seconds                                  4494.98                       # Real time elapsed on the host
+host_inst_rate                                  56697                       # Simulator instruction rate (inst/s)
+host_tick_rate                               26904511                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262296                       # Number of bytes of host memory used
+host_seconds                                  3904.35                       # Real time elapsed on the host
 sim_insts                                   221363017                       # Number of instructions simulated
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        210090141                       # number of cpu cycles simulated
+system.cpu.numCycles                        210088989                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 25989444                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           25989444                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            2880460                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              23775424                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 20999107                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 25906091                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           25906091                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            2877681                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              23697798                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 20934390                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           30913045                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      262360842                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    25989444                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           20999107                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      70912631                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                26788053                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               84314801                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   59                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           386                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  28891572                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                510286                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          210004513                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.080616                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.257688                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           30843739                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      261974302                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    25906091                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           20934390                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      70794160                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                26721651                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               84571192                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   69                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           411                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  28839529                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                526028                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          210002245                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.077492                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.256338                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                140976557     67.13%     67.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4102515      1.95%     69.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  3266952      1.56%     70.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4494510      2.14%     72.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4287341      2.04%     74.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4445757      2.12%     76.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5469335      2.60%     79.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3067811      1.46%     81.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 39893735     19.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                141083594     67.18%     67.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4096564      1.95%     69.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  3267465      1.56%     70.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4473347      2.13%     72.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4273378      2.03%     74.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  4452036      2.12%     76.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5454314      2.60%     79.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3065570      1.46%     81.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 39835977     18.97%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            210004513                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.123706                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.248801                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 45877800                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              73040488                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  56067682                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              11154952                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               23863591                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              425695349                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               23863591                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 54978073                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                20531962                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          23888                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  57215372                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              53391627                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              414341081                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     9                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               29904351                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              20832303                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           439740854                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1072087884                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1060055510                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          12032374                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            210002245                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.123310                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.246968                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 45814663                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              73297000                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  55964774                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              11133134                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               23792674                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              424975722                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               23792674                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 54914820                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                20522213                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          23840                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  57109649                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              53639049                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              413573068                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    15                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               30245146                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              20822120                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           438852783                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1070324075                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1058519342                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          11804733                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             234363409                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                205377445                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1472                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1467                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 107891206                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            105317858                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            38075077                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          93159528                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         32053194                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  401973184                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                1452                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 281949896                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             93319                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       180405521                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    380338666                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            206                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     210004513                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.342590                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.373881                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                204489374                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1468                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1462                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 108174037                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            105166977                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            38036544                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          93207180                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         32406467                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  401191410                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                1447                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 281389101                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             88945                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       179610706                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    379681728                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            201                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     210002245                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.339934                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.371545                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            69632726     33.16%     33.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            64637798     30.78%     63.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            36965443     17.60%     81.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            20500342      9.76%     91.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            11980383      5.70%     97.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4341078      2.07%     99.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1469899      0.70%     99.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              380882      0.18%     99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8               95962      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            69597365     33.14%     33.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            64957213     30.93%     64.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            36846366     17.55%     81.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            20444772      9.74%     91.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            11872646      5.65%     97.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4318388      2.06%     99.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1525465      0.73%     99.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              350714      0.17%     99.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               89316      0.04%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       210004513                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       210002245                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  107259      3.58%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2493480     83.26%     86.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                394104     13.16%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  107872      3.66%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2450287     83.09%     86.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                390701     13.25%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           1205058      0.43%      0.43% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             187553155     66.52%     66.95% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     66.95% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             1592331      0.56%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.51% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             67840384     24.06%     91.57% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            23758968      8.43%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           1204241      0.43%      0.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             187252248     66.55%     66.97% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     66.97% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1588066      0.56%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.54% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             67629899     24.03%     91.57% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            23714647      8.43%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              281949896                       # Type of FU issued
-system.cpu.iq.rate                           1.342042                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2994843                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010622                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          771774380                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         576023644                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    274192966                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             5218087                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            6409815                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      2516754                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              281110852                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2628829                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         16405664                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              281389101                       # Type of FU issued
+system.cpu.iq.rate                           1.339381                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2948860                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010480                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          770610110                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         574654249                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    273620025                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             5208142                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            6216706                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      2514026                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              280509716                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2624004                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         16305906                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     48668268                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         6062                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        61115                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     17559361                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     48517387                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         5787                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        69063                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     17520828                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        45288                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads        45289                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               23863591                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  694538                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                427795                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           401974636                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            134263                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             105317858                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             38075077                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1452                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 312662                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 40441                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          61115                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        2496230                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       580255                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              3076485                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             278882390                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              66609586                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3067506                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               23792674                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  691646                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                425399                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           401192857                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            138630                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             105166977                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             38036544                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1447                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 309021                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 40843                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          69063                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        2486335                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       578919                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              3065254                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             278324671                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              66381551                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3064430                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     90001503                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 15748098                       # Number of branches executed
-system.cpu.iew.exec_stores                   23391917                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.327442                       # Inst execution rate
-system.cpu.iew.wb_sent                      277747224                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     276709720                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 222890509                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 374197573                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     89772300                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15687599                       # Number of branches executed
+system.cpu.iew.exec_stores                   23390749                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.324794                       # Inst execution rate
+system.cpu.iew.wb_sent                      277184129                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     276134051                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 222355020                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 373725319                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.317100                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.595649                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.314367                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.594969                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      221363017                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       180623719                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       179841994                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1246                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           2880510                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    186140922                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.189223                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.544912                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           2877741                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    186209571                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.188784                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.542023                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     71104558     38.20%     38.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     70002292     37.61%     75.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     18277000      9.82%     85.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     12672001      6.81%     92.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      5444041      2.92%     95.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2973709      1.60%     96.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      2048209      1.10%     98.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1096137      0.59%     98.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2522975      1.36%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     71071645     38.17%     38.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     70044936     37.62%     75.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     18344188      9.85%     85.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12667816      6.80%     92.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      5471591      2.94%     95.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2983054      1.60%     96.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      2040122      1.10%     98.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1105861      0.59%     98.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2480358      1.33%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    186140922                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    186209571                       # Number of insts commited each cycle
 system.cpu.commit.count                     221363017                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       77165306                       # Number of memory references committed
@@ -255,50 +255,50 @@ system.cpu.commit.branches                   12326943                       # Nu
 system.cpu.commit.fp_insts                    2162459                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 220339606                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               2522975                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               2480358                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    585604683                       # The number of ROB reads
-system.cpu.rob.rob_writes                   827851683                       # The number of ROB writes
-system.cpu.timesIdled                            1839                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           85628                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    584934224                       # The number of ROB reads
+system.cpu.rob.rob_writes                   826225881                       # The number of ROB writes
+system.cpu.timesIdled                            1865                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           86744                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   221363017                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             221363017                       # Number of Instructions Simulated
-system.cpu.cpi                               0.949075                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.949075                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.053657                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.053657                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                516476198                       # number of integer regfile reads
-system.cpu.int_regfile_writes               284804952                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   3512787                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2173928                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               145108967                       # number of misc regfile reads
+system.cpu.cpi                               0.949070                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.949070                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.053663                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.053663                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                515807985                       # number of integer regfile reads
+system.cpu.int_regfile_writes               284258767                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   3504419                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2170248                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               144660799                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    844                       # number of misc regfile writes
-system.cpu.icache.replacements                   4263                       # number of replacements
-system.cpu.icache.tagsinuse               1631.686111                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 28884352                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   6229                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                4637.076898                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                   4219                       # number of replacements
+system.cpu.icache.tagsinuse               1625.397975                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 28832382                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   6182                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                4663.924620                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1631.686111                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.796722                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               28884352                       # number of ReadReq hits
-system.cpu.icache.demand_hits                28884352                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               28884352                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 7220                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  7220                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 7220                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      170089500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       170089500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      170089500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           28891572                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            28891572                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           28891572                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000250                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000250                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000250                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 23558.102493                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 23558.102493                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 23558.102493                       # average overall miss latency
+system.cpu.icache.occ_blocks::0           1625.397975                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.793651                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               28832382                       # number of ReadReq hits
+system.cpu.icache.demand_hits                28832382                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               28832382                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 7147                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  7147                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 7147                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      169208500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       169208500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      169208500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           28839529                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            28839529                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           28839529                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000248                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000248                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000248                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 23675.458234                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 23675.458234                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 23675.458234                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -308,59 +308,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               990                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                990                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               990                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            6230                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             6230                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            6230                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits               961                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                961                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               961                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            6186                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             6186                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            6186                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    125517500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    125517500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    125517500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    125111000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    125111000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    125111000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000216                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000216                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000216                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 20147.271268                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 20147.271268                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 20147.271268                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000214                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000214                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000214                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 20224.862593                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 20224.862593                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 20224.862593                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                     50                       # number of replacements
-system.cpu.dcache.tagsinuse               1406.909972                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 70508700                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                   1965                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               35882.290076                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                     49                       # number of replacements
+system.cpu.dcache.tagsinuse               1408.251063                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 70379715                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1964                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               35834.885438                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           1406.909972                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.343484                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               50000081                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              20508618                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                70508699                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               70508699                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  707                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                7112                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                  7819                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 7819                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       23625000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency     187799500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency       211424500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      211424500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           50000788                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::0           1408.251063                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.343811                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               49871091                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              20508613                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                70379704                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               70379704                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  713                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                7117                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                  7830                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 7830                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       23577500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     188115500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency       211693000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      211693000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           49871804                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses          20515730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            70516518                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           70516518                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses            70387534                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           70387534                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate          0.000014                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate         0.000347                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate           0.000111                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate          0.000111                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 33415.841584                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 26406.003937                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 27039.838854                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 27039.838854                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 33068.022440                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 26431.853309                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 27036.143040                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 27036.143040                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -370,71 +370,71 @@ system.cpu.dcache.avg_blocked_cycles::no_targets     no_value
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks                       10                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits               303                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits             5550                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits               5853                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits              5853                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             404                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           1562                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             1966                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            1966                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits               311                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits             5551                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits               5862                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits              5862                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             402                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1566                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             1968                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            1968                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     13769000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency     54860000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency     68629000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency     68629000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency     13701000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     55004000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     68705000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     68705000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000008                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.000076                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate      0.000028                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate     0.000028                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34081.683168                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35121.638924                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 34907.934893                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 34907.934893                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34082.089552                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35123.882503                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34911.077236                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34911.077236                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              2506.517035                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    2870                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                  3766                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.762082                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              2496.142499                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    2832                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3755                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.754194                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          2505.502143                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1             1.014892                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.076462                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          2495.127708                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             1.014791                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.076145                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::1            0.000031                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                  2870                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits                  2832                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits                  10                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits                   6                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                   2876                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                  2876                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                3762                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses              1556                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 5318                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                5318                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     128883000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency     53194000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      182077000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     182077000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses              6632                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.demand_hits                   2838                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  2838                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                3751                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses                4                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses              1557                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 5308                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                5308                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     128522000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     53234000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      181756000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     181756000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              6583                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses              10                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            1562                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses               8194                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses              8194                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.567250                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_accesses              4                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            1563                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses               8146                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              8146                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.569801                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.996159                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.649011                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.649011                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34259.170654                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34186.375321                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34237.871380                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34237.871380                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate       0.996161                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.651608                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.651608                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34263.396428                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34190.109184                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34241.899020                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34241.899020                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -446,28 +446,28 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           3762                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         1556                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            5318                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           5318                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses           3751                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses            4                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1557                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            5308                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           5308                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    116744500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     48343500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    165088000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    165088000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency    116406500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency       124000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     48370500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    164777000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    164777000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.567250                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.569801                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.996159                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.649011                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.649011                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31032.562467                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.996161                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.651608                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.651608                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31033.457745                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.087404                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31043.249342                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31043.249342                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31066.473988                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31043.142427                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31043.142427                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index f022a446ddfeabd4247e96dd2e85a4e394c33545..fa9debdd1aae0d8088798e216c0636a5911b6b1e 100755 (executable)
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:00:53
-gem5 started Jul  8 2011 15:20:58
+gem5 compiled Jul 15 2011 17:43:54
+gem5 started Jul 15 2011 20:03:54
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 12002500 because target called exit()
+Exiting @ tick 12003500 because target called exit()
index 50d6ec22a9ec915e894fcf07ef6904de16e34fb3..a8b7869e57bf925d769eb572970c9230e7c89af2 100644 (file)
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000012                       # Number of seconds simulated
-sim_ticks                                    12002500                       # Number of ticks simulated
+sim_ticks                                    12003500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  25819                       # Simulator instruction rate (inst/s)
-host_tick_rate                               48521023                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 243716                       # Number of bytes of host memory used
-host_seconds                                     0.25                       # Real time elapsed on the host
+host_inst_rate                                  47992                       # Simulator instruction rate (inst/s)
+host_tick_rate                               90187460                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 243780                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        6386                       # Number of instructions simulated
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1863                       # DTB read hits
+system.cpu.dtb.read_hits                         1860                       # DTB read hits
 system.cpu.dtb.read_misses                         45                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1908                       # DTB read accesses
-system.cpu.dtb.write_hits                        1047                       # DTB write hits
+system.cpu.dtb.read_accesses                     1905                       # DTB read accesses
+system.cpu.dtb.write_hits                        1043                       # DTB write hits
 system.cpu.dtb.write_misses                        28                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    1075                       # DTB write accesses
-system.cpu.dtb.data_hits                         2910                       # DTB hits
+system.cpu.dtb.write_accesses                    1071                       # DTB write accesses
+system.cpu.dtb.data_hits                         2903                       # DTB hits
 system.cpu.dtb.data_misses                         73                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2983                       # DTB accesses
-system.cpu.itb.fetch_hits                        2044                       # ITB hits
+system.cpu.dtb.data_accesses                     2976                       # DTB accesses
+system.cpu.itb.fetch_hits                        2041                       # ITB hits
 system.cpu.itb.fetch_misses                        29                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    2073                       # ITB accesses
+system.cpu.itb.fetch_accesses                    2070                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -41,102 +41,102 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            24006                       # number of cpu cycles simulated
+system.cpu.numCycles                            24008                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     2516                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               1462                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                     2505                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               1456                       # Number of conditional branches predicted
 system.cpu.BPredUnit.condIncorrect                458                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  1947                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      723                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups                  1935                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      719                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                      372                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.usedRAS                      373                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                  67                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               7155                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          14481                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2516                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1095                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          2626                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1554                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles               7150                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          14447                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2505                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1092                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          2619                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1555                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.BlockedCycles                   1112                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                   24                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           631                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      2044                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   318                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              12602                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.149103                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.531397                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      2041                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   320                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              12591                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.147407                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.529389                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     9976     79.16%     79.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      274      2.17%     81.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      231      1.83%     83.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      220      1.75%     84.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      235      1.86%     86.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      176      1.40%     88.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      257      2.04%     90.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      141      1.12%     91.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1092      8.67%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     9972     79.20%     79.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      273      2.17%     81.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      226      1.79%     83.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      222      1.76%     84.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      235      1.87%     86.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      177      1.41%     88.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      258      2.05%     90.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      141      1.12%     91.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1087      8.63%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                12602                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.104807                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.603224                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     7976                       # Number of cycles decode is idle
+system.cpu.fetch.rateDist::total                12591                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.104340                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.601758                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     7971                       # Number of cycles decode is idle
 system.cpu.decode.BlockedCycles                  1126                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2455                       # Number of cycles decode is running
+system.cpu.decode.RunCycles                      2448                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                    69                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    976                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  216                       # Number of times decode resolved a branch
+system.cpu.decode.SquashCycles                    977                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  214                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                    85                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  13403                       # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts                  13375                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   215                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    976                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     8164                       # Number of cycles rename is idle
+system.cpu.rename.SquashCycles                    977                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     8160                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                     432                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles            358                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2326                       # Number of cycles rename is running
+system.cpu.rename.RunCycles                      2318                       # Number of cycles rename is running
 system.cpu.rename.UnblockCycles                   346                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  12866                       # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts                  12830                       # Number of instructions processed by rename
 system.cpu.rename.IQFullEvents                     11                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LSQFullEvents                   291                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands                9599                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 16086                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            16069                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands                9571                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 16046                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            16029                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                17                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  4583                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     5016                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     4988                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 28                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             22                       # count of temporary serializing insts renamed
 system.cpu.rename.skidInsts                       881                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2397                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1265                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.insertedLoads                 2392                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1263                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 4                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      11578                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      11550                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  27                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      9768                       # Number of instructions issued
+system.cpu.iq.iqInstsIssued                      9758                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued                45                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            4900                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         2850                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined            4875                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         2832                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             10                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         12602                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.775115                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.397410                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         12591                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.774998                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.396796                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                8516     67.58%     67.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1470     11.66%     79.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1066      8.46%     87.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 684      5.43%     93.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 441      3.50%     96.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 254      2.02%     98.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                8508     67.57%     67.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1466     11.64%     79.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1070      8.50%     87.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 685      5.44%     93.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 438      3.48%     96.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 253      2.01%     98.64% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                 129      1.02%     99.67% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                  30      0.24%     99.90% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  12      0.10%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           12602                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           12591                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                      13     12.38%     12.38% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     12.38% # attempts to use FU when none available
@@ -172,114 +172,114 @@ system.cpu.iq.fu_full::MemWrite                    38     36.19%    100.00% # at
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  6583     67.39%     67.41% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.42% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2078     21.27%     88.72% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1102     11.28%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  6577     67.40%     67.42% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.45% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2074     21.25%     88.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1102     11.29%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   9768                       # Type of FU issued
-system.cpu.iq.rate                           0.406898                       # Inst issue rate
+system.cpu.iq.FU_type_0::total                   9758                       # Type of FU issued
+system.cpu.iq.rate                           0.406448                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         105                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010749                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              32267                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             16511                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         8987                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate                   0.010760                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              32236                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             16459                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         8983                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  21                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 10                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           10                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   9860                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   9850                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      11                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               61                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               60                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1212                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1207                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           21                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          400                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           20                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          398                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    976                       # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles                    977                       # Number of cycles IEW is squashing
 system.cpu.iew.iewBlockCycles                     150                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                     8                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               11685                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               148                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2397                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1265                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts               11657                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               142                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2392                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1263                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 27                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      5                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             21                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            118                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.memOrderViolationEvents             20                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            119                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect          327                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  445                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  9324                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1918                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               444                       # Number of squashed instructions skipped in execute
+system.cpu.iew.branchMispredicts                  446                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  9316                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1915                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               442                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                            80                       # number of nop insts executed
-system.cpu.iew.exec_refs                         2995                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1503                       # Number of branches executed
-system.cpu.iew.exec_stores                       1077                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.388403                       # Inst execution rate
-system.cpu.iew.wb_sent                           9127                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          8997                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      4717                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      6401                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         2988                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1504                       # Number of branches executed
+system.cpu.iew.exec_stores                       1073                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.388037                       # Inst execution rate
+system.cpu.iew.wb_sent                           9122                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          8993                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      4720                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      6405                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.374781                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.736916                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.374583                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.736924                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           6403                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            5279                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            5251                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               380                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        11626                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.550748                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.411308                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        11614                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.551317                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.413328                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         8945     76.94%     76.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1414     12.16%     89.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          463      3.98%     93.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          244      2.10%     95.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          156      1.34%     96.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           87      0.75%     97.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          110      0.95%     98.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           44      0.38%     98.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         8938     76.96%     76.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1410     12.14%     89.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          462      3.98%     93.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          241      2.08%     95.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          158      1.36%     96.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           87      0.75%     97.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          110      0.95%     98.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           45      0.39%     98.60% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::8          163      1.40%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        11626                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        11614                       # Number of insts commited each cycle
 system.cpu.commit.count                          6403                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                           2050                       # Number of memory references committed
@@ -291,48 +291,48 @@ system.cpu.commit.int_insts                      6321                       # Nu
 system.cpu.commit.function_calls                  127                       # Number of function calls committed.
 system.cpu.commit.bw_lim_events                   163                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        22794                       # The number of ROB reads
-system.cpu.rob.rob_writes                       24351                       # The number of ROB writes
+system.cpu.rob.rob_reads                        22754                       # The number of ROB reads
+system.cpu.rob.rob_writes                       24296                       # The number of ROB writes
 system.cpu.timesIdled                             230                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           11404                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           11417                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        6386                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                  6386                       # Number of Instructions Simulated
-system.cpu.cpi                               3.759161                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.759161                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.266017                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.266017                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    11850                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    6735                       # number of integer regfile writes
+system.cpu.cpi                               3.759474                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.759474                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.265995                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.265995                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    11838                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    6732                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         8                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                159.654959                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1612                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                159.648657                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1609                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    311                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   5.183280                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   5.173633                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            159.654959                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.077957                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   1612                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    1612                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   1612                       # number of overall hits
+system.cpu.icache.occ_blocks::0            159.648657                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.077953                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits                   1609                       # number of ReadReq hits
+system.cpu.icache.demand_hits                    1609                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits                   1609                       # number of overall hits
 system.cpu.icache.ReadReq_misses                  432                       # number of ReadReq misses
 system.cpu.icache.demand_misses                   432                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses                  432                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       15402000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        15402000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       15402000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               2044                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                2044                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               2044                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.211350                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.211350                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.211350                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 35652.777778                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 35652.777778                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 35652.777778                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency       15393500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        15393500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       15393500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses               2041                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses                2041                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses               2041                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.211661                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.211661                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.211661                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 35633.101852                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35633.101852                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35633.101852                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -349,52 +349,52 @@ system.cpu.icache.ReadReq_mshr_misses             311                       # nu
 system.cpu.icache.demand_mshr_misses              311                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses             311                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     10985500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     10985500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     10985500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     10986500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     10986500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     10986500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.152153                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.152153                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.152153                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35323.151125                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35323.151125                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35323.151125                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.152376                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.152376                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.152376                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35326.366559                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35326.366559                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35326.366559                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                109.289403                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2155                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                109.288630                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2154                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    174                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  12.385057                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  12.379310                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            109.289403                       # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0            109.288630                       # Average occupied blocks per context
 system.cpu.dcache.occ_percent::0             0.026682                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1646                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits                   1645                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits                   509                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    2155                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   2155                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  155                       # number of ReadReq misses
+system.cpu.dcache.demand_hits                    2154                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits                   2154                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  154                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses                 356                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   511                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  511                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        5502500                       # number of ReadReq miss cycles
+system.cpu.dcache.demand_misses                   510                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                  510                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency        5497000                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency      12467500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency        17970000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       17970000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1801                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency        17964500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency       17964500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses               1799                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses               865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2666                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2666                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.086063                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses                2664                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses               2664                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.085603                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate         0.411561                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.191673                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.191673                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency        35500                       # average ReadReq miss latency
+system.cpu.dcache.demand_miss_rate           0.191441                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.191441                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 35694.805195                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency 35021.067416                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 35166.340509                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 35166.340509                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency 35224.509804                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 35224.509804                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -404,10 +404,10 @@ system.cpu.dcache.avg_blocked_cycles::no_targets     no_value
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                54                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits                53                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits              283                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                337                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               337                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits                336                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits               336                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses             101                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses             73                       # number of WriteReq MSHR misses
 system.cpu.dcache.demand_mshr_misses              174                       # number of demand (read+write) MSHR misses
@@ -418,10 +418,10 @@ system.cpu.dcache.WriteReq_mshr_miss_latency      2611500
 system.cpu.dcache.demand_mshr_miss_latency      6265500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency      6265500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.056080                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.056142                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.065266                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.065266                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.065315                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.065315                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36178.217822                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35773.972603                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency 36008.620690                       # average overall mshr miss latency
@@ -431,12 +431,12 @@ system.cpu.dcache.mshr_cap_events                   0                       # nu
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               221.186144                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               221.178797                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   411                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.002433                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           221.186144                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0           221.178797                       # Average occupied blocks per context
 system.cpu.l2cache.occ_percent::0            0.006750                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits                     1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits                      1                       # number of demand (read+write) hits
@@ -445,10 +445,10 @@ system.cpu.l2cache.ReadReq_misses                 411                       # nu
 system.cpu.l2cache.ReadExReq_misses                73                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses                  484                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses                 484                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      14128000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency      14129000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency      2513500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       16641500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      16641500                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency       16642500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency      16642500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses               412                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses              73                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses                485                       # number of demand (read+write) accesses
@@ -457,10 +457,10 @@ system.cpu.l2cache.ReadReq_miss_rate         0.997573                       # mi
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate          0.997938                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate         0.997938                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34374.695864                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34377.128954                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34431.506849                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34383.264463                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34383.264463                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34385.330579                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34385.330579                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
index 74424d63b828a38d622331957410f5a5da331461..b62422ecd3a58fe9917416350c2e15b056590a1c 100755 (executable)
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:00:53
-gem5 started Jul  8 2011 15:21:09
+gem5 compiled Jul 15 2011 17:43:54
+gem5 started Jul 15 2011 20:04:15
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 6921000 because target called exit()
+Exiting @ tick 6833000 because target called exit()
index 5e52ef944acf744a32a50ade1761b0befa2e7c2d..886aae88f39448da8db5ff59396f9c7fdc87f4df 100644 (file)
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000007                       # Number of seconds simulated
-sim_ticks                                     6921000                       # Number of ticks simulated
+sim_ticks                                     6833000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  33894                       # Simulator instruction rate (inst/s)
-host_tick_rate                               98227338                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242788                       # Number of bytes of host memory used
+host_inst_rate                                  36521                       # Simulator instruction rate (inst/s)
+host_tick_rate                              104491306                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 242860                       # Number of bytes of host memory used
 host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                          720                       # DTB read hits
-system.cpu.dtb.read_misses                         34                       # DTB read misses
+system.cpu.dtb.read_hits                          679                       # DTB read hits
+system.cpu.dtb.read_misses                         26                       # DTB read misses
 system.cpu.dtb.read_acv                             1                       # DTB read access violations
-system.cpu.dtb.read_accesses                      754                       # DTB read accesses
-system.cpu.dtb.write_hits                         354                       # DTB write hits
-system.cpu.dtb.write_misses                        22                       # DTB write misses
+system.cpu.dtb.read_accesses                      705                       # DTB read accesses
+system.cpu.dtb.write_hits                         356                       # DTB write hits
+system.cpu.dtb.write_misses                        18                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                     376                       # DTB write accesses
-system.cpu.dtb.data_hits                         1074                       # DTB hits
-system.cpu.dtb.data_misses                         56                       # DTB misses
+system.cpu.dtb.write_accesses                     374                       # DTB write accesses
+system.cpu.dtb.data_hits                         1035                       # DTB hits
+system.cpu.dtb.data_misses                         44                       # DTB misses
 system.cpu.dtb.data_acv                             1                       # DTB access violations
-system.cpu.dtb.data_accesses                     1130                       # DTB accesses
-system.cpu.itb.fetch_hits                         976                       # ITB hits
+system.cpu.dtb.data_accesses                     1079                       # DTB accesses
+system.cpu.itb.fetch_hits                         945                       # ITB hits
 system.cpu.itb.fetch_misses                        30                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    1006                       # ITB accesses
+system.cpu.itb.fetch_accesses                     975                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -41,245 +41,244 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.numCycles                            13843                       # number of cpu cycles simulated
+system.cpu.numCycles                            13667                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     1112                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted                583                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect                236                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                   781                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      240                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     1041                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted                518                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect                226                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                   733                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      220                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                      215                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.usedRAS                      210                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                  34                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               3787                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                           6697                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        1112                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                455                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          1166                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                     814                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                    253                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles               3751                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                           6413                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        1041                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                430                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          1115                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     754                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                    212                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                   17                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           781                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                       976                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   159                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples               6557                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.021351                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.437035                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles           785                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                       945                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   157                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples               6383                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.004700                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.420463                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     5391     82.22%     82.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                       67      1.02%     83.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      123      1.88%     85.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                       97      1.48%     86.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      146      2.23%     88.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                       50      0.76%     89.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                       61      0.93%     90.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                       83      1.27%     91.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      539      8.22%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     5268     82.53%     82.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                       60      0.94%     83.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      118      1.85%     85.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                       94      1.47%     86.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      140      2.19%     88.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                       58      0.91%     89.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                       55      0.86%     90.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                       65      1.02%     91.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      525      8.22%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                 6557                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.080329                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.483782                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     4673                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                   269                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      1132                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                     7                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    476                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  152                       # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total                 6383                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.076169                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.469232                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     4642                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                   226                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      1083                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                     6                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    426                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  158                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                    80                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                   6020                       # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts                   5734                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   284                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    476                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     4772                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                      89                       # Number of cycles rename is blocking
+system.cpu.rename.SquashCycles                    426                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     4737                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                      57                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles            147                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      1039                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                    34                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                   5743                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                     15                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                    11                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands                4153                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                  6495                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups             6483                       # Number of integer rename lookups
+system.cpu.rename.RunCycles                       997                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                    19                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                   5480                       # Number of instructions processed by rename
+system.cpu.rename.LSQFullEvents                    14                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands                3945                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                  6160                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups             6148                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                12                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  1768                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     2385                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     2177                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                  8                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts              6                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       117                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                  961                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                 458                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                 5                       # Number of conflicting loads.
+system.cpu.rename.skidInsts                       107                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                  882                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                 453                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                 3                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                3                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       4907                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                       4659                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                   6                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      3996                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                90                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            2355                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         1385                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                      3882                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                49                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            2129                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         1179                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples          6557                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.609425                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.316967                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples          6383                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.608178                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.298400                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                4952     75.52%     75.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                 578      8.82%     84.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 360      5.49%     89.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 270      4.12%     93.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 209      3.19%     97.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 109      1.66%     98.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                  54      0.82%     99.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  17      0.26%     99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                   8      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                4812     75.39%     75.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                 543      8.51%     83.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 388      6.08%     89.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 264      4.14%     94.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 199      3.12%     97.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 107      1.68%     98.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                  55      0.86%     99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  10      0.16%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                   5      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total            6557                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total            6383                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       1      2.27%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     20     45.45%     47.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    23     52.27%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       1      2.44%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     17     41.46%     43.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    23     56.10%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  2819     70.55%     70.55% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.03%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.57% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                  794     19.87%     90.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                 382      9.56%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  2767     71.28%     71.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.03%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.30% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                  734     18.91%     90.21% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                 380      9.79%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   3996                       # Type of FU issued
-system.cpu.iq.rate                           0.288666                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                          44                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.011011                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              14670                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes              7267                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         3636                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   3882                       # Type of FU issued
+system.cpu.iq.rate                           0.284042                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                          41                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010562                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              14224                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes              6793                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         3573                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  13                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  6                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            6                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   4033                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   3916                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       7                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               32                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               35                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads          546                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads          467                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation            6                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          164                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          159                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    476                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                      79                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                     7                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts                5242                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts                68                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                   961                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                  458                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                    426                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                      44                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                     6                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts                5003                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                64                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                   882                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                  453                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                  6                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      4                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents              6                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             52                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          137                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  189                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  3843                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                   755                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               153                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect             54                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          121                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  175                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  3749                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                   706                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               133                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                           329                       # number of nop insts executed
-system.cpu.iew.exec_refs                         1131                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                      644                       # Number of branches executed
-system.cpu.iew.exec_stores                        376                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.277613                       # Inst execution rate
-system.cpu.iew.wb_sent                           3725                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          3642                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      1733                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      2231                       # num instructions consuming a value
+system.cpu.iew.exec_nop                           338                       # number of nop insts executed
+system.cpu.iew.exec_refs                         1080                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                      629                       # Number of branches executed
+system.cpu.iew.exec_stores                        374                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.274310                       # Inst execution rate
+system.cpu.iew.wb_sent                           3647                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          3579                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      1702                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      2165                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.263093                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.776782                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.261872                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.786143                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           2576                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            2657                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            2418                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls               4                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               159                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples         6081                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.423615                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.271187                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               149                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples         5957                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.432432                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.291215                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         5177     85.13%     85.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          230      3.78%     88.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          323      5.31%     94.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          118      1.94%     96.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4           67      1.10%     97.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           52      0.86%     98.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           37      0.61%     98.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           20      0.33%     99.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           57      0.94%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         5066     85.04%     85.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          221      3.71%     88.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          314      5.27%     94.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          118      1.98%     96.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4           71      1.19%     97.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           53      0.89%     98.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           34      0.57%     98.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           20      0.34%     98.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           60      1.01%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total         6081                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total         5957                       # Number of insts commited each cycle
 system.cpu.commit.count                          2576                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                            709                       # Number of memory references committed
@@ -289,49 +288,49 @@ system.cpu.commit.branches                        396                       # Nu
 system.cpu.commit.fp_insts                          6                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      2367                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                   71                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                    57                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                    60                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        11010                       # The number of ROB reads
-system.cpu.rob.rob_writes                       10947                       # The number of ROB writes
+system.cpu.rob.rob_reads                        10644                       # The number of ROB reads
+system.cpu.rob.rob_writes                       10417                       # The number of ROB writes
 system.cpu.timesIdled                             139                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                            7286                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                            7284                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        2387                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                  2387                       # Number of Instructions Simulated
-system.cpu.cpi                               5.799330                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         5.799330                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.172434                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.172434                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                     4649                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    2817                       # number of integer regfile writes
+system.cpu.cpi                               5.725597                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         5.725597                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.174654                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.174654                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                     4520                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    2768                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         6                       # number of floating regfile reads
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                 92.452549                       # Cycle average of tags in use
-system.cpu.icache.total_refs                      735                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                 91.574139                       # Cycle average of tags in use
+system.cpu.icache.total_refs                      704                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    185                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   3.972973                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   3.805405                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0             92.452549                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.045143                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                    735                       # number of ReadReq hits
-system.cpu.icache.demand_hits                     735                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                    735                       # number of overall hits
+system.cpu.icache.occ_blocks::0             91.574139                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.044714                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits                    704                       # number of ReadReq hits
+system.cpu.icache.demand_hits                     704                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits                    704                       # number of overall hits
 system.cpu.icache.ReadReq_misses                  241                       # number of ReadReq misses
 system.cpu.icache.demand_misses                   241                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses                  241                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency        8775500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency         8775500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency        8775500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses                976                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                 976                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses                976                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.246926                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.246926                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.246926                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36412.863071                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36412.863071                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36412.863071                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency        8777500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency         8777500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency        8777500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses                945                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses                 945                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses                945                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.255026                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.255026                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.255026                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 36421.161826                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 36421.161826                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 36421.161826                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -348,52 +347,52 @@ system.cpu.icache.ReadReq_mshr_misses             185                       # nu
 system.cpu.icache.demand_mshr_misses              185                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses             185                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency      6554000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency      6554000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency      6554000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency      6554500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency      6554500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency      6554500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.189549                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.189549                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.189549                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35427.027027                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35427.027027                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35427.027027                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.195767                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.195767                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.195767                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35429.729730                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35429.729730                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35429.729730                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 45.779373                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                      794                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 45.439198                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                      765                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                     85                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                   9.341176                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                          9                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             45.779373                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.011177                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                    572                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::0             45.439198                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.011094                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits                    543                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits                   222                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                     794                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                    794                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  116                       # number of ReadReq misses
+system.cpu.dcache.demand_hits                     765                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits                    765                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  101                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses                  72                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   188                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  188                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        3872000                       # number of ReadReq miss cycles
+system.cpu.dcache.demand_misses                   173                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                  173                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency        3605000                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency       2816500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency         6688500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency        6688500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses                688                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency         6421500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency        6421500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses                644                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses               294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                 982                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses                982                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.168605                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses                 938                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses                938                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.156832                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate         0.244898                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.191446                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.191446                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 33379.310345                       # average ReadReq miss latency
+system.cpu.dcache.demand_miss_rate           0.184435                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.184435                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 35693.069307                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency 39118.055556                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 35577.127660                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 35577.127660                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency 37118.497110                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 37118.497110                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -403,50 +402,50 @@ system.cpu.dcache.avg_blocked_cycles::no_targets     no_value
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                55                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits                40                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits               48                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                103                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               103                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits                 88                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                88                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses              61                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses             24                       # number of WriteReq MSHR misses
 system.cpu.dcache.demand_mshr_misses               85                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses              85                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      2165500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency      2169000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency       872000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      3037500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      3037500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency      3041000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency      3041000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.088663                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.094720                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.081633                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.086558                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.086558                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency        35500                       # average ReadReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate      0.090618                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.090618                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35557.377049                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36333.333333                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35735.294118                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35735.294118                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35776.470588                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35776.470588                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               121.331762                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               120.203882                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   246                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                         0                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           121.331762                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.003703                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           120.203882                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.003668                       # Average percentage of cache occupancy
 system.cpu.l2cache.demand_hits                      0                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits                     0                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses                 246                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses                24                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses                  270                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses                 270                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency       8443500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency       8447500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency       831000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency        9274500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency       9274500                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency        9278500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency       9278500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses               246                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses              24                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses                270                       # number of demand (read+write) accesses
@@ -455,10 +454,10 @@ system.cpu.l2cache.ReadReq_miss_rate                1                       # mi
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate                 1                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate                1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34323.170732                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34339.430894                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency        34625                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        34350                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        34350                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34364.814815                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34364.814815                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -475,19 +474,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses           24                       # nu
 system.cpu.l2cache.demand_mshr_misses             270                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses            270                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency      7659500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency      7661500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency       756000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency      8415500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency      8415500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency      8417500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency      8417500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31136.178862                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31144.308943                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        31500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31168.518519                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31168.518519                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31175.925926                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31175.925926                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 357a5d59dea4f45c83b8e3340fbe17e2a56cf040..57d02de2647dcfb5408eabc6de87bb1abf075039 100755 (executable)
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:18:43
-gem5 started Jul  8 2011 15:23:20
+gem5 compiled Jul 15 2011 18:02:03
+gem5 started Jul 16 2011 04:26:12
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 9834500 because target called exit()
+Exiting @ tick 9807000 because target called exit()
index d884999d2c44f7e1bf75ec3889c0c35d39d9043d..6012e4873ec3aeedd40fc952d386de9622b37560 100644 (file)
@@ -1,12 +1,12 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000010                       # Number of seconds simulated
-sim_ticks                                     9834500                       # Number of ticks simulated
+sim_ticks                                     9807000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  38040                       # Simulator instruction rate (inst/s)
-host_tick_rate                               65174027                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 253652                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
+host_inst_rate                                  35563                       # Simulator instruction rate (inst/s)
+host_tick_rate                               60757564                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253712                       # Number of bytes of host memory used
+host_seconds                                     0.16                       # Real time elapsed on the host
 sim_insts                                        5739                       # Number of instructions simulated
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
@@ -51,244 +51,244 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.numCycles                            19670                       # number of cpu cycles simulated
+system.cpu.numCycles                            19615                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     2538                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               1884                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                     2511                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               1859                       # Number of conditional branches predicted
 system.cpu.BPredUnit.condIncorrect                440                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  1886                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      760                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups                  1876                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      752                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                      268                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                  53                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               6290                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          12764                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2538                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1028                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          2852                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1670                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   1030                       # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.RASInCorrect                  54                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles               6264                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          12675                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2511                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1020                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          2829                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1652                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                   1029                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    2                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles            31                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      2054                       # Number of cache lines fetched
+system.cpu.fetch.CacheLines                      2035                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   312                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              11334                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.423857                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.772019                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              11271                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.423476                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.772468                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     8482     74.84%     74.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      284      2.51%     77.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      192      1.69%     79.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      246      2.17%     81.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      242      2.14%     83.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      324      2.86%     86.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      124      1.09%     87.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      120      1.06%     88.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1320     11.65%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     8442     74.90%     74.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      274      2.43%     77.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      191      1.69%     79.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      247      2.19%     81.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      241      2.14%     83.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      319      2.83%     86.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      123      1.09%     87.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      122      1.08%     88.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1312     11.64%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                11334                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.129029                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.648907                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     6573                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1079                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2654                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    60                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    968                       # Number of cycles decode is squashing
+system.cpu.fetch.rateDist::total                11271                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.128014                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.646189                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     6547                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  1078                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2630                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    61                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    955                       # Number of cycles decode is squashing
 system.cpu.decode.BranchResolved                  421                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                   167                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  14169                       # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts                  14078                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   591                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    968                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     6862                       # Number of cycles rename is idle
+system.cpu.rename.SquashCycles                    955                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     6833                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                     248                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles            651                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2422                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   183                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  13321                       # Number of instructions processed by rename
+system.cpu.rename.RunCycles                      2402                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   182                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  13232                       # Number of instructions processed by rename
 system.cpu.rename.LSQFullEvents                   164                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               12898                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 60750                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            59430                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands               12797                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 60391                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            59071                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups              1320                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  5684                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     7209                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     7108                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 16                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             13                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       446                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2701                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1759                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                11                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores                5                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      11506                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts                       440                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2692                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1760                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                10                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores                8                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      11421                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  25                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      9339                       # Number of instructions issued
+system.cpu.iq.iqInstsIssued                      9287                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued               101                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            5207                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        14048                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined            5147                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        13929                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              1                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         11334                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.823981                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.484525                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         11271                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.823973                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.485474                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                7613     67.17%     67.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1341     11.83%     79.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 855      7.54%     86.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 564      4.98%     91.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 476      4.20%     95.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 284      2.51%     98.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 147      1.30%     99.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  42      0.37%     99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                7571     67.17%     67.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1335     11.84%     79.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 851      7.55%     86.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 557      4.94%     91.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 476      4.22%     95.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 278      2.47%     98.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 148      1.31%     99.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  43      0.38%     99.89% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  12      0.11%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           11334                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           11271                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       6      2.79%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    138     64.19%     66.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    71     33.02%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       6      2.75%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    141     64.68%     67.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    71     32.57%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  5727     61.32%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    7      0.07%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.03%     61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2324     24.88%     86.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1278     13.68%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5675     61.11%     61.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    7      0.08%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.03%     61.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.21% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2324     25.02%     86.24% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1278     13.76%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   9339                       # Type of FU issued
-system.cpu.iq.rate                           0.474784                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         215                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023022                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              30256                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             16705                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         8361                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   9287                       # Type of FU issued
+system.cpu.iq.rate                           0.473464                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         218                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023474                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              30092                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             16563                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         8319                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  72                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 48                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   9514                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   9465                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      40                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               67                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               66                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1500                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1491                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           19                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          821                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          822                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    968                       # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles                    955                       # Number of cycles IEW is squashing
 system.cpu.iew.iewBlockCycles                     129                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                     8                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               11534                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               218                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2701                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1759                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts               11449                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               210                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2692                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1760                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 13                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      0                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             19                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             95                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          303                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  398                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  8897                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2129                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               442                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect             96                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          301                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  397                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  8853                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2124                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               434                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             3                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3351                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1479                       # Number of branches executed
+system.cpu.iew.exec_refs                         3346                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1462                       # Number of branches executed
 system.cpu.iew.exec_stores                       1222                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.452313                       # Inst execution rate
-system.cpu.iew.wb_sent                           8556                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          8377                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      3980                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      7830                       # num instructions consuming a value
+system.cpu.iew.exec_rate                     0.451338                       # Inst execution rate
+system.cpu.iew.wb_sent                           8511                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          8335                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      3964                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      7808                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.425877                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.508301                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.424930                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.507684                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           5739                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            5640                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            5552                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              24                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               351                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        10367                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.553583                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.355703                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               350                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        10317                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.556266                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.365268                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         8010     77.26%     77.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1098     10.59%     87.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          433      4.18%     92.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          284      2.74%     94.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          184      1.77%     96.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          168      1.62%     98.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           67      0.65%     98.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           39      0.38%     99.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           84      0.81%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         7976     77.31%     77.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1088     10.55%     87.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          426      4.13%     91.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          280      2.71%     94.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          183      1.77%     96.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          171      1.66%     98.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           67      0.65%     98.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           38      0.37%     99.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           88      0.85%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        10367                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        10317                       # Number of insts commited each cycle
 system.cpu.commit.count                          5739                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                           2139                       # Number of memory references committed
@@ -298,49 +298,49 @@ system.cpu.commit.branches                        945                       # Nu
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      4985                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                   82                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                    84                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                    88                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        21505                       # The number of ROB reads
-system.cpu.rob.rob_writes                       23748                       # The number of ROB writes
+system.cpu.rob.rob_reads                        21363                       # The number of ROB reads
+system.cpu.rob.rob_writes                       23555                       # The number of ROB writes
 system.cpu.timesIdled                             180                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                            8336                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                            8344                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5739                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                  5739                       # Number of Instructions Simulated
-system.cpu.cpi                               3.427426                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.427426                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.291764                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.291764                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    40468                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    8226                       # number of integer regfile writes
+system.cpu.cpi                               3.417843                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.417843                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.292582                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.292582                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    40304                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    8184                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        29                       # number of floating regfile reads
-system.cpu.misc_regfile_reads                   15801                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                   15709                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
 system.cpu.icache.replacements                      2                       # number of replacements
-system.cpu.icache.tagsinuse                150.859133                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1688                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                150.950866                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1669                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    296                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   5.702703                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   5.638514                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            150.859133                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.073662                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   1688                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    1688                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   1688                       # number of overall hits
+system.cpu.icache.occ_blocks::0            150.950866                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.073706                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits                   1669                       # number of ReadReq hits
+system.cpu.icache.demand_hits                    1669                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits                   1669                       # number of overall hits
 system.cpu.icache.ReadReq_misses                  366                       # number of ReadReq misses
 system.cpu.icache.demand_misses                   366                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses                  366                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       12656500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        12656500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       12656500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               2054                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                2054                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               2054                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.178189                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.178189                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.178189                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 34580.601093                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 34580.601093                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 34580.601093                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency       12661500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        12661500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       12661500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses               2035                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses                2035                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses               2035                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.179853                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.179853                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.179853                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 34594.262295                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 34594.262295                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 34594.262295                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -357,60 +357,60 @@ system.cpu.icache.ReadReq_mshr_misses             296                       # nu
 system.cpu.icache.demand_mshr_misses              296                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses             296                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency      9940500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency      9940500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency      9940500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency      9939500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency      9939500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency      9939500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.144109                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.144109                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.144109                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 33582.770270                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 33582.770270                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 33582.770270                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.145455                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.145455                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.145455                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 33579.391892                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 33579.391892                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 33579.391892                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 92.281770                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 92.326406                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     2420                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    156                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  15.512821                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             92.281770                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.022530                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0             92.326406                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.022541                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits                   1791                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits                   609                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits                9                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits                11                       # number of StoreCondReq hits
 system.cpu.dcache.demand_hits                    2400                       # number of demand (read+write) hits
 system.cpu.dcache.overall_hits                   2400                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  178                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses                  177                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses                 304                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses                   482                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  482                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        5526000                       # number of ReadReq miss cycles
+system.cpu.dcache.demand_misses                   481                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                  481                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency        5493000                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency      10705500                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency        76500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency        16231500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       16231500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1969                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency        16198500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency       16198500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses               1968                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses               913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses            11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2882                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2882                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.090401                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses                2881                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses               2881                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.089939                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate         0.332968                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate     0.181818                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.167245                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.167245                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 31044.943820                       # average ReadReq miss latency
+system.cpu.dcache.demand_miss_rate           0.166956                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.166956                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 31033.898305                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency 35215.460526                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency        38250                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 33675.311203                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 33675.311203                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency 33676.715177                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 33676.715177                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -420,41 +420,41 @@ system.cpu.dcache.avg_blocked_cycles::no_targets     no_value
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                64                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits                63                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits              262                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                326                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               326                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits                325                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits               325                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses             114                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses             42                       # number of WriteReq MSHR misses
 system.cpu.dcache.demand_mshr_misses              156                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses             156                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      3236500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency      3236000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency      1505000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      4741500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      4741500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency      4741000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency      4741000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.057897                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.057927                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.046002                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.054129                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.054129                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28390.350877                       # average ReadReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate      0.054148                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.054148                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28385.964912                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 30394.230769                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 30394.230769                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 30391.025641                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 30391.025641                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               190.940380                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               191.048860                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                      43                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   362                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.118785                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           190.940380                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.005827                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           191.048860                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.005830                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits                    43                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits                     43                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits                    43                       # number of overall hits
@@ -462,10 +462,10 @@ system.cpu.l2cache.ReadReq_misses                 367                       # nu
 system.cpu.l2cache.ReadExReq_misses                42                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses                  409                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses                 409                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      12612500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency      12610500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency      1450500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       14063000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      14063000                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency       14061000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency      14061000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses               410                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses              42                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses                452                       # number of demand (read+write) accesses
@@ -474,10 +474,10 @@ system.cpu.l2cache.ReadReq_miss_rate         0.895122                       # mi
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate          0.904867                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate         0.904867                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34366.485014                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34361.035422                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency 34535.714286                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34383.863081                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34383.863081                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34378.973105                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34378.973105                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
index d2612b5d7d54a88ef242f5a80093950912818b4d..cfd15d7a73cc704eed667f812b4c18fb4484ff7f 100755 (executable)
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:04:50
-gem5 started Jul  8 2011 15:22:25
+gem5 compiled Jul 15 2011 17:48:05
+gem5 started Jul 15 2011 20:13:48
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 12285500 because target called exit()
+Exiting @ tick 12273500 because target called exit()
index 39498f79154f9e8c3b19558c7f2d8f52641c4b6f..d9d305c594ab310b0e485a7571cde46eebee70d3 100644 (file)
@@ -1,12 +1,12 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000012                       # Number of seconds simulated
-sim_ticks                                    12285500                       # Number of ticks simulated
+sim_ticks                                    12273500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  28817                       # Simulator instruction rate (inst/s)
-host_tick_rate                               68479139                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 244744                       # Number of bytes of host memory used
-host_seconds                                     0.18                       # Real time elapsed on the host
+host_inst_rate                                  33014                       # Simulator instruction rate (inst/s)
+host_tick_rate                               78373339                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 244788                       # Number of bytes of host memory used
+host_seconds                                     0.16                       # Real time elapsed on the host
 sim_insts                                        5169                       # Number of instructions simulated
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
@@ -27,199 +27,199 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            24572                       # number of cpu cycles simulated
+system.cpu.numCycles                            24548                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     1982                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               1348                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                     1977                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               1345                       # Number of conditional branches predicted
 system.cpu.BPredUnit.condIncorrect                399                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  1584                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      496                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups                  1580                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      493                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                      251                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                  71                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               7946                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          12305                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        1982                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                747                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          3034                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1194                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles               7914                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          12271                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        1977                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                744                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          3026                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1189                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.BlockedCycles                    756                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           145                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      1787                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   231                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              12667                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.971422                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.277830                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      1783                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   230                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              12623                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.972114                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.277844                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     9633     76.05%     76.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     1253      9.89%     85.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      111      0.88%     86.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      138      1.09%     87.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      289      2.28%     90.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                       92      0.73%     90.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      132      1.04%     91.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      144      1.14%     93.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      875      6.91%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     9597     76.03%     76.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     1250      9.90%     85.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      108      0.86%     86.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      139      1.10%     87.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      289      2.29%     90.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                       93      0.74%     90.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      132      1.05%     91.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      145      1.15%     93.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      870      6.89%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                12667                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.080661                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.500773                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     8135                       # Number of cycles decode is idle
+system.cpu.fetch.rateDist::total                12623                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.080536                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.499878                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     8103                       # Number of cycles decode is idle
 system.cpu.decode.BlockedCycles                   871                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2867                       # Number of cycles decode is running
+system.cpu.decode.RunCycles                      2859                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                    51                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    743                       # Number of cycles decode is squashing
+system.cpu.decode.SquashCycles                    739                       # Number of cycles decode is squashing
 system.cpu.decode.BranchResolved                  107                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                    43                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  11479                       # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts                  11438                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   162                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    743                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     8306                       # Number of cycles rename is idle
+system.cpu.rename.SquashCycles                    739                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     8274                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                     258                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles            499                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2750                       # Number of cycles rename is running
+system.cpu.rename.RunCycles                      2742                       # Number of cycles rename is running
 system.cpu.rename.UnblockCycles                   111                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11058                       # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts                  11017                       # Number of instructions processed by rename
 system.cpu.rename.LSQFullEvents                   101                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands                6730                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 13185                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            13180                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands                6705                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 13125                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            13120                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 5                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  3410                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     3320                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     3295                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 18                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             11                       # count of temporary serializing insts renamed
 system.cpu.rename.skidInsts                       281                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2359                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1184                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.insertedLoads                 2349                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1175                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                1                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       8691                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                       8651                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  13                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      7857                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                51                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            3019                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         1823                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                      7822                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                50                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            2995                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         1815                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              3                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         12667                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.620273                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.285525                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         12623                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.619663                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.285161                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                9298     73.40%     73.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1326     10.47%     83.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 831      6.56%     90.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 513      4.05%     94.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 361      2.85%     97.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 205      1.62%     98.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                  85      0.67%     99.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  33      0.26%     99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                9267     73.41%     73.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1321     10.47%     83.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 831      6.58%     90.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 511      4.05%     94.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 357      2.83%     97.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 203      1.61%     98.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                  83      0.66%     99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  35      0.28%     99.88% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  15      0.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           12667                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           12623                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       3      2.07%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     90     62.07%     64.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    52     35.86%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       3      2.05%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     91     62.33%     64.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    52     35.62%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  4616     58.75%     58.75% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    4      0.05%     58.80% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     2      0.03%     58.83% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.03%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     58.85% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2141     27.25%     86.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1092     13.90%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  4598     58.78%     58.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    4      0.05%     58.83% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     2      0.03%     58.86% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.03%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     58.89% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2131     27.24%     86.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1085     13.87%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   7857                       # Type of FU issued
-system.cpu.iq.rate                           0.319754                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         145                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.018455                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              28573                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             11730                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         7154                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   7822                       # Type of FU issued
+system.cpu.iq.rate                           0.318641                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         146                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.018665                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              28459                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             11666                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         7121                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   4                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  2                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            2                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   8000                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   7966                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       2                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               65                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1195                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1185                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation            9                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          259                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          250                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    743                       # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles                    739                       # Number of cycles IEW is squashing
 system.cpu.iew.iewBlockCycles                     165                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                    13                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10089                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts               10044                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts               128                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2359                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1184                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts                  2349                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1175                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 13                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      6                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
@@ -227,44 +227,44 @@ system.cpu.iew.memOrderViolationEvents              9                       # Nu
 system.cpu.iew.predictedTakenIncorrect            107                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect          309                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts                  416                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  7573                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2041                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               284                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts                  7537                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2031                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               285                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1385                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3109                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1276                       # Number of branches executed
-system.cpu.iew.exec_stores                       1068                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.308196                       # Inst execution rate
-system.cpu.iew.wb_sent                           7250                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          7156                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      2771                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      3964                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          1380                       # number of nop insts executed
+system.cpu.iew.exec_refs                         3091                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1271                       # Number of branches executed
+system.cpu.iew.exec_stores                       1060                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.307031                       # Inst execution rate
+system.cpu.iew.wb_sent                           7215                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          7123                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      2761                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      3949                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.291226                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.699041                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.290166                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.699164                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           5826                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            4255                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            4210                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              10                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               357                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        11924                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.488594                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.274116                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        11884                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.490239                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.276602                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         9523     79.86%     79.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          968      8.12%     87.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          656      5.50%     93.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          322      2.70%     96.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          146      1.22%     97.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         9485     79.81%     79.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          966      8.13%     87.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          656      5.52%     93.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          321      2.70%     96.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          147      1.24%     97.40% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::5          102      0.86%     98.26% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::6           64      0.54%     98.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           42      0.35%     99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          101      0.85%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           41      0.35%     99.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          102      0.86%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        11924                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        11884                       # Number of insts commited each cycle
 system.cpu.commit.count                          5826                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                           2089                       # Number of memory references committed
@@ -274,49 +274,49 @@ system.cpu.commit.branches                        916                       # Nu
 system.cpu.commit.fp_insts                          2                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      5124                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                   87                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                   101                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   102                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        21891                       # The number of ROB reads
-system.cpu.rob.rob_writes                       20916                       # The number of ROB writes
+system.cpu.rob.rob_reads                        21805                       # The number of ROB reads
+system.cpu.rob.rob_writes                       20822                       # The number of ROB writes
 system.cpu.timesIdled                             251                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           11905                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           11925                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5169                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                  5169                       # Number of Instructions Simulated
-system.cpu.cpi                               4.753724                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         4.753724                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.210361                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.210361                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    10347                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    5013                       # number of integer regfile writes
+system.cpu.cpi                               4.749081                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         4.749081                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.210567                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.210567                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    10287                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    4991                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         3                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                     154                       # number of misc regfile reads
 system.cpu.icache.replacements                     17                       # number of replacements
-system.cpu.icache.tagsinuse                161.262110                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1367                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                161.223747                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1364                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    336                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   4.068452                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   4.059524                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            161.262110                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.078741                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   1367                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    1367                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   1367                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  420                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   420                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  420                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       15216000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        15216000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       15216000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               1787                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                1787                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               1787                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.235031                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.235031                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.235031                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36228.571429                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36228.571429                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36228.571429                       # average overall miss latency
+system.cpu.icache.occ_blocks::0            161.223747                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.078723                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits                   1364                       # number of ReadReq hits
+system.cpu.icache.demand_hits                    1364                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits                   1364                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  419                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   419                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  419                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       15179500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        15179500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       15179500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses               1783                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses                1783                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses               1783                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.234997                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.234997                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.234997                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 36227.923628                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 36227.923628                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 36227.923628                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -326,59 +326,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits                84                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                 84                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                84                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits                83                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                 83                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                83                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses             336                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses              336                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses             336                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     11782000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     11782000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     11782000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     11784000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     11784000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     11784000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.188025                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.188025                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.188025                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35065.476190                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35065.476190                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35065.476190                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.188446                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.188446                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.188446                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35071.428571                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35071.428571                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35071.428571                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 92.136669                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2391                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 92.122056                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2382                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    142                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  16.838028                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  16.774648                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             92.136669                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.022494                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1813                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::0             92.122056                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.022491                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits                   1804                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits                   578                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    2391                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   2391                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  135                       # number of ReadReq misses
+system.cpu.dcache.demand_hits                    2382                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits                   2382                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  134                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses                 347                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   482                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  482                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        4832000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      11507500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency        16339500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       16339500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1948                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses                   481                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                  481                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency        4801000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency      11505500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency        16306500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency       16306500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses               1938                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses               925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2873                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2873                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.069302                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses                2863                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses               2863                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.069143                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate         0.375135                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.167769                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.167769                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 35792.592593                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33162.824207                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 33899.377593                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 33899.377593                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate           0.168006                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.168006                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 35828.358209                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 33157.060519                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 33901.247401                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 33901.247401                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -388,40 +388,40 @@ system.cpu.dcache.avg_blocked_cycles::no_targets     no_value
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                44                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits                43                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits              296                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                340                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               340                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits                339                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits               339                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses              91                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses             51                       # number of WriteReq MSHR misses
 system.cpu.dcache.demand_mshr_misses              142                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses             142                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.ReadReq_mshr_miss_latency      3272000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      1836500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      5108500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      5108500                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency      1835500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency      5107500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency      5107500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.046715                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.046956                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.049426                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.049426                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.049598                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.049598                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35956.043956                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36009.803922                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35975.352113                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35975.352113                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35990.196078                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35968.309859                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35968.309859                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               221.568003                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               221.520650                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       3                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   424                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.007075                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           221.568003                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.006762                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           221.520650                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.006760                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits                     3                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits                      3                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits                     3                       # number of overall hits
@@ -429,10 +429,10 @@ system.cpu.l2cache.ReadReq_misses                 424                       # nu
 system.cpu.l2cache.ReadExReq_misses                51                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses                  475                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses                 475                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      14561000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      1761000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       16322000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      16322000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency      14561500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency      1760000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency       16321500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency      16321500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses               427                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses              51                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses                478                       # number of demand (read+write) accesses
@@ -441,10 +441,10 @@ system.cpu.l2cache.ReadReq_miss_rate         0.992974                       # mi
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate          0.993724                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate         0.993724                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34341.981132                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34529.411765                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34362.105263                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34362.105263                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34343.160377                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34509.803922                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34361.052632                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34361.052632                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -461,19 +461,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses           51                       # nu
 system.cpu.l2cache.demand_mshr_misses             475                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses            475                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     13198500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      1599500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     14798000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     14798000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency     13198000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency      1598500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency     14796500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency     14796500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.992974                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate     0.993724                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate     0.993724                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31128.537736                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31362.745098                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31153.684211                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31153.684211                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31127.358491                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31343.137255                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.526316                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.526316                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 3b8650bce860c783df3848f9a49192299c61e72b..d1cb3e24690a18847d89ea750f3eb2682ef573b6 100755 (executable)
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:06:16
-gem5 started Jul  8 2011 15:22:37
+gem5 compiled Jul 15 2011 17:49:29
+gem5 started Jul 15 2011 20:14:11
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 11010500 because target called exit()
+Exiting @ tick 10910500 because target called exit()
index d012d707f52a8f779f7097a6561876c985a7bdae..bac6ac3e373f6fe21e445518839b87bd5699601f 100644 (file)
@@ -1,12 +1,12 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000011                       # Number of seconds simulated
-sim_ticks                                    11010500                       # Number of ticks simulated
+sim_ticks                                    10910500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  36368                       # Simulator instruction rate (inst/s)
-host_tick_rate                               69032646                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 241332                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
+host_inst_rate                                  31106                       # Simulator instruction rate (inst/s)
+host_tick_rate                               58503850                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 241340                       # Number of bytes of host memory used
+host_seconds                                     0.19                       # Real time elapsed on the host
 sim_insts                                        5800                       # Number of instructions simulated
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
@@ -27,244 +27,244 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    9                       # Number of system calls
-system.cpu.numCycles                            22022                       # number of cpu cycles simulated
+system.cpu.numCycles                            21822                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     2367                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               1975                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                     2297                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               1905                       # Number of conditional branches predicted
 system.cpu.BPredUnit.condIncorrect                402                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  1913                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      680                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups                  1853                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      666                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                      189                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                  30                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               6529                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          13348                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2367                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                869                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          2278                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1276                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                    941                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles               6507                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          12976                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2297                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                855                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          2210                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1212                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                    909                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines                      1754                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   281                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              10610                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.258058                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.653017                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      1711                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   280                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              10433                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.243746                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.642546                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     8332     78.53%     78.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      151      1.42%     79.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      185      1.74%     81.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      141      1.33%     83.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      226      2.13%     85.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      137      1.29%     86.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      283      2.67%     89.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      123      1.16%     90.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1032      9.73%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     8223     78.82%     78.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      152      1.46%     80.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      173      1.66%     81.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      127      1.22%     83.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      217      2.08%     85.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      137      1.31%     86.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      283      2.71%     89.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      122      1.17%     90.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      999      9.58%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                10610                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.107483                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.606121                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     6699                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1011                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2107                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    82                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    711                       # Number of cycles decode is squashing
+system.cpu.fetch.rateDist::total                10433                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.105261                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.594629                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     6670                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                   983                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2045                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    79                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    656                       # Number of cycles decode is squashing
 system.cpu.decode.BranchResolved                  304                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                   152                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  11818                       # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts                  11459                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   428                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    711                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     6902                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     392                       # Number of cycles rename is blocking
+system.cpu.rename.SquashCycles                    656                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     6866                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     379                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles            350                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      1977                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   278                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11283                       # Number of instructions processed by rename
+system.cpu.rename.RunCycles                      1920                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   262                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  10928                       # Number of instructions processed by rename
 system.cpu.rename.IQFullEvents                      7                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   220                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands                9842                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 18439                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            18368                       # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents                   207                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands                9549                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 17852                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            17781                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                71                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  5007                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     4835                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     4542                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 25                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             25                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       566                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 1897                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1627                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                48                       # Number of conflicting loads.
+system.cpu.rename.skidInsts                       544                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 1864                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1573                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                52                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores               44                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      10258                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                       9933                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  69                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      8750                       # Number of instructions issued
+system.cpu.iq.iqInstsIssued                      8536                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued                64                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            4202                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         3778                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined            3878                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         3544                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             53                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         10610                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.824694                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.535023                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         10433                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.818173                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.531685                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                7338     69.16%     69.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1037      9.77%     78.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 771      7.27%     86.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 497      4.68%     90.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 457      4.31%     95.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 303      2.86%     98.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 135      1.27%     99.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  49      0.46%     99.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                7234     69.34%     69.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1021      9.79%     79.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 762      7.30%     86.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 472      4.52%     90.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 448      4.29%     95.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 290      2.78%     98.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 132      1.27%     99.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  51      0.49%     99.78% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  23      0.22%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           10610                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           10433                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      10      6.45%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     68     43.87%     50.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    77     49.68%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       9      5.84%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     68     44.16%     50.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    77     50.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  5520     63.09%     63.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     63.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     63.09% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     63.11% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1751     20.01%     83.12% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1477     16.88%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5388     63.12%     63.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     63.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     63.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     63.14% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1717     20.11%     83.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1429     16.74%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8750                       # Type of FU issued
-system.cpu.iq.rate                           0.397330                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         155                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.017714                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              28255                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             14489                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         8028                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   8536                       # Type of FU issued
+system.cpu.iq.rate                           0.391165                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         154                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.018041                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              27649                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             13831                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         7849                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  74                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 52                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           30                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   8867                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   8652                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      38                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               79                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               68                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads          935                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads          902                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            1                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           19                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          581                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation            6                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          527                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    711                       # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles                    656                       # Number of cycles IEW is squashing
 system.cpu.iew.iewBlockCycles                     186                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                    23                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10327                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts               10002                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                43                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  1897                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1627                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts                  1864                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1573                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 60                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                     14                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             19                       # Number of memory order violations
+system.cpu.iew.memOrderViolationEvents              6                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect             62                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          239                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  301                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  8358                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1644                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               392                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedNotTakenIncorrect          238                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  300                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  8170                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1611                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               366                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3035                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1315                       # Number of branches executed
-system.cpu.iew.exec_stores                       1391                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.379530                       # Inst execution rate
-system.cpu.iew.wb_sent                           8174                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          8058                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      4233                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      6765                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         2952                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1313                       # Number of branches executed
+system.cpu.iew.exec_stores                       1341                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.374393                       # Inst execution rate
+system.cpu.iew.wb_sent                           7993                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          7879                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      4173                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      6691                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.365907                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.625721                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.361058                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.623674                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           5800                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            4533                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            4208                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              16                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               252                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples         9899                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.585918                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.365203                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples         9777                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.593229                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.375317                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         7502     75.79%     75.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          985      9.95%     85.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          645      6.52%     92.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          262      2.65%     94.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          188      1.90%     96.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          118      1.19%     97.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           77      0.78%     98.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           41      0.41%     99.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           81      0.82%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         7386     75.54%     75.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          981     10.03%     85.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          642      6.57%     92.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          262      2.68%     94.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          190      1.94%     96.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          116      1.19%     97.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           75      0.77%     98.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           41      0.42%     99.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           84      0.86%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total         9899                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total         9777                       # Number of insts commited each cycle
 system.cpu.commit.count                          5800                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                           2008                       # Number of memory references committed
@@ -274,45 +274,45 @@ system.cpu.commit.branches                       1038                       # Nu
 system.cpu.commit.fp_insts                         22                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      5706                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                  103                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                    81                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                    84                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        20151                       # The number of ROB reads
-system.cpu.rob.rob_writes                       21378                       # The number of ROB writes
-system.cpu.timesIdled                             216                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           11412                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        19701                       # The number of ROB reads
+system.cpu.rob.rob_writes                       20673                       # The number of ROB writes
+system.cpu.timesIdled                             218                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           11389                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5800                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                  5800                       # Number of Instructions Simulated
-system.cpu.cpi                               3.796897                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.796897                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.263373                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.263373                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    13256                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7085                       # number of integer regfile writes
+system.cpu.cpi                               3.762414                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.762414                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.265787                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.265787                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    12979                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    6957                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        28                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                169.489368                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1334                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                169.539680                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1291                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    351                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   3.800570                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   3.678063                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            169.489368                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.082758                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   1334                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    1334                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   1334                       # number of overall hits
+system.cpu.icache.occ_blocks::0            169.539680                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.082783                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits                   1291                       # number of ReadReq hits
+system.cpu.icache.demand_hits                    1291                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits                   1291                       # number of overall hits
 system.cpu.icache.ReadReq_misses                  420                       # number of ReadReq misses
 system.cpu.icache.demand_misses                   420                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses                  420                       # number of overall misses
 system.cpu.icache.ReadReq_miss_latency       15114500                       # number of ReadReq miss cycles
 system.cpu.icache.demand_miss_latency        15114500                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency       15114500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               1754                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                1754                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               1754                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.239453                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.239453                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.239453                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses               1711                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses                1711                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses               1711                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.245470                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.245470                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.245470                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency 35986.904762                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency 35986.904762                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency 35986.904762                       # average overall miss latency
@@ -336,9 +336,9 @@ system.cpu.icache.ReadReq_mshr_miss_latency     12207500                       #
 system.cpu.icache.demand_mshr_miss_latency     12207500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency     12207500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.200114                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.200114                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.200114                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate     0.205143                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.205143                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.205143                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 34779.202279                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 34779.202279                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 34779.202279                       # average overall mshr miss latency
@@ -347,37 +347,37 @@ system.cpu.icache.mshr_cap_events                   0                       # nu
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 66.389041                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2180                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 66.296919                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2156                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    105                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  20.761905                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  20.533333                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             66.389041                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.016208                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1445                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   735                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    2180                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   2180                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                   90                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                 311                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   401                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  401                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        3011000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      10558500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency        13569500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       13569500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1535                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::0             66.296919                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.016186                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits                   1428                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits                   728                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                    2156                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits                   2156                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                   88                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                 318                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                   406                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                  406                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency        2947000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency      10802500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency        13749500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency       13749500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses               1516                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses              1046                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2581                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2581                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.058632                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.297323                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.155366                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.155366                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 33455.555556                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33950.160772                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 33839.152120                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 33839.152120                       # average overall miss latency
+system.cpu.dcache.demand_accesses                2562                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses               2562                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.058047                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.304015                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.158470                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.158470                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 33488.636364                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 33970.125786                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 33865.763547                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 33865.763547                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -387,39 +387,39 @@ system.cpu.dcache.avg_blocked_cycles::no_targets     no_value
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                33                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits              263                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                296                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               296                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits                31                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits              270                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits                301                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits               301                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses              57                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses             48                       # number of WriteReq MSHR misses
 system.cpu.dcache.demand_mshr_misses              105                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses             105                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.ReadReq_mshr_miss_latency      1963500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      1750500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      3714000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      3714000                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency      1751000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency      3714500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency      3714500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.037134                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.037599                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.045889                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.040682                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.040682                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.040984                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.040984                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34447.368421                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36468.750000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35371.428571                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35371.428571                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36479.166667                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35376.190476                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35376.190476                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               200.598447                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               200.613051                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       9                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   399                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.022556                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           200.598447                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0           200.613051                       # Average occupied blocks per context
 system.cpu.l2cache.occ_percent::0            0.006122                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits                     9                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits                      9                       # number of demand (read+write) hits
@@ -429,9 +429,9 @@ system.cpu.l2cache.ReadExReq_misses                48                       # nu
 system.cpu.l2cache.demand_misses                  447                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses                 447                       # number of overall misses
 system.cpu.l2cache.ReadReq_miss_latency      13714000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      1678000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       15392000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      15392000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency      1678500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency       15392500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency      15392500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses               408                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses              48                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses                456                       # number of demand (read+write) accesses
@@ -441,9 +441,9 @@ system.cpu.l2cache.ReadExReq_miss_rate              1                       # mi
 system.cpu.l2cache.demand_miss_rate          0.980263                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate         0.980263                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency 34370.927318                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34958.333333                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34434.004474                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34434.004474                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34968.750000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34435.123043                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34435.123043                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -460,19 +460,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses           48                       # nu
 system.cpu.l2cache.demand_mshr_misses             447                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses            447                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     12433500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency     12434000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency      1526000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     13959500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     13959500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency     13960000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency     13960000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.977941                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate     0.980263                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate     0.980263                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31161.654135                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31162.907268                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31791.666667                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31229.306488                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31229.306488                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.425056                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.425056                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index e361952bb21ec41278fbdd3f801d1e7b5d083416..66b7170d90d90c0f562206e253b275f3b1a65e4b 100755 (executable)
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:18:15
-gem5 started Jul  8 2011 15:23:04
+gem5 compiled Jul 15 2011 18:01:24
+gem5 started Jul 16 2011 00:22:08
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 11102000 because target called exit()
+Exiting @ tick 11087000 because target called exit()
index a1f123e2277d1f6e54e8c2532f800b223655fb74..f6f7897f3246f006155a22ee010b9c563b208fbc 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000011                       # Number of seconds simulated
-sim_ticks                                    11102000                       # Number of ticks simulated
+sim_ticks                                    11087000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  58378                       # Simulator instruction rate (inst/s)
-host_tick_rate                               66066423                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 248304                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
+host_inst_rate                                  48237                       # Simulator instruction rate (inst/s)
+host_tick_rate                               54512378                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 248340                       # Number of bytes of host memory used
+host_seconds                                     0.20                       # Real time elapsed on the host
 sim_insts                                        9809                       # Number of instructions simulated
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            22205                       # number of cpu cycles simulated
+system.cpu.numCycles                            22175                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     3070                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               3070                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                     3057                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               3057                       # Number of conditional branches predicted
 system.cpu.BPredUnit.condIncorrect                497                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  2745                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                     1002                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups                  2732                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      995                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               5900                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          14062                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        3070                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1002                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          3986                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    2234                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles               5894                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          14000                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        3057                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                995                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          3968                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    2223                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.BlockedCycles                   1500                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles             9                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      1900                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   273                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              13123                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.933552                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.219407                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      1891                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   272                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              13088                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.930776                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.218766                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     9243     70.43%     70.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      169      1.29%     71.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      176      1.34%     73.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      241      1.84%     74.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      234      1.78%     76.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      195      1.49%     78.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      280      2.13%     80.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      141      1.07%     81.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2444     18.62%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     9227     70.50%     70.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      167      1.28%     71.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      175      1.34%     73.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      239      1.83%     74.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      232      1.77%     76.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      193      1.47%     78.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      279      2.13%     80.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      139      1.06%     81.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2437     18.62%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                13123                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.138257                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.633281                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     6251                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1454                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      3582                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   112                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1724                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  24194                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1724                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     6540                       # Number of cycles rename is idle
+system.cpu.fetch.rateDist::total                13088                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.137858                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.631342                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     6247                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  1453                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      3564                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   111                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1713                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  24084                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                   1713                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     6535                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                     523                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles            524                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      3382                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   430                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  22801                       # Number of instructions processed by rename
+system.cpu.rename.RunCycles                      3364                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   429                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  22708                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                     2                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                     68                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LSQFullEvents                   271                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               21341                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 47863                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            47847                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands               21249                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 47660                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            47644                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  9368                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    11973                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                    11881                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 33                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             33                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      1611                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2253                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1786                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts                      1609                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2239                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1783                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                13                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores                5                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      20643                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  35                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     17013                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                65                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           10307                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        13151                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             22                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         13123                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.296426                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.004622                       # Number of insts issued each cycle
+system.cpu.memDep0.conflictingStores                6                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      20542                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  34                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     16959                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                63                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined           10220                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        13000                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             21                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         13088                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.295767                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.003323                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                8026     61.16%     61.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1107      8.44%     69.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1007      7.67%     77.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 730      5.56%     82.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 676      5.15%     87.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 728      5.55%     93.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 620      4.72%     98.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 194      1.48%     99.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  35      0.27%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                8001     61.13%     61.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1107      8.46%     69.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1007      7.69%     77.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 733      5.60%     82.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 670      5.12%     88.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 725      5.54%     93.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 615      4.70%     98.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 196      1.50%     99.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  34      0.26%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           13123                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           13088                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      95     66.90%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     24     16.90%     83.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    23     16.20%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      94     66.67%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     24     17.02%     83.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    23     16.31%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 4      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 13681     80.41%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1854     10.90%     91.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1474      8.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 13641     80.44%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1844     10.87%     91.33% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1470      8.67%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  17013                       # Type of FU issued
-system.cpu.iq.rate                           0.766179                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         142                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.008347                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              47348                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             30994                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        15803                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  16959                       # Type of FU issued
+system.cpu.iq.rate                           0.764780                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         141                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.008314                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              47202                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             30805                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        15753                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  17147                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  17092                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               80                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1197                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses           13                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1183                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses           12                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           14                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          852                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          849                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1724                       # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles                   1713                       # Number of cycles IEW is squashing
 system.cpu.iew.iewBlockCycles                     144                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                    16                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               20678                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts                15                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2253                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1786                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 35                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispatchedInsts               20576                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                23                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2239                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1783                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 34                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      6                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             14                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             66                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          524                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  590                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 16148                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1748                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               865                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect             65                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          523                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  588                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 16098                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1742                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               861                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3114                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1606                       # Number of branches executed
-system.cpu.iew.exec_stores                       1366                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.727224                       # Inst execution rate
-system.cpu.iew.wb_sent                          15964                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         15807                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                     10570                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     15744                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3105                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1601                       # Number of branches executed
+system.cpu.iew.exec_stores                       1363                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.725953                       # Inst execution rate
+system.cpu.iew.wb_sent                          15916                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         15757                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                     10536                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     15696                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.711867                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.671367                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.710575                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.671254                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           9809                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts           10868                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           10766                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              13                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               497                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        11399                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.860514                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.681683                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        11375                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.862330                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.686905                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         7958     69.81%     69.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1091      9.57%     79.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          577      5.06%     84.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          889      7.80%     92.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          346      3.04%     95.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          149      1.31%     96.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          139      1.22%     97.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           66      0.58%     98.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          184      1.61%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         7943     69.83%     69.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1088      9.56%     79.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          574      5.05%     84.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          883      7.76%     92.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          343      3.02%     95.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          152      1.34%     96.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          139      1.22%     97.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           66      0.58%     98.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          187      1.64%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        11399                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        11375                       # Number of insts commited each cycle
 system.cpu.commit.count                          9809                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                           1990                       # Number of memory references committed
@@ -255,48 +255,48 @@ system.cpu.commit.branches                       1214                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      9714                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                   184                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   187                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        31892                       # The number of ROB reads
-system.cpu.rob.rob_writes                       43113                       # The number of ROB writes
+system.cpu.rob.rob_reads                        31763                       # The number of ROB reads
+system.cpu.rob.rob_writes                       42898                       # The number of ROB writes
 system.cpu.timesIdled                             182                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                            9082                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                            9087                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        9809                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                  9809                       # Number of Instructions Simulated
-system.cpu.cpi                               2.263737                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.263737                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.441747                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.441747                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    23720                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   14686                       # number of integer regfile writes
+system.cpu.cpi                               2.260679                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.260679                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.442345                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.442345                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    23665                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   14643                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
-system.cpu.misc_regfile_reads                    7234                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                    7210                       # number of misc regfile reads
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                145.121253                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1536                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                145.144237                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1527                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    298                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   5.154362                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   5.124161                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            145.121253                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.070860                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   1536                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    1536                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   1536                       # number of overall hits
+system.cpu.icache.occ_blocks::0            145.144237                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.070871                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits                   1527                       # number of ReadReq hits
+system.cpu.icache.demand_hits                    1527                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits                   1527                       # number of overall hits
 system.cpu.icache.ReadReq_misses                  364                       # number of ReadReq misses
 system.cpu.icache.demand_misses                   364                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses                  364                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       13311000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        13311000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       13311000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               1900                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                1900                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               1900                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.191579                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.191579                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.191579                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36568.681319                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36568.681319                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36568.681319                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency       13314500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        13314500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       13314500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses               1891                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses                1891                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses               1891                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.192491                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.192491                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.192491                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 36578.296703                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 36578.296703                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 36578.296703                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -313,52 +313,52 @@ system.cpu.icache.ReadReq_mshr_misses             298                       # nu
 system.cpu.icache.demand_mshr_misses              298                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses             298                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     10465000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     10465000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     10465000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     10466500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     10466500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     10466500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.156842                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.156842                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.156842                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35117.449664                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35117.449664                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35117.449664                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.157589                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.157589                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.157589                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35122.483221                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35122.483221                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35122.483221                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 85.500276                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2118                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 85.499149                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2112                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    145                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  14.606897                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  14.565517                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             85.500276                       # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0             85.499149                       # Average occupied blocks per context
 system.cpu.dcache.occ_percent::0             0.020874                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1500                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits                   1494                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits                   618                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    2118                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   2118                       # number of overall hits
+system.cpu.dcache.demand_hits                    2112                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits                   2112                       # number of overall hits
 system.cpu.dcache.ReadReq_misses                  113                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses                 316                       # number of WriteReq misses
 system.cpu.dcache.demand_misses                   429                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses                  429                       # number of overall misses
 system.cpu.dcache.ReadReq_miss_latency        3938500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      10704500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency        14643000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       14643000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1613                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_miss_latency      10708500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency        14647000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency       14647000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses               1607                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses               934                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2547                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2547                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.070056                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses                2541                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses               2541                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.070317                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate         0.338330                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.168433                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.168433                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate           0.168831                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.168831                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency 34853.982301                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency        33875                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 34132.867133                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 34132.867133                       # average overall miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 33887.658228                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 34142.191142                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 34142.191142                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -377,17 +377,17 @@ system.cpu.dcache.WriteReq_mshr_misses             77                       # nu
 system.cpu.dcache.demand_mshr_misses              146                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses             146                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      2421500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      2762000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency      2422500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency      2761000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_latency      5183500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency      5183500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.042777                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.042937                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.082441                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.057322                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.057322                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35094.202899                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35870.129870                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate      0.057458                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.057458                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35108.695652                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35857.142857                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency 35503.424658                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 35503.424658                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
@@ -395,13 +395,13 @@ system.cpu.dcache.mshr_cap_events                   0                       # nu
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               178.583785                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               178.614114                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   364                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.005495                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           178.583785                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.005450                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           178.614114                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.005451                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits                     2                       # number of overall hits
@@ -409,10 +409,10 @@ system.cpu.l2cache.ReadReq_misses                 365                       # nu
 system.cpu.l2cache.ReadExReq_misses                77                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses                  442                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses                 442                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      12493000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      2653500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       15146500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      15146500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency      12494500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency      2654000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency       15148500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency      15148500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses               367                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses              77                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses                444                       # number of demand (read+write) accesses
@@ -421,10 +421,10 @@ system.cpu.l2cache.ReadReq_miss_rate         0.994550                       # mi
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate          0.995495                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate         0.995495                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34227.397260                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34461.038961                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34268.099548                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34268.099548                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34231.506849                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34467.532468                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34272.624434                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34272.624434                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -441,19 +441,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses           77                       # nu
 system.cpu.l2cache.demand_mshr_misses             442                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses            442                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     11328000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency     11330000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency      2409500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     13737500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     13737500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency     13739500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency     13739500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate     0.994550                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate     0.995495                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate     0.995495                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.616438                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31041.095890                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31292.207792                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31080.316742                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31080.316742                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31084.841629                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31084.841629                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index f562f208e0710c85308dce70824fcae071787de6..ece91e6a2c8cb7f5dfbb7b64188ef9178e81376e 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:00:53
-gem5 started Jul  8 2011 15:21:20
+gem5 compiled Jul 15 2011 17:43:54
+gem5 started Jul 15 2011 20:04:28
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -11,4 +11,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 Hello world!
 Hello world!
-Exiting @ tick 13218000 because target called exit()
+Exiting @ tick 13202000 because target called exit()
index ba1ddb358a29cc6c43d47113e609a51e5a948c6a..85f082537587d38ada9fa9b94d2d61411ce8ffa4 100644 (file)
@@ -1,33 +1,33 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000013                       # Number of seconds simulated
-sim_ticks                                    13218000                       # Number of ticks simulated
+sim_ticks                                    13202000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  47211                       # Simulator instruction rate (inst/s)
-host_tick_rate                               48851159                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 244284                       # Number of bytes of host memory used
-host_seconds                                     0.27                       # Real time elapsed on the host
+host_inst_rate                                  45146                       # Simulator instruction rate (inst/s)
+host_tick_rate                               46657266                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 244348                       # Number of bytes of host memory used
+host_seconds                                     0.28                       # Real time elapsed on the host
 sim_insts                                       12773                       # Number of instructions simulated
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         3714                       # DTB read hits
-system.cpu.dtb.read_misses                         89                       # DTB read misses
+system.cpu.dtb.read_hits                         3722                       # DTB read hits
+system.cpu.dtb.read_misses                         94                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     3803                       # DTB read accesses
-system.cpu.dtb.write_hits                        1992                       # DTB write hits
-system.cpu.dtb.write_misses                        59                       # DTB write misses
+system.cpu.dtb.read_accesses                     3816                       # DTB read accesses
+system.cpu.dtb.write_hits                        1984                       # DTB write hits
+system.cpu.dtb.write_misses                        61                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    2051                       # DTB write accesses
+system.cpu.dtb.write_accesses                    2045                       # DTB write accesses
 system.cpu.dtb.data_hits                         5706                       # DTB hits
-system.cpu.dtb.data_misses                        148                       # DTB misses
+system.cpu.dtb.data_misses                        155                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     5854                       # DTB accesses
-system.cpu.itb.fetch_hits                        4085                       # ITB hits
+system.cpu.dtb.data_accesses                     5861                       # DTB accesses
+system.cpu.itb.fetch_hits                        4091                       # ITB hits
 system.cpu.itb.fetch_misses                        56                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    4141                       # ITB accesses
+system.cpu.itb.fetch_accesses                    4147                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -42,175 +42,175 @@ system.cpu.itb.data_acv                             0                       # DT
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload0.num_syscalls                  17                       # Number of system calls
 system.cpu.workload1.num_syscalls                  17                       # Number of system calls
-system.cpu.numCycles                            26437                       # number of cpu cycles simulated
+system.cpu.numCycles                            26405                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     5187                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               2958                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect               1247                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  3609                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                     1000                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     5174                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               2964                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect               1252                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  3548                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                     1004                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                      740                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                 156                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               1108                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          29051                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        5187                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1740                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          5000                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1319                       # Number of cycles fetch has spent squashing
+system.cpu.BPredUnit.usedRAS                      734                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                 158                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles               1115                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          28962                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        5174                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1738                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          4987                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1325                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   44                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines                      4085                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   640                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              20361                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.426796                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.797497                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      4091                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   637                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              20201                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.433691                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.801868                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    15361     75.44%     75.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      451      2.22%     77.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      362      1.78%     79.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      388      1.91%     81.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      391      1.92%     83.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      325      1.60%     84.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      409      2.01%     86.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      323      1.59%     88.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2351     11.55%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    15214     75.31%     75.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      449      2.22%     77.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      365      1.81%     79.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      384      1.90%     81.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      390      1.93%     83.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      328      1.62%     84.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      404      2.00%     86.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      329      1.63%     88.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2338     11.57%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                20361                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.196202                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.098877                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    28250                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  5561                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      4330                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   453                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1870                       # Number of cycles decode is squashing
+system.cpu.fetch.rateDist::total                20201                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.195948                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.096838                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    27985                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  5533                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      4328                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   445                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1869                       # Number of cycles decode is squashing
 system.cpu.decode.BranchResolved                  485                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   311                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  25978                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   552                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                   1870                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    28803                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    2995                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            772                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      4141                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1883                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  24541                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    11                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.LSQFullEvents                  1746                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               18357                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 30569                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            30535                       # Number of integer rename lookups
+system.cpu.decode.BranchMispred                   315                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  25962                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   512                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                   1869                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    28534                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    2990                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            752                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      4136                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  1879                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  24542                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    12                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.LSQFullEvents                  1739                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               18358                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 30575                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            30541                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                34                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  9166                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     9191                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     9192                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 52                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             40                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      4665                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2306                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1192                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts                      4646                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2308                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1190                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads                 2327                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores                1184                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.insertedLoads                 2319                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores                1181                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep1.conflictingLoads                 3                       # Number of conflicting loads.
 system.cpu.memDep1.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      22275                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      22288                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  49                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     19420                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                71                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            8699                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         4701                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                     19435                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                67                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            8694                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         4709                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             15                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         20361                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.953784                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.476295                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         20201                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.962081                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.481018                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               12146     59.65%     59.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                2930     14.39%     74.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                2237     10.99%     85.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1382      6.79%     91.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 875      4.30%     96.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 479      2.35%     98.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 226      1.11%     99.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  69      0.34%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  17      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               11990     59.35%     59.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                2928     14.49%     73.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                2232     11.05%     84.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1366      6.76%     91.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 891      4.41%     96.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 479      2.37%     98.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 237      1.17%     99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  60      0.30%     99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  18      0.09%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           20361                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           20201                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       8      4.44%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    103     57.22%     61.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    69     38.33%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       9      4.92%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    106     57.92%     62.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    68     37.16%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  6596     67.90%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2046     21.06%     89.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1068     10.99%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  6617     67.89%     67.91% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.94% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2056     21.09%     89.03% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1069     10.97%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   9715                       # Type of FU issued
+system.cpu.iq.FU_type_0::total                   9747                       # Type of FU issued
 system.cpu.iq.FU_type_1::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu                  6577     67.77%     67.79% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu                  6565     67.76%     67.78% # Type of FU issued
 system.cpu.iq.FU_type_1::IntMult                    1      0.01%     67.80% # Type of FU issued
 system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     67.80% # Type of FU issued
 system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     67.82% # Type of FU issued
@@ -239,13 +239,13 @@ system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     67.82% # Ty
 system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     67.82% # Type of FU issued
 system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     67.82% # Type of FU issued
 system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead                 2049     21.11%     88.93% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite                1074     11.07%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead                 2046     21.12%     88.93% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite                1072     11.07%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total                   9705                       # Type of FU issued
+system.cpu.iq.FU_type_1::total                   9688                       # Type of FU issued
 system.cpu.iq.FU_type::No_OpClass                   4      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type::IntAlu                   13173     67.83%     67.85% # Type of FU issued
+system.cpu.iq.FU_type::IntAlu                   13182     67.83%     67.85% # Type of FU issued
 system.cpu.iq.FU_type::IntMult                      2      0.01%     67.86% # Type of FU issued
 system.cpu.iq.FU_type::IntDiv                       0      0.00%     67.86% # Type of FU issued
 system.cpu.iq.FU_type::FloatAdd                     4      0.02%     67.88% # Type of FU issued
@@ -274,127 +274,127 @@ system.cpu.iq.FU_type::SimdFloatMisc                0      0.00%     67.88% # Ty
 system.cpu.iq.FU_type::SimdFloatMult                0      0.00%     67.88% # Type of FU issued
 system.cpu.iq.FU_type::SimdFloatMultAcc             0      0.00%     67.88% # Type of FU issued
 system.cpu.iq.FU_type::SimdFloatSqrt                0      0.00%     67.88% # Type of FU issued
-system.cpu.iq.FU_type::MemRead                   4095     21.09%     88.97% # Type of FU issued
-system.cpu.iq.FU_type::MemWrite                  2142     11.03%    100.00% # Type of FU issued
+system.cpu.iq.FU_type::MemRead                   4102     21.11%     88.98% # Type of FU issued
+system.cpu.iq.FU_type::MemWrite                  2141     11.02%    100.00% # Type of FU issued
 system.cpu.iq.FU_type::IprAccess                    0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type::InstPrefetch                 0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type::total                    19420                       # Type of FU issued
-system.cpu.iq.rate                           0.734577                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0                       90                       # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1                       90                       # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total                  180                       # FU busy when requested
-system.cpu.iq.fu_busy_rate::0                0.004634                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1                0.004634                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total            0.009269                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              59410                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             31025                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        17735                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type::total                    19435                       # Type of FU issued
+system.cpu.iq.rate                           0.736035                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0                       94                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1                       89                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total                  183                       # FU busy when requested
+system.cpu.iq.fu_busy_rate::0                0.004837                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1                0.004579                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total            0.009416                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              59279                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             31036                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        17747                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  42                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 20                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           20                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  19574                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  19592                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               48                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1121                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1123                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           16                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          327                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           15                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          325                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads               64                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread1.forwLoads               61                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread1.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads         1142                       # Number of loads squashed
+system.cpu.iew.lsq.thread1.squashedLoads         1134                       # Number of loads squashed
 system.cpu.iew.lsq.thread1.ignoredResponses            5                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation           13                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores          319                       # Number of stores squashed
+system.cpu.iew.lsq.thread1.memOrderViolation           16                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores          316                       # Number of stores squashed
 system.cpu.iew.lsq.thread1.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread1.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread1.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread1.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1870                       # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles                   1869                       # Number of cycles IEW is squashing
 system.cpu.iew.iewBlockCycles                    1204                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    65                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               22464                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               427                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  4633                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2376                       # Number of dispatched store instructions
+system.cpu.iew.iewUnblockCycles                    64                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               22477                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               401                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  4627                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2371                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 49                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                     38                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     1                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             29                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            214                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          883                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                 1097                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 18405                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0               1891                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1               1918                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total           3809                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1015                       # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents             31                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            218                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          882                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                 1100                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 18425                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0               1901                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1               1921                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total           3822                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1010                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp::0                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::1                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::total                      0                       # number of swp insts executed
 system.cpu.iew.exec_nop::0                         75                       # number of nop insts executed
 system.cpu.iew.exec_nop::1                         65                       # number of nop insts executed
 system.cpu.iew.exec_nop::total                    140                       # number of nop insts executed
-system.cpu.iew.exec_refs::0                      2925                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::1                      2953                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::total                  5878                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::0                      2932                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::1                      2948                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::total                  5880                       # number of memory reference insts executed
 system.cpu.iew.exec_branches::0                  1521                       # Number of branches executed
-system.cpu.iew.exec_branches::1                  1527                       # Number of branches executed
-system.cpu.iew.exec_branches::total              3048                       # Number of branches executed
-system.cpu.iew.exec_stores::0                    1034                       # Number of stores executed
-system.cpu.iew.exec_stores::1                    1035                       # Number of stores executed
-system.cpu.iew.exec_stores::total                2069                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.696183                       # Inst execution rate
-system.cpu.iew.wb_sent::0                        9003                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1                        9003                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total                   18006                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0                       8892                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::1                       8863                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::total                  17755                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0                   4543                       # num instructions producing a value
-system.cpu.iew.wb_producers::1                   4543                       # num instructions producing a value
-system.cpu.iew.wb_producers::total               9086                       # num instructions producing a value
-system.cpu.iew.wb_consumers::0                   5945                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::1                   5949                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::total              11894                       # num instructions consuming a value
+system.cpu.iew.exec_branches::1                  1526                       # Number of branches executed
+system.cpu.iew.exec_branches::total              3047                       # Number of branches executed
+system.cpu.iew.exec_stores::0                    1031                       # Number of stores executed
+system.cpu.iew.exec_stores::1                    1027                       # Number of stores executed
+system.cpu.iew.exec_stores::total                2058                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.697785                       # Inst execution rate
+system.cpu.iew.wb_sent::0                        9024                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1                        8991                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total                   18015                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0                       8913                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::1                       8854                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::total                  17767                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0                   4555                       # num instructions producing a value
+system.cpu.iew.wb_producers::1                   4549                       # num instructions producing a value
+system.cpu.iew.wb_producers::total               9104                       # num instructions producing a value
+system.cpu.iew.wb_consumers::0                   5963                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::1                   5961                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::total              11924                       # num instructions consuming a value
 system.cpu.iew.wb_penalized::0                      0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_penalized::1                      0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_penalized::total                  0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate::0                    0.336347                       # insts written-back per cycle
-system.cpu.iew.wb_rate::1                    0.335250                       # insts written-back per cycle
-system.cpu.iew.wb_rate::total                0.671597                       # insts written-back per cycle
-system.cpu.iew.wb_fanout::0                  0.764172                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::1                  0.763658                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::total              1.527829                       # average fanout of values written-back
+system.cpu.iew.wb_rate::0                    0.337550                       # insts written-back per cycle
+system.cpu.iew.wb_rate::1                    0.335315                       # insts written-back per cycle
+system.cpu.iew.wb_rate::total                0.672865                       # insts written-back per cycle
+system.cpu.iew.wb_fanout::0                  0.763877                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::1                  0.763127                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::total              1.527004                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate::0                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::1                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::total             0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts          12807                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            9583                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            9596                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              34                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               951                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        20336                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.629770                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.428976                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               953                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        20176                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.634764                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.436773                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        14766     72.61%     72.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         2895     14.24%     86.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1050      5.16%     92.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          514      2.53%     94.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          350      1.72%     96.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          235      1.16%     97.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          212      1.04%     98.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           89      0.44%     98.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          225      1.11%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        14631     72.52%     72.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         2865     14.20%     86.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1050      5.20%     91.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          518      2.57%     94.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          346      1.71%     96.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          239      1.18%     97.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          208      1.03%     98.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           91      0.45%     98.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          228      1.13%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        20336                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        20176                       # Number of insts commited each cycle
 system.cpu.commit.count::0                       6403                       # Number of instructions committed
 system.cpu.commit.count::1                       6404                       # Number of instructions committed
 system.cpu.commit.count::total                  12807                       # Number of instructions committed
@@ -422,25 +422,25 @@ system.cpu.commit.int_insts::total              12642                       # Nu
 system.cpu.commit.function_calls::0               127                       # Number of function calls committed.
 system.cpu.commit.function_calls::1               127                       # Number of function calls committed.
 system.cpu.commit.function_calls::total           254                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                   225                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   228                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited::0                     0                       # number of insts not committed due to BW limits
 system.cpu.commit.bw_limited::1                     0                       # number of insts not committed due to BW limits
 system.cpu.commit.bw_limited::total                 0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                       101662                       # The number of ROB reads
-system.cpu.rob.rob_writes                       46661                       # The number of ROB writes
-system.cpu.timesIdled                             242                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                            6076                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                       101307                       # The number of ROB reads
+system.cpu.rob.rob_writes                       46689                       # The number of ROB writes
+system.cpu.timesIdled                             233                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                            6204                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts::0                     6386                       # Number of Instructions Simulated
 system.cpu.committedInsts::1                     6387                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                 12773                       # Number of Instructions Simulated
-system.cpu.cpi::0                            4.139837                       # CPI: Cycles Per Instruction
-system.cpu.cpi::1                            4.139189                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.069757                       # CPI: Total CPI of All Threads
-system.cpu.ipc::0                            0.241555                       # IPC: Instructions Per Cycle
-system.cpu.ipc::1                            0.241593                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.483149                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    23349                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   13299                       # number of integer regfile writes
+system.cpu.cpi::0                            4.134826                       # CPI: Cycles Per Instruction
+system.cpu.cpi::1                            4.134179                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.067251                       # CPI: Total CPI of All Threads
+system.cpu.ipc::0                            0.241848                       # IPC: Instructions Per Cycle
+system.cpu.ipc::1                            0.241886                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.483734                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    23374                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   13316                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        4                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       2                       # number of misc regfile reads
@@ -448,41 +448,41 @@ system.cpu.misc_regfile_writes                      2                       # nu
 system.cpu.icache.replacements::0                   6                       # number of replacements
 system.cpu.icache.replacements::1                   0                       # number of replacements
 system.cpu.icache.replacements::total               6                       # number of replacements
-system.cpu.icache.tagsinuse                314.403866                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     3230                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                314.165301                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     3236                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    626                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   5.159744                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   5.169329                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            314.403866                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.153518                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   3230                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    3230                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   3230                       # number of overall hits
+system.cpu.icache.occ_blocks::0            314.165301                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.153401                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits                   3236                       # number of ReadReq hits
+system.cpu.icache.demand_hits                    3236                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits                   3236                       # number of overall hits
 system.cpu.icache.ReadReq_misses                  855                       # number of ReadReq misses
 system.cpu.icache.demand_misses                   855                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses                  855                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::0     30717000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     30717000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::0     30717000                       # number of demand (read+write) miss cycles
+system.cpu.icache.ReadReq_miss_latency::0     30710500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     30710500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::0     30710500                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_latency::1            0                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     30717000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::0     30717000                       # number of overall miss cycles
+system.cpu.icache.demand_miss_latency::total     30710500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::0     30710500                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::1            0                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     30717000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               4085                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                4085                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               4085                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.209302                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.209302                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.209302                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 35926.315789                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 35926.315789                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 35926.315789                       # average overall miss latency
+system.cpu.icache.overall_miss_latency::total     30710500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses               4091                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses                4091                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses               4091                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.208995                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.208995                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.208995                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::0 35918.713450                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35918.713450                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::0 35918.713450                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 35926.315789                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 35926.315789                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35918.713450                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::0 35918.713450                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 35926.315789                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35918.713450                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -513,30 +513,30 @@ system.cpu.icache.overall_mshr_misses::total          626
 system.cpu.icache.overall_mshr_uncacheable_misses::0            0                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::1            0                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::0     22275500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     22275500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::0     22275500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::0     22267000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     22267000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::0     22267000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_latency::1            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     22275500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::0     22275500                       # number of overall MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     22267000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::0     22267000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::1            0                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     22275500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     22267000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::0            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::1            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.153244                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.153244                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0     0.153244                       # mshr miss rate for demand accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::0     0.153019                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.153019                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::0     0.153019                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::1            0                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.153244                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0     0.153244                       # mshr miss rate for overall accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.153019                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::0     0.153019                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.153244                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35583.865815                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::0 35583.865815                       # average overall mshr miss latency
+system.cpu.icache.overall_mshr_miss_rate::total     0.153019                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35570.287540                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::0 35570.287540                       # average overall mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::1     no_value                       # average overall mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::total     no_value                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::0 35583.865815                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::0 35570.287540                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::1     no_value                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total     no_value                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::0     no_value                       # average overall mshr uncacheable latency
@@ -552,49 +552,49 @@ system.cpu.icache.no_allocate_misses                0                       # Nu
 system.cpu.dcache.replacements::0                   0                       # number of replacements
 system.cpu.dcache.replacements::1                   0                       # number of replacements
 system.cpu.dcache.replacements::total               0                       # number of replacements
-system.cpu.dcache.tagsinuse                216.203520                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     4314                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                216.133399                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     4323                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    347                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  12.432277                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  12.458213                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            216.203520                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.052784                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   3294                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::0            216.133399                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.052767                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits                   3303                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits                  1020                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    4314                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   4314                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  306                       # number of ReadReq misses
+system.cpu.dcache.demand_hits                    4323                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits                   4323                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  308                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses                 710                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                  1016                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 1016                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::0     11205000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11205000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::0     24076500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     24076500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::0     35281500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_misses                  1018                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 1018                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::0     11179500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11179500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::0     24106500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     24106500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::0     35286000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_latency::1            0                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     35281500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::0     35281500                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::total     35286000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::0     35286000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::1            0                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     35281500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               3600                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.overall_miss_latency::total     35286000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses               3611                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses              1730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                5330                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               5330                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.085000                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses                5341                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses               5341                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.085295                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate         0.410405                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.190619                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.190619                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 36617.647059                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 36617.647059                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 33910.563380                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33910.563380                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 34725.885827                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate           0.190601                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.190601                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::0 36297.077922                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 36297.077922                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::0 33952.816901                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33952.816901                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::0 34662.082515                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 34725.885827                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 34725.885827                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 34662.082515                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0 34662.082515                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 34725.885827                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 34662.082515                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -606,16 +606,16 @@ system.cpu.dcache.cache_copies                      0                       # nu
 system.cpu.dcache.writebacks::0                     0                       # number of writebacks
 system.cpu.dcache.writebacks::1                     0                       # number of writebacks
 system.cpu.dcache.writebacks::total                 0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::0            105                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          105                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::0            107                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          107                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::0           564                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          564                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::0             669                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::0             671                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_hits::1               0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          669                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::0            669                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          671                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::0            671                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_hits::1              0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          669                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          671                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::0          201                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          201                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::0          146                       # number of WriteReq MSHR misses
@@ -629,35 +629,35 @@ system.cpu.dcache.overall_mshr_misses::total          347
 system.cpu.dcache.overall_mshr_uncacheable_misses::0            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::1            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::0      7390000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7390000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::0      5293000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5293000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::0     12683000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::0      7376000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7376000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::0      5298000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5298000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::0     12674000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_latency::1            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     12683000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::0     12683000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     12674000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::0     12674000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::1            0                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     12683000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     12674000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency::0            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency::1            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency::total            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.055833                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.055833                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.055663                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.055663                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.084393                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0     0.065103                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::0     0.064969                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::1            0                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.065103                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0     0.065103                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.064969                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::0     0.064969                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.065103                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36766.169154                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36253.424658                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::0 36550.432277                       # average overall mshr miss latency
+system.cpu.dcache.overall_mshr_miss_rate::total     0.064969                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36696.517413                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36287.671233                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::0 36524.495677                       # average overall mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::1     no_value                       # average overall mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::total     no_value                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::0 36550.432277                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::0 36524.495677                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::1     no_value                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total     no_value                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0     no_value                       # average overall mshr uncacheable latency
@@ -673,13 +673,13 @@ system.cpu.dcache.no_allocate_misses                0                       # Nu
 system.cpu.l2cache.replacements::0                  0                       # number of replacements
 system.cpu.l2cache.replacements::1                  0                       # number of replacements
 system.cpu.l2cache.replacements::total              0                       # number of replacements
-system.cpu.l2cache.tagsinuse               435.485428                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               435.235373                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   825                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.002424                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           435.485428                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.013290                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           435.235373                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.013282                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits                     2                       # number of overall hits
@@ -687,16 +687,16 @@ system.cpu.l2cache.ReadReq_misses                 825                       # nu
 system.cpu.l2cache.ReadExReq_misses               146                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses                  971                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses                 971                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::0     28485000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     28485000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::0      5065500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5065500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::0     33550500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::0     28470000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     28470000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::0      5066000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5066000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::0     33536000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::1            0                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     33550500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::0     33550500                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::total     33536000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::0     33536000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::1            0                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     33550500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     33536000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses               827                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses             146                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses                973                       # number of demand (read+write) accesses
@@ -705,16 +705,16 @@ system.cpu.l2cache.ReadReq_miss_rate         0.997582                       # mi
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate          0.997945                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate         0.997945                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::0 34527.272727                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34527.272727                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34695.205479                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34695.205479                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::0 34552.523172                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::0 34509.090909                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34509.090909                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34698.630137                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34698.630137                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::0 34537.590113                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34552.523172                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::0 34552.523172                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34537.590113                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::0 34537.590113                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34552.523172                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34537.590113                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs        21000                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                4                       # number of cycles access was blocked
@@ -745,16 +745,16 @@ system.cpu.l2cache.overall_mshr_misses::total          971
 system.cpu.l2cache.overall_mshr_uncacheable_misses::0            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::1            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::0     25905000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25905000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::0      4613500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4613500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::0     30518500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::0     25887000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25887000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::0      4614000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4614000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::0     30501000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::1            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     30518500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::0     30518500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     30501000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::0     30501000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::1            0                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     30518500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     30501000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::0            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::1            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::total            0                       # number of overall MSHR uncacheable cycles
@@ -768,12 +768,12 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.997945
 system.cpu.l2cache.overall_mshr_miss_rate::0     0.997945                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.997945                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0        31400                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31599.315068                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31429.969104                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31378.181818                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31602.739726                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31411.946447                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::1     no_value                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::total     no_value                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31429.969104                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31411.946447                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::1     no_value                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total     no_value                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0     no_value                       # average overall mshr uncacheable latency
index 636722350b9708c82f7ce93c54add1cda755201f..8de42a2d1bb3cfef07284d8a64b56f1bc7399388 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:08:13
-gem5 started Jul  8 2011 15:22:48
+gem5 compiled Jul 15 2011 17:51:42
+gem5 started Jul 15 2011 20:49:40
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -18,4 +18,4 @@ LDTX:         Passed
 LDTW:          Passed
 STTW:          Passed
 Done
-Exiting @ tick 18121000 because target called exit()
+Exiting @ tick 18114000 because target called exit()
index 34c9dc344e0ef412f04b86c6b06536e10e657df5..44f3bc0f0bf0d6827ab749bf470c7a33be4d6810 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000018                       # Number of seconds simulated
-sim_ticks                                    18121000                       # Number of ticks simulated
+sim_ticks                                    18114000                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  13353                       # Simulator instruction rate (inst/s)
-host_tick_rate                               16745708                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 246680                       # Number of bytes of host memory used
-host_seconds                                     1.08                       # Real time elapsed on the host
+host_inst_rate                                  40525                       # Simulator instruction rate (inst/s)
+host_tick_rate                               50798832                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 250076                       # Number of bytes of host memory used
+host_seconds                                     0.36                       # Real time elapsed on the host
 sim_insts                                       14449                       # Number of instructions simulated
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            36243                       # number of cpu cycles simulated
+system.cpu.numCycles                            36229                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     5652                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               3765                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect                848                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  5024                       # Number of BTB lookups
+system.cpu.BPredUnit.lookups                     5641                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               3757                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect                847                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  5015                       # Number of BTB lookups
 system.cpu.BPredUnit.BTBHits                     2638                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                      357                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                 168                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles              10750                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          25938                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        5652                       # Number of branches that fetch encountered
+system.cpu.fetch.icacheStallCycles              10704                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          25822                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        5641                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches               2995                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          8192                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    2326                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   6715                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.Cycles                          8176                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    2307                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                   6717                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           641                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      4621                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   374                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              27680                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.937066                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.038861                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      4608                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   368                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              27606                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.935376                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.035144                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    19488     70.40%     70.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     4056     14.65%     85.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      538      1.94%     87.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      473      1.71%     88.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      725      2.62%     91.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      641      2.32%     93.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      275      0.99%     94.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      240      0.87%     95.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1244      4.49%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    19430     70.38%     70.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     4056     14.69%     85.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      538      1.95%     87.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      472      1.71%     88.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      725      2.63%     91.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      639      2.31%     93.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      274      0.99%     94.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      241      0.87%     95.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1231      4.46%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                27680                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.155947                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.715669                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    11171                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  7401                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      7541                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   189                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1378                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  24386                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1378                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    11668                       # Number of cycles rename is idle
+system.cpu.fetch.rateDist::total                27606                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.155704                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.712744                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    11125                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  7403                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      7524                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   190                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1364                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  24270                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                   1364                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    11622                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                     225                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           6686                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      7269                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   454                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  22625                       # Number of instructions processed by rename
+system.cpu.rename.serializeStallCycles           6687                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      7253                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   455                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  22509                       # Number of instructions processed by rename
 system.cpu.rename.IQFullEvents                      3                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LSQFullEvents                   135                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               20272                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 41976                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            41976                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands               20189                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 41765                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            41765                       # Number of integer rename lookups
 system.cpu.rename.CommittedMaps                 13832                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     6440                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     6357                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                639                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            632                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      2436                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 3146                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                2001                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                 7                       # Number of conflicting loads.
+system.cpu.rename.tempSerializingInsts            633                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      2443                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 3114                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1976                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                 4                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      19436                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      19328                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                 615                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     18669                       # Number of instructions issued
+system.cpu.iq.iqInstsIssued                     18581                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued                81                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            4953                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         4052                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined            4856                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         3975                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved            140                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         27680                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.674458                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.255150                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         27606                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.673078                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.254278                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               19155     69.20%     69.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                3456     12.49%     81.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                2226      8.04%     89.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1550      5.60%     95.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 660      2.38%     97.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 386      1.39%     99.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               19117     69.25%     69.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                3446     12.48%     81.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                2219      8.04%     89.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1536      5.56%     95.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 657      2.38%     97.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 384      1.39%     99.11% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                 197      0.71%     99.82% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                  41      0.15%     99.97% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   9      0.03%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           27680                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           27606                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                      35     25.18%     25.18% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     25.18% # attempts to use FU when none available
@@ -136,114 +136,114 @@ system.cpu.iq.fu_full::MemWrite                    78     56.12%    100.00% # at
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 13814     73.99%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     73.99% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2983     15.98%     89.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1872     10.03%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 13779     74.16%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     74.16% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2952     15.89%     90.04% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1850      9.96%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  18669                       # Type of FU issued
-system.cpu.iq.rate                           0.515106                       # Inst issue rate
+system.cpu.iq.FU_type_0::total                  18581                       # Type of FU issued
+system.cpu.iq.rate                           0.512876                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         139                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.007445                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              65238                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             25029                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        17501                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate                   0.007481                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              64988                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             24825                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        17429                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   0                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  0                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  18808                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  18720                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       0                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               32                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               26                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads          920                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads          888                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           32                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          553                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           28                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          528                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1378                       # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles                   1364                       # Number of cycles IEW is squashing
 system.cpu.iew.iewBlockCycles                      96                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                    10                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               21162                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts               21045                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts               247                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  3146                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2001                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts                  3114                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1976                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                615                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      2                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             32                       # Number of memory order violations
+system.cpu.iew.memOrderViolationEvents             28                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect            371                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          577                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  948                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 17934                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2892                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               735                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedNotTakenIncorrect          573                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  944                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 17855                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2862                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               726                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1111                       # number of nop insts executed
-system.cpu.iew.exec_refs                         4666                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     3968                       # Number of branches executed
-system.cpu.iew.exec_stores                       1774                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.494827                       # Inst execution rate
-system.cpu.iew.wb_sent                          17667                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         17501                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      8169                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      9773                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          1102                       # number of nop insts executed
+system.cpu.iew.exec_refs                         4620                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     3963                       # Number of branches executed
+system.cpu.iew.exec_stores                       1758                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.492837                       # Inst execution rate
+system.cpu.iew.wb_sent                          17592                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         17429                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      8123                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      9726                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.482879                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.835874                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.481079                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.835184                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts          15175                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            5911                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            5794                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             475                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               848                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        26319                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.576580                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.276701                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               847                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        26259                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.577897                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.280480                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        19114     72.62%     72.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         4004     15.21%     87.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1216      4.62%     92.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          789      3.00%     95.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          371      1.41%     96.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          322      1.22%     98.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          345      1.31%     99.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           56      0.21%     99.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          102      0.39%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        19069     72.62%     72.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         3994     15.21%     87.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1208      4.60%     92.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          790      3.01%     95.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          369      1.41%     96.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          322      1.23%     98.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          345      1.31%     99.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           57      0.22%     99.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          105      0.40%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        26319                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        26259                       # Number of insts commited each cycle
 system.cpu.commit.count                         15175                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                           3674                       # Number of memory references committed
@@ -253,48 +253,48 @@ system.cpu.commit.branches                       3359                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                     12186                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                  187                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                   102                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   105                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        46480                       # The number of ROB reads
-system.cpu.rob.rob_writes                       43556                       # The number of ROB writes
-system.cpu.timesIdled                             180                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                            8563                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        46300                       # The number of ROB reads
+system.cpu.rob.rob_writes                       43308                       # The number of ROB writes
+system.cpu.timesIdled                             181                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                            8623                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                       14449                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                 14449                       # Number of Instructions Simulated
-system.cpu.cpi                               2.508340                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.508340                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.398670                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.398670                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    28668                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   15998                       # number of integer regfile writes
-system.cpu.misc_regfile_reads                    6298                       # number of misc regfile reads
+system.cpu.cpi                               2.507371                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.507371                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.398824                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.398824                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    28557                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   15938                       # number of integer regfile writes
+system.cpu.misc_regfile_reads                    6251                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    569                       # number of misc regfile writes
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                193.254298                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     4159                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                193.216525                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     4151                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    332                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  12.527108                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  12.503012                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            193.254298                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.094362                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   4159                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    4159                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   4159                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  462                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   462                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  462                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       16041500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        16041500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       16041500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               4621                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                4621                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               4621                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.099978                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.099978                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.099978                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 34721.861472                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 34721.861472                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 34721.861472                       # average overall miss latency
+system.cpu.icache.occ_blocks::0            193.216525                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.094344                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits                   4151                       # number of ReadReq hits
+system.cpu.icache.demand_hits                    4151                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits                   4151                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  457                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   457                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  457                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       15956000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        15956000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       15956000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses               4608                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses                4608                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses               4608                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.099175                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.099175                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.099175                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 34914.660832                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 34914.660832                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 34914.660832                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -304,9 +304,9 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               130                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                130                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               130                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits               125                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                125                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               125                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses             332                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses              332                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses             332                       # number of overall MSHR misses
@@ -315,9 +315,9 @@ system.cpu.icache.ReadReq_mshr_miss_latency     11653500                       #
 system.cpu.icache.demand_mshr_miss_latency     11653500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency     11653500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.071846                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.071846                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.071846                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate     0.072049                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.072049                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.072049                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35100.903614                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 35100.903614                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 35100.903614                       # average overall mshr miss latency
@@ -326,18 +326,18 @@ system.cpu.icache.mshr_cap_events                   0                       # nu
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                102.161362                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     3736                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                102.149831                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     3712                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    146                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  25.589041                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  25.424658                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            102.161362                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.024942                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   2696                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::0            102.149831                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.024939                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits                   2672                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits                  1034                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits                      6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits                    3730                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   3730                       # number of overall hits
+system.cpu.dcache.demand_hits                    3706                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits                   3706                       # number of overall hits
 system.cpu.dcache.ReadReq_misses                  114                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses                 408                       # number of WriteReq misses
 system.cpu.dcache.demand_misses                   522                       # number of demand (read+write) misses
@@ -346,15 +346,15 @@ system.cpu.dcache.ReadReq_miss_latency        3994500                       # nu
 system.cpu.dcache.WriteReq_miss_latency      14649500                       # number of WriteReq miss cycles
 system.cpu.dcache.demand_miss_latency        18644000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency       18644000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               2810                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses               2786                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses              1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses                  6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                4252                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               4252                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.040569                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses                4228                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses               4228                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.040919                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate         0.282940                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.122766                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.122766                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate           0.123463                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.123463                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency 35039.473684                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency 35905.637255                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency 35716.475096                       # average overall miss latency
@@ -382,10 +382,10 @@ system.cpu.dcache.WriteReq_mshr_miss_latency      2985000
 system.cpu.dcache.demand_mshr_miss_latency      5226500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency      5226500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.022420                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.022613                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.057559                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.034337                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.034337                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.034532                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.034532                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35579.365079                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35963.855422                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency 35797.945205                       # average overall mshr miss latency
@@ -395,13 +395,13 @@ system.cpu.dcache.mshr_cap_events                   0                       # nu
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               228.417094                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               228.374360                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   393                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.005089                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           228.417094                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.006971                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           228.374360                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.006969                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits                     2                       # number of overall hits
index c3cdcc73a3647e215adda3ab73b96c6efbf8295b..67f90c44c597a36e4f41a2ea9642d298517c3cb0 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  8 2011 15:08:13
-gem5 started Jul  8 2011 15:22:59
+gem5 compiled Jul 18 2011 17:36:58
+gem5 started Jul 18 2011 17:37:01
 gem5 executing on u200439-lin.austin.arm.com
 command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 Global frequency set at 1000000000000 ticks per second
@@ -15,19 +15,19 @@ Init done
 [Iteration 1, Thread 3] Got lock
 [Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 1 completed
+[Iteration 2, Thread 1] Got lock
+[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 2, Thread 2] Got lock
 [Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 2 completed
-[Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 3, Thread 3] Got lock
 [Iteration 3, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 3, Thread 1] Got lock
+[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
 Iteration 3 completed
 [Iteration 4, Thread 1] Got lock
 [Iteration 4, Thread 1] Critical section done, previously next=0, now next=1
@@ -36,19 +36,19 @@ Iteration 3 completed
 [Iteration 4, Thread 3] Got lock
 [Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 4 completed
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 5, Thread 3] Got lock
 [Iteration 5, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
 Iteration 5 completed
 [Iteration 6, Thread 1] Got lock
 [Iteration 6, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 6 completed
 [Iteration 7, Thread 1] Got lock
 [Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
@@ -57,26 +57,26 @@ Iteration 6 completed
 [Iteration 7, Thread 3] Got lock
 [Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 7 completed
-[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 8, Thread 2] Got lock
+[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
 [Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 8 completed
+[Iteration 9, Thread 3] Got lock
+[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
 [Iteration 9, Thread 2] Got lock
 [Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
-[Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 9 completed
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
 [Iteration 10, Thread 1] Got lock
 [Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 10 completed
 PASSED :-)
-Exiting @ tick 104204500 because target called exit()
+Exiting @ tick 104314500 because target called exit()
index 80611aaa5041b3616d9f0a8ee59f329114041af7..30cbeea1f3246e1b30ecd49d756e56c7a4c86a12 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000104                       # Number of seconds simulated
-sim_ticks                                   104204500                       # Number of ticks simulated
+sim_ticks                                   104314500                       # Number of ticks simulated
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  98850                       # Simulator instruction rate (inst/s)
-host_tick_rate                               10137150                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 260004                       # Number of bytes of host memory used
-host_seconds                                    10.28                       # Real time elapsed on the host
-sim_insts                                     1016120                       # Number of instructions simulated
+host_inst_rate                                 102986                       # Simulator instruction rate (inst/s)
+host_tick_rate                               10543012                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263248                       # Number of bytes of host memory used
+host_seconds                                     9.89                       # Real time elapsed on the host
+sim_insts                                     1018958                       # Number of instructions simulated
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          208410                       # number of cpu cycles simulated
+system.cpu0.numCycles                          208630                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups                   80590                       # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted             78618                       # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect              1041                       # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups                79686                       # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits                   77242                       # Number of BTB hits
+system.cpu0.BPredUnit.lookups                   80647                       # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted             78658                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect              1043                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups                79786                       # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits                   77333                       # Number of BTB hits
 system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS                     414                       # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.usedRAS                     410                       # Number of times the RAS was used to get a target.
 system.cpu0.BPredUnit.RASInCorrect                132                       # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles             16537                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                        478571                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                      80590                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches             77656                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                       158025                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                   3261                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles                 12770                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.icacheStallCycles             16573                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                        478963                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                      80647                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches             77743                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                       158144                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                   3218                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles                 12869                       # Number of cycles fetch has spent blocked
 system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu0.fetch.PendingTrapStallCycles         1227                       # Number of stall cycles due to pending traps
 system.cpu0.fetch.CacheLines                     5521                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes                  450                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples            190625                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             2.510536                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.192774                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.IcacheSquashes                  447                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples            190842                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             2.509736                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.192738                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                   32600     17.10%     17.10% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                   78462     41.16%     58.26% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                     548      0.29%     58.55% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                    1030      0.54%     59.09% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                     642      0.34%     59.43% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                   74529     39.10%     98.52% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                     776      0.41%     98.93% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                     250      0.13%     99.06% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                    1788      0.94%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                   32698     17.13%     17.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                   78519     41.14%     58.28% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                     548      0.29%     58.56% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                     993      0.52%     59.08% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                     666      0.35%     59.43% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                   74596     39.09%     98.52% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                     803      0.42%     98.94% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                     245      0.13%     99.07% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                    1774      0.93%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total              190625                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.386690                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       2.296296                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                   16909                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles                14231                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                   157125                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles                  299                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                  2061                       # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts                476395                       # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles                  2061                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                   17525                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                   1226                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles         12360                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                   156835                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles                  618                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts                473886                       # Number of instructions processed by rename
+system.cpu0.fetch.rateDist::total              190842                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.386555                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       2.295753                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                   16953                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles                14325                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                   157237                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles                  303                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                  2024                       # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts                476777                       # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles                  2024                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                   17557                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                   1397                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles         12280                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                   156961                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles                  623                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts                474190                       # Number of instructions processed by rename
 system.cpu0.rename.IQFullEvents                     5                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents                  214                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands             323802                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups               945058                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups          945058                       # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps               313352                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                   10450                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts               798                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts           821                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                     3525                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads              151968                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores              76679                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads            74216                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores           74111                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                    396475                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.rename.LSQFullEvents                  220                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands             324005                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups               945716                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups          945716                       # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps               313636                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                   10369                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts               805                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts           826                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                     3607                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads              152098                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores              76745                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads            74317                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores           74189                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                    396736                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu0.iq.iqNonSpecInstsAdded                848                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                   394743                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued               99                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined           8405                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined         7242                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqInstsIssued                   395043                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued               98                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined           8301                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined         7145                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu0.iq.iqSquashedNonSpecRemoved           289                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples       190625                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        2.070783                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.085610                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::samples       190842                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        2.070000                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.087097                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0              31655     16.61%     16.61% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1               5136      2.69%     19.30% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2              75959     39.85%     59.15% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3              75246     39.47%     98.62% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4               1565      0.82%     99.44% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                775      0.41%     99.85% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6                215      0.11%     99.96% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7                 66      0.03%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0              31780     16.65%     16.65% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1               5153      2.70%     19.35% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2              75954     39.80%     59.15% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3              75299     39.46%     98.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4               1583      0.83%     99.44% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                772      0.40%     99.84% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6                222      0.12%     99.96% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7                 71      0.04%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  8      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total         190625                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total         190842                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                     35     15.42%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     15.42% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                    74     32.60%     48.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite                  118     51.98%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                     35     14.96%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     14.96% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                    80     34.19%     49.15% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite                  119     50.85%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu               166789     42.25%     42.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu               166899     42.25%     42.25% # Type of FU issued
 system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.25% # Type of FU issued
 system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.25% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.25% # Type of FU issued
@@ -165,137 +165,137 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.25% # Ty
 system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.25% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.25% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.25% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead              151686     38.43%     80.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite              76268     19.32%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead              151806     38.43%     80.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite              76338     19.32%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total                394743                       # Type of FU issued
-system.cpu0.iq.rate                          1.894069                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                        227                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.000575                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads            980437                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes           405782                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses       393268                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total                395043                       # Type of FU issued
+system.cpu0.iq.rate                          1.893510                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                        234                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.000592                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads            981260                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes           405931                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses       393580                       # Number of integer instruction queue wakeup accesses
 system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses                394970                       # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses                395277                       # Number of integer alu accesses
 system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads           73850                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads           73924                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads         1708                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.squashedLoads         1696                       # Number of loads squashed
 system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation           55                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores         1043                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation           47                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores         1038                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu0.iew.lsq.thread0.cacheBlocked           18                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                  2061                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                    862                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles                   25                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts             472051                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts              355                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts               151968                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts               76679                       # Number of dispatched store instructions
+system.cpu0.iew.iewSquashCycles                  2024                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                   1027                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles                   29                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts             472386                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts              357                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts               152098                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts               76745                       # Number of dispatched store instructions
 system.cpu0.iew.iewDispNonSpecInsts               747                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                    23                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewIQFullEvents                    27                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents            55                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect           456                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect          747                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts                1203                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts               393858                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts               151382                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts              885                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.memOrderViolationEvents            47                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect           467                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect          734                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts                1201                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts               394160                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts               151501                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts              883                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                        74728                       # number of nop insts executed
-system.cpu0.iew.exec_refs                      227540                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                   78360                       # Number of branches executed
-system.cpu0.iew.exec_stores                     76158                       # Number of stores executed
-system.cpu0.iew.exec_rate                    1.889823                       # Inst execution rate
-system.cpu0.iew.wb_sent                        393529                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                       393268                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                   233079                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                   235200                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                        74802                       # number of nop insts executed
+system.cpu0.iew.exec_refs                      227729                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                   78433                       # Number of branches executed
+system.cpu0.iew.exec_stores                     76228                       # Number of stores executed
+system.cpu0.iew.exec_rate                    1.889278                       # Inst execution rate
+system.cpu0.iew.wb_sent                        393840                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                       393580                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                   233254                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                   235363                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      1.886992                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.990982                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      1.886498                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.991039                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitCommittedInsts        462373                       # The number of committed instructions
-system.cpu0.commit.commitSquashedInsts           9639                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitCommittedInsts        462799                       # The number of committed instructions
+system.cpu0.commit.commitSquashedInsts           9548                       # The number of squashed insts skipped by commit
 system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts             1041                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples       188581                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     2.451854                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     2.134496                       # Number of insts commited each cycle
+system.cpu0.commit.branchMispredicts             1043                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples       188835                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     2.450812                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     2.134995                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0        32178     17.06%     17.06% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1        78251     41.49%     58.56% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2         2149      1.14%     59.70% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3          733      0.39%     60.09% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4          648      0.34%     60.43% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5        73572     39.01%     99.44% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6          474      0.25%     99.69% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7          279      0.15%     99.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8          297      0.16%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0        32324     17.12%     17.12% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1        78261     41.44%     58.56% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2         2190      1.16%     59.72% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3          719      0.38%     60.10% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4          660      0.35%     60.45% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5        73613     38.98%     99.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6          484      0.26%     99.69% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7          280      0.15%     99.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8          304      0.16%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total       188581                       # Number of insts commited each cycle
-system.cpu0.commit.count                       462373                       # Number of instructions committed
+system.cpu0.commit.committed_per_cycle::total       188835                       # Number of insts commited each cycle
+system.cpu0.commit.count                       462799                       # Number of instructions committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                        225896                       # Number of memory references committed
-system.cpu0.commit.loads                       150260                       # Number of loads committed
+system.cpu0.commit.refs                        226109                       # Number of memory references committed
+system.cpu0.commit.loads                       150402                       # Number of loads committed
 system.cpu0.commit.membars                         84                       # Number of memory barriers committed
-system.cpu0.commit.branches                     77524                       # Number of branches committed
+system.cpu0.commit.branches                     77595                       # Number of branches committed
 system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                   311682                       # Number of committed integer instructions.
+system.cpu0.commit.int_insts                   311966                       # Number of committed integer instructions.
 system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events                  297                       # number cycles where commit BW limit reached
+system.cpu0.commit.bw_lim_events                  304                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                      659135                       # The number of ROB reads
-system.cpu0.rob.rob_writes                     946098                       # The number of ROB writes
+system.cpu0.rob.rob_reads                      659717                       # The number of ROB reads
+system.cpu0.rob.rob_writes                     946730                       # The number of ROB writes
 system.cpu0.timesIdled                            320                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                          17785                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts                     388034                       # Number of Instructions Simulated
-system.cpu0.committedInsts_total               388034                       # Number of Instructions Simulated
-system.cpu0.cpi                              0.537092                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        0.537092                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              1.861878                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        1.861878                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                  704687                       # number of integer regfile reads
-system.cpu0.int_regfile_writes                 317694                       # number of integer regfile writes
+system.cpu0.idleCycles                          17788                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts                     388389                       # Number of Instructions Simulated
+system.cpu0.committedInsts_total               388389                       # Number of Instructions Simulated
+system.cpu0.cpi                              0.537168                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        0.537168                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              1.861616                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        1.861616                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                  705237                       # number of integer regfile reads
+system.cpu0.int_regfile_writes                 317939                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
-system.cpu0.misc_regfile_reads                 229306                       # number of misc regfile reads
+system.cpu0.misc_regfile_reads                 229506                       # number of misc regfile reads
 system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
 system.cpu0.icache.replacements                   294                       # number of replacements
-system.cpu0.icache.tagsinuse               244.310261                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                    4819                       # Total number of references to valid blocks.
+system.cpu0.icache.tagsinuse               244.353542                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                    4816                       # Total number of references to valid blocks.
 system.cpu0.icache.sampled_refs                   581                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                  8.294320                       # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs                  8.289157                       # Average number of references to valid blocks.
 system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0           244.310261                       # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0            0.477168                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits                  4819                       # number of ReadReq hits
-system.cpu0.icache.demand_hits                   4819                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits                  4819                       # number of overall hits
-system.cpu0.icache.ReadReq_misses                 702                       # number of ReadReq misses
-system.cpu0.icache.demand_misses                  702                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses                 702                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency      27601000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency       27601000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency      27601000                       # number of overall miss cycles
+system.cpu0.icache.occ_blocks::0           244.353542                       # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0            0.477253                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits                  4816                       # number of ReadReq hits
+system.cpu0.icache.demand_hits                   4816                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits                  4816                       # number of overall hits
+system.cpu0.icache.ReadReq_misses                 705                       # number of ReadReq misses
+system.cpu0.icache.demand_misses                  705                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses                 705                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency      27621000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency       27621000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency      27621000                       # number of overall miss cycles
 system.cpu0.icache.ReadReq_accesses              5521                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.demand_accesses               5521                       # number of demand (read+write) accesses
 system.cpu0.icache.overall_accesses              5521                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate         0.127151                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate          0.127151                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate         0.127151                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency 39317.663818                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency 39317.663818                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency 39317.663818                       # average overall miss latency
+system.cpu0.icache.ReadReq_miss_rate         0.127694                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate          0.127694                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate         0.127694                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency 39178.723404                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency 39178.723404                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency 39178.723404                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs        15500                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
@@ -305,67 +305,67 @@ system.cpu0.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.writebacks                       0                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits              120                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits               120                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits              120                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits              123                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits               123                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits              123                       # number of overall MSHR hits
 system.cpu0.icache.ReadReq_mshr_misses            582                       # number of ReadReq MSHR misses
 system.cpu0.icache.demand_mshr_misses             582                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.overall_mshr_misses            582                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency     21371000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency     21371000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency     21371000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency     21370500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency     21370500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency     21370500                       # number of overall MSHR miss cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_miss_rate     0.105416                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.demand_mshr_miss_rate     0.105416                       # mshr miss rate for demand accesses
 system.cpu0.icache.overall_mshr_miss_rate     0.105416                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36719.931271                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 36719.931271                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 36719.931271                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36719.072165                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 36719.072165                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 36719.072165                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements                     9                       # number of replacements
-system.cpu0.dcache.tagsinuse               139.593674                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                   95831                       # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse               139.605252                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                   97332                       # Total number of references to valid blocks.
 system.cpu0.dcache.sampled_refs                   174                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                550.752874                       # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs                559.379310                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0           140.420812                       # Average occupied blocks per context
-system.cpu0.dcache.occ_blocks::1            -0.827138                       # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0            0.274259                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_blocks::0           140.432639                       # Average occupied blocks per context
+system.cpu0.dcache.occ_blocks::1            -0.827387                       # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0            0.274282                       # Average percentage of cache occupancy
 system.cpu0.dcache.occ_percent::1           -0.001616                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits                 76983                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits                75054                       # number of WriteReq hits
+system.cpu0.dcache.ReadReq_hits                 77006                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits                75125                       # number of WriteReq hits
 system.cpu0.dcache.SwapReq_hits                    23                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits                 152037                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits                152037                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses                 495                       # number of ReadReq misses
+system.cpu0.dcache.demand_hits                 152131                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits                152131                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses                 517                       # number of ReadReq misses
 system.cpu0.dcache.WriteReq_misses                540                       # number of WriteReq misses
 system.cpu0.dcache.SwapReq_misses                  19                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses                 1035                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses                1035                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency      13943500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency     24690984                       # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency        375000                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency       38634484                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency      38634484                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses             77478                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses            75594                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_misses                 1057                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses                1057                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency      14689500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency     24684984                       # number of WriteReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency        371000                       # number of SwapReq miss cycles
+system.cpu0.dcache.demand_miss_latency       39374484                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency      39374484                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses             77523                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses            75665                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses                42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses             153072                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses            153072                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate         0.006389                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate        0.007143                       # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_accesses             153188                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses            153188                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate         0.006669                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate        0.007137                       # miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_miss_rate         0.452381                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate          0.006762                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate         0.006762                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency 28168.686869                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency 45724.044444                       # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency 19736.842105                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency 37328.003865                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency 37328.003865                       # average overall miss latency
+system.cpu0.dcache.demand_miss_rate          0.006900                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate         0.006900                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency 28412.959381                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency 45712.933333                       # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency 19526.315789                       # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency 37251.167455                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency 37251.167455                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs       180500                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
@@ -375,324 +375,324 @@ system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks                       6                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits              308                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits             369                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits               677                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits              677                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses            187                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses           171                       # number of WriteReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_hits              327                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits             368                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits               695                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits              695                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses            190                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses           172                       # number of WriteReq MSHR misses
 system.cpu0.dcache.SwapReq_mshr_misses             19                       # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses             358                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses            358                       # number of overall MSHR misses
+system.cpu0.dcache.demand_mshr_misses             362                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses            362                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency      5126500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency      5221000                       # number of ReadReq MSHR miss cycles
 system.cpu0.dcache.WriteReq_mshr_miss_latency      6255000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency       318000                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency     11381500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency     11381500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency       314000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency     11476000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency     11476000                       # number of overall MSHR miss cycles
 system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate     0.002414                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate     0.002262                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate     0.002451                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate     0.002273                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate     0.452381                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate     0.002339                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate     0.002339                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27414.438503                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36578.947368                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 16736.842105                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 31791.899441                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 31791.899441                       # average overall mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate     0.002363                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate     0.002363                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27478.947368                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36366.279070                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 16526.315789                       # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 31701.657459                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 31701.657459                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                          174065                       # number of cpu cycles simulated
+system.cpu1.numCycles                          174299                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups                   53680                       # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted             51050                       # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect              1082                       # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups                49680                       # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits                   47696                       # Number of BTB hits
+system.cpu1.BPredUnit.lookups                   52109                       # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted             49472                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect              1085                       # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups                48061                       # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits                   46077                       # Number of BTB hits
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS                     674                       # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.usedRAS                     697                       # Number of times the RAS was used to get a target.
 system.cpu1.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles             25860                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                        302062                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                      53680                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches             48370                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                       105407                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                   3162                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles                 31070                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.icacheStallCycles             26834                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                        291727                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                      52109                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches             46774                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                       102734                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                   3160                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles                 32953                       # Number of cycles fetch has spent blocked
 system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles         6439                       # Number of stall cycles due to no active thread to fetch from
+system.cpu1.fetch.NoActiveThreadStallCycles         6397                       # Number of stall cycles due to no active thread to fetch from
 system.cpu1.fetch.PendingTrapStallCycles          670                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines                    17358                       # Number of cache lines fetched
+system.cpu1.fetch.CacheLines                    18341                       # Number of cache lines fetched
 system.cpu1.fetch.IcacheSquashes                  181                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples            171455                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.761757                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.155300                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::samples            171592                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.700120                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.136214                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                   66048     38.52%     38.52% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                   53266     31.07%     69.59% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                    5206      3.04%     72.63% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                    3414      1.99%     74.62% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                     592      0.35%     74.96% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                   38163     22.26%     97.22% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                    1383      0.81%     98.03% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                     403      0.24%     98.26% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                    2980      1.74%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                   68858     40.13%     40.13% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                   52174     30.41%     70.53% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                    5705      3.32%     73.86% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                    3354      1.95%     75.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                     589      0.34%     76.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                   36150     21.07%     97.22% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                    1352      0.79%     98.01% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                     417      0.24%     98.26% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                    2993      1.74%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total              171455                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.308391                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.735340                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                   30212                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles                28102                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                   100316                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles                 4382                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                  2004                       # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts                299336                       # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles                  2004                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                   30858                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                  13502                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles         13779                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                    96392                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles                 8481                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts                297385                       # Number of instructions processed by rename
+system.cpu1.fetch.rateDist::total              171592                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.298963                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.673716                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                   31662                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles                29517                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                    97188                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles                 4829                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                  1999                       # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts                288965                       # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles                  1999                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                   32299                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                  14957                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles         13738                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                    92828                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles                 9374                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts                287067                       # Number of instructions processed by rename
 system.cpu1.rename.IQFullEvents                    26                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents                   56                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands             208391                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups               574206                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups          574206                       # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps               198747                       # Number of HB maps that are committed
+system.cpu1.rename.LSQFullEvents                   60                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands             200824                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups               551922                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups          551922                       # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps               191180                       # Number of HB maps that are committed
 system.cpu1.rename.UndoneMaps                    9644                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts              1073                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts          1204                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                    11164                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads               85765                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores              40966                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads            40880                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores           36423                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                    247992                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded               5619                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                   250090                       # Number of instructions issued
+system.cpu1.rename.serializingInsts              1080                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts          1209                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                    11997                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads               82177                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores              38952                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads            39303                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores           34405                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                    238842                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded               6064                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                   241475                       # Number of instructions issued
 system.cpu1.iq.iqSquashedInstsIssued                3                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined           8378                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined         7678                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved           648                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples       171455                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        1.458633                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.309488                       # Number of insts issued each cycle
+system.cpu1.iq.iqSquashedInstsExamined           8361                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined         7490                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved           637                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples       171592                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        1.407263                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.310082                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0              63066     36.78%     36.78% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1              20362     11.88%     48.66% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2              40913     23.86%     72.52% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3              42366     24.71%     97.23% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4               3338      1.95%     99.18% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               1156      0.67%     99.85% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6                160      0.09%     99.95% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0              65840     38.37%     38.37% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1              21732     12.66%     51.04% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2              38889     22.66%     73.70% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3              40378     23.53%     97.23% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4               3339      1.95%     99.18% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               1157      0.67%     99.85% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6                163      0.09%     99.95% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                 40      0.02%     99.97% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                 54      0.03%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total         171455                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total         171592                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                     12      4.58%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      4.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                    60     22.90%     27.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite                  190     72.52%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                     12      4.55%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      4.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                    62     23.48%     28.03% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                  190     71.97%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu               120097     48.02%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead               89434     35.76%     83.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite              40559     16.22%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu               116586     48.28%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead               86332     35.75%     84.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite              38557     15.97%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total                250090                       # Type of FU issued
-system.cpu1.iq.rate                          1.436762                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                        262                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.001048                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads            671900                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes           262020                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses       248980                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total                241475                       # Type of FU issued
+system.cpu1.iq.rate                          1.385407                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                        264                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.001093                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads            654809                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes           253298                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses       240376                       # Number of integer instruction queue wakeup accesses
 system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses                250352                       # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses                241739                       # Number of integer alu accesses
 system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           36283                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads           34273                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads         1818                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads         1784                       # Number of loads squashed
 system.cpu1.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
 system.cpu1.iew.lsq.thread0.memOrderViolation           31                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores          869                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedStores          861                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                  2004                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                   1662                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                   52                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts             295488                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts              312                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts                85765                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts               40966                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts              1034                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                    50                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles                  1999                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                   1765                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                   48                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts             285192                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts              302                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts                82177                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts               38952                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts              1043                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                    45                       # Number of times the IQ has become full, causing a stall
 system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
 system.cpu1.iew.memOrderViolationEvents            31                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect           608                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect          631                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts                1239                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts               249342                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts                84980                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts              748                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.predictedTakenIncorrect           599                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect          655                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts                1254                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts               240736                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts                81423                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts              739                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        41877                       # number of nop insts executed
-system.cpu1.iew.exec_refs                      125494                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                   50909                       # Number of branches executed
-system.cpu1.iew.exec_stores                     40514                       # Number of stores executed
-system.cpu1.iew.exec_rate                    1.432465                       # Inst execution rate
-system.cpu1.iew.wb_sent                        249148                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                       248980                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                   142220                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                   146685                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                        40286                       # number of nop insts executed
+system.cpu1.iew.exec_refs                      119940                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                   49359                       # Number of branches executed
+system.cpu1.iew.exec_stores                     38517                       # Number of stores executed
+system.cpu1.iew.exec_rate                    1.381167                       # Inst execution rate
+system.cpu1.iew.wb_sent                        240543                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                       240376                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                   136693                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                   141184                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      1.430385                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.969561                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      1.379101                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.968190                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitCommittedInsts        285859                       # The number of committed instructions
-system.cpu1.commit.commitSquashedInsts           9624                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls           4971                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts             1082                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples       163013                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     1.753596                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     2.061352                       # Number of insts commited each cycle
+system.cpu1.commit.commitCommittedInsts        275649                       # The number of committed instructions
+system.cpu1.commit.commitSquashedInsts           9533                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls           5427                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts             1085                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples       163197                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     1.689057                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     2.043019                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0        61328     37.62%     37.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1        49151     30.15%     67.77% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2         5963      3.66%     71.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3         5859      3.59%     75.03% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4         1587      0.97%     76.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5        36625     22.47%     98.47% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6          608      0.37%     98.84% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7         1052      0.65%     99.48% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8          840      0.52%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0        64641     39.61%     39.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1        47584     29.16%     68.77% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2         5957      3.65%     72.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3         6309      3.87%     76.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4         1571      0.96%     77.25% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        34599     21.20%     98.45% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6          646      0.40%     98.84% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7         1051      0.64%     99.49% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8          839      0.51%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total       163013                       # Number of insts commited each cycle
-system.cpu1.commit.count                       285859                       # Number of instructions committed
+system.cpu1.commit.committed_per_cycle::total       163197                       # Number of insts commited each cycle
+system.cpu1.commit.count                       275649                       # Number of instructions committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                        124044                       # Number of memory references committed
-system.cpu1.commit.loads                        83947                       # Number of loads committed
-system.cpu1.commit.membars                       4259                       # Number of memory barriers committed
-system.cpu1.commit.branches                     50321                       # Number of branches committed
+system.cpu1.commit.refs                        118484                       # Number of memory references committed
+system.cpu1.commit.loads                        80393                       # Number of loads committed
+system.cpu1.commit.membars                       4716                       # Number of memory barriers committed
+system.cpu1.commit.branches                     48770                       # Number of branches committed
 system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                   196488                       # Number of committed integer instructions.
+system.cpu1.commit.int_insts                   189379                       # Number of committed integer instructions.
 system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events                  840                       # number cycles where commit BW limit reached
+system.cpu1.commit.bw_lim_events                  839                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                      457069                       # The number of ROB reads
-system.cpu1.rob.rob_writes                     592971                       # The number of ROB writes
-system.cpu1.timesIdled                            229                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                           2610                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.committedInsts                     240487                       # Number of Instructions Simulated
-system.cpu1.committedInsts_total               240487                       # Number of Instructions Simulated
-system.cpu1.cpi                              0.723802                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        0.723802                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              1.381593                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        1.381593                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                  434614                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                 202365                       # number of integer regfile writes
+system.cpu1.rob.rob_reads                      446953                       # The number of ROB reads
+system.cpu1.rob.rob_writes                     572364                       # The number of ROB writes
+system.cpu1.timesIdled                            225                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                           2707                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.committedInsts                     231370                       # Number of Instructions Simulated
+system.cpu1.committedInsts_total               231370                       # Number of Instructions Simulated
+system.cpu1.cpi                              0.753334                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        0.753334                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              1.327432                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        1.327432                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                  418038                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                 194832                       # number of integer regfile writes
 system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 127051                       # number of misc regfile reads
+system.cpu1.misc_regfile_reads                 121491                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                   646                       # number of misc regfile writes
 system.cpu1.icache.replacements                   317                       # number of replacements
-system.cpu1.icache.tagsinuse                84.485339                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                   16887                       # Total number of references to valid blocks.
+system.cpu1.icache.tagsinuse                84.540462                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                   17870                       # Total number of references to valid blocks.
 system.cpu1.icache.sampled_refs                   427                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                 39.548009                       # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs                 41.850117                       # Average number of references to valid blocks.
 system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0            84.485339                       # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0            0.165010                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits                 16887                       # number of ReadReq hits
-system.cpu1.icache.demand_hits                  16887                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits                 16887                       # number of overall hits
+system.cpu1.icache.occ_blocks::0            84.540462                       # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0            0.165118                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits                 17870                       # number of ReadReq hits
+system.cpu1.icache.demand_hits                  17870                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits                 17870                       # number of overall hits
 system.cpu1.icache.ReadReq_misses                 471                       # number of ReadReq misses
 system.cpu1.icache.demand_misses                  471                       # number of demand (read+write) misses
 system.cpu1.icache.overall_misses                 471                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency       7156000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency        7156000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency       7156000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses             17358                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses              17358                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses             17358                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate         0.027134                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate          0.027134                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate         0.027134                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency 15193.205945                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency 15193.205945                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency 15193.205945                       # average overall miss latency
+system.cpu1.icache.ReadReq_miss_latency       7203000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency        7203000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency       7203000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses             18341                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses              18341                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses             18341                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate         0.025680                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate          0.025680                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate         0.025680                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency 15292.993631                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency 15292.993631                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency 15292.993631                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -709,60 +709,60 @@ system.cpu1.icache.ReadReq_mshr_misses            427                       # nu
 system.cpu1.icache.demand_mshr_misses             427                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.overall_mshr_misses            427                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency      5329000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency      5329000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency      5329000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency      5374000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency      5374000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency      5374000                       # number of overall MSHR miss cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate     0.024600                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate     0.024600                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate     0.024600                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12480.093677                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 12480.093677                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 12480.093677                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate     0.023281                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate     0.023281                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate     0.023281                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12585.480094                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 12585.480094                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 12585.480094                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                     2                       # number of replacements
-system.cpu1.dcache.tagsinuse                18.326142                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                   46034                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs               1587.379310                       # Average number of references to valid blocks.
+system.cpu1.dcache.tagsinuse                18.587934                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                   44079                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs               1469.300000                       # Average number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0            24.418432                       # Average occupied blocks per context
-system.cpu1.dcache.occ_blocks::1            -6.092290                       # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0            0.047692                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::1           -0.011899                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits                 48212                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits                39908                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits                    12                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits                  88120                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits                 88120                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses                 470                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses                123                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses                  54                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses                  593                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses                 593                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency       9944500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency      2927000                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency       1215000                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency       12871500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency      12871500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses             48682                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses            40031                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses                66                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses              88713                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses             88713                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate         0.009654                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate        0.003073                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate         0.818182                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate          0.006684                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate         0.006684                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency 21158.510638                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency 23796.747967                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency        22500                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency 21705.733558                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency 21705.733558                       # average overall miss latency
+system.cpu1.dcache.occ_blocks::0            24.401402                       # Average occupied blocks per context
+system.cpu1.dcache.occ_blocks::1            -5.813468                       # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0            0.047659                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::1           -0.011354                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits                 46657                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits                37902                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits                    13                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits                  84559                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits                 84559                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses                 478                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses                124                       # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses                  52                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses                  602                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses                 602                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency      10263500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency      2943000                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency       1147500                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency       13206500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency      13206500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses             47135                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses            38026                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses                65                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses              85161                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses             85161                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate         0.010141                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate        0.003261                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate         0.800000                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate          0.007069                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate         0.007069                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency 21471.757322                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency 23733.870968                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency 22067.307692                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency 21937.707641                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency 21937.707641                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -772,324 +772,324 @@ system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.writebacks                       1                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits              318                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits              323                       # number of ReadReq MSHR hits
 system.cpu1.dcache.WriteReq_mshr_hits              18                       # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits               336                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits              336                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses            152                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses           105                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses             54                       # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses             257                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses            257                       # number of overall MSHR misses
+system.cpu1.dcache.demand_mshr_hits               341                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits              341                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses            155                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses           106                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses             52                       # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses             261                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses            261                       # number of overall MSHR misses
 system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency      1992500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency      1603000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency      1053000                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency      3595500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency      3595500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency      2081000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency      1617000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency       991500                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency      3698000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency      3698000                       # number of overall MSHR miss cycles
 system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate     0.003122                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate     0.002623                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate     0.818182                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate     0.002897                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate     0.002897                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13108.552632                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15266.666667                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency        19500                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 13990.272374                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 13990.272374                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_mshr_miss_rate     0.003288                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate     0.002788                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate     0.800000                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate     0.003065                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate     0.003065                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13425.806452                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15254.716981                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 19067.307692                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 14168.582375                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 14168.582375                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.numCycles                          173778                       # number of cpu cycles simulated
+system.cpu2.numCycles                          174012                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.BPredUnit.lookups                   50805                       # Number of BP lookups
-system.cpu2.BPredUnit.condPredicted             48180                       # Number of conditional branches predicted
-system.cpu2.BPredUnit.condIncorrect              1153                       # Number of conditional branches incorrect
-system.cpu2.BPredUnit.BTBLookups                47027                       # Number of BTB lookups
-system.cpu2.BPredUnit.BTBHits                   44960                       # Number of BTB hits
+system.cpu2.BPredUnit.lookups                   49364                       # Number of BP lookups
+system.cpu2.BPredUnit.condPredicted             46732                       # Number of conditional branches predicted
+system.cpu2.BPredUnit.condIncorrect              1149                       # Number of conditional branches incorrect
+system.cpu2.BPredUnit.BTBLookups                45640                       # Number of BTB lookups
+system.cpu2.BPredUnit.BTBHits                   43565                       # Number of BTB hits
 system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.BPredUnit.usedRAS                     640                       # Number of times the RAS was used to get a target.
+system.cpu2.BPredUnit.usedRAS                     657                       # Number of times the RAS was used to get a target.
 system.cpu2.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
-system.cpu2.fetch.icacheStallCycles             27007                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                        283163                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                      50805                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches             45600                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                        99886                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                   3304                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles                 32566                       # Number of cycles fetch has spent blocked
+system.cpu2.fetch.icacheStallCycles             27807                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                        273927                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                      49364                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches             44222                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                        97488                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                   3286                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles                 34436                       # Number of cycles fetch has spent blocked
 system.cpu2.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles         6449                       # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles          778                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines                    18144                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                  200                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples            168765                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.677854                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.125811                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.NoActiveThreadStallCycles         6393                       # Number of stall cycles due to no active thread to fetch from
+system.cpu2.fetch.PendingTrapStallCycles          776                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.CacheLines                    19059                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                  204                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples            168964                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.621215                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.105359                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                   68879     40.81%     40.81% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                   50491     29.92%     70.73% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                    5634      3.34%     74.07% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                    3757      2.23%     76.30% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                     707      0.42%     76.71% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                   34670     20.54%     97.26% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                    1324      0.78%     98.04% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                     413      0.24%     98.29% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                    2890      1.71%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                   71476     42.30%     42.30% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                   49527     29.31%     71.61% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                    6067      3.59%     75.21% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                    3620      2.14%     77.35% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                     727      0.43%     77.78% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                   32912     19.48%     97.26% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                    1356      0.80%     98.06% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                     430      0.25%     98.31% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                    2849      1.69%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total              168765                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.292356                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.629453                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                   31662                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles                29441                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                    94497                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles                 4642                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                  2074                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts                280431                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                  2074                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                   32376                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                  14418                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles         14186                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                    90338                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles                 8924                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts                278200                       # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents                    53                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents                   43                       # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands             195247                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups               534109                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups          534109                       # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps               184829                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                   10418                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts              1050                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts          1186                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                    11541                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads               79019                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores              37409                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads            37644                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores           32854                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                    231381                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded               5925                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                   233568                       # Number of instructions issued
+system.cpu2.fetch.rateDist::total              168964                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.283682                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.574185                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                   32851                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles                30934                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                    91695                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles                 5032                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                  2059                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts                271116                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                  2059                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                   33552                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                  15710                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles         14408                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                    87161                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles                 9681                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts                268912                       # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents                    31                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents                   44                       # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands             188421                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups               514106                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups          514106                       # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps               178126                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                   10295                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts              1067                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts          1200                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                    12338                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads               75825                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores              35625                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads            36244                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores           31069                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                    223185                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded               6329                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                   225866                       # Number of instructions issued
 system.cpu2.iq.iqSquashedInstsIssued                3                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined           8776                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined         8266                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved           641                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples       168765                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.383984                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.307813                       # Number of insts issued each cycle
+system.cpu2.iq.iqSquashedInstsExamined           8708                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined         8050                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved           643                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples       168964                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.336770                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.306398                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0              66154     39.20%     39.20% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1              21382     12.67%     51.87% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2              37723     22.35%     74.22% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3              38911     23.06%     97.28% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4               3386      2.01%     99.28% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5                949      0.56%     99.85% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6                160      0.09%     99.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0              68732     40.68%     40.68% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1              22583     13.37%     54.04% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2              35943     21.27%     75.32% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3              37102     21.96%     97.28% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4               3355      1.99%     99.26% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5                981      0.58%     99.84% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6                168      0.10%     99.94% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::7                 42      0.02%     99.97% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::8                 58      0.03%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total         168765                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total         168964                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                     19      7.28%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      7.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                    52     19.92%     27.20% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                  190     72.80%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                     19      7.04%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      7.04% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                    61     22.59%     29.63% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                  190     70.37%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu               113638     48.65%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead               82927     35.50%     84.16% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite              37003     15.84%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu               110492     48.92%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.92% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead               80155     35.49%     84.41% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite              35219     15.59%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total                233568                       # Type of FU issued
-system.cpu2.iq.rate                          1.344060                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                        261                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.001117                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads            636165                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes           246114                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses       232313                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total                225866                       # Type of FU issued
+system.cpu2.iq.rate                          1.297991                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                        270                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.001195                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads            620969                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes           238254                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses       224626                       # Number of integer instruction queue wakeup accesses
 system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses                233829                       # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses                226136                       # Number of integer alu accesses
 system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads           32721                       # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads           30939                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads         1885                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.squashedLoads         1843                       # Number of loads squashed
 system.cpu2.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
 system.cpu2.iew.lsq.thread0.memOrderViolation           32                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores          861                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedStores          851                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                  2074                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                   1817                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles                   62                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts             275982                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts              400                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts                79019                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts               37409                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts               998                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                    54                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewSquashCycles                  2059                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                   1941                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles                   63                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts             266778                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts              354                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts                75825                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts               35625                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts              1017                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                    57                       # Number of times the IQ has become full, causing a stall
 system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
 system.cpu2.iew.memOrderViolationEvents            32                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect           681                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect          621                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts                1302                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts               232725                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts                78144                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts              843                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.predictedTakenIncorrect           683                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect          611                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts                1294                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts               225033                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts                74984                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts              833                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        38676                       # number of nop insts executed
-system.cpu2.iew.exec_refs                      115111                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                   47758                       # Number of branches executed
-system.cpu2.iew.exec_stores                     36967                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.339209                       # Inst execution rate
-system.cpu2.iew.wb_sent                        232494                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                       232313                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                   131935                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                   136342                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                        37264                       # number of nop insts executed
+system.cpu2.iew.exec_refs                      110168                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                   46372                       # Number of branches executed
+system.cpu2.iew.exec_stores                     35184                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.293204                       # Inst execution rate
+system.cpu2.iew.wb_sent                        224799                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                       224626                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                   127004                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                   131415                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.336838                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.967677                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.290865                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.966435                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitCommittedInsts        265754                       # The number of committed instructions
-system.cpu2.commit.commitSquashedInsts          10224                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls           5284                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts             1153                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples       160243                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.658444                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.033027                       # Number of insts commited each cycle
+system.cpu2.commit.commitCommittedInsts        256702                       # The number of committed instructions
+system.cpu2.commit.commitSquashedInsts          10072                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls           5686                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts             1149                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples       160513                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.599260                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.012930                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0        64923     40.52%     40.52% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1        46026     28.72%     69.24% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2         5970      3.73%     72.96% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3         6149      3.84%     76.80% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4         1628      1.02%     77.82% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5        33154     20.69%     98.51% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6          514      0.32%     98.83% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7         1057      0.66%     99.49% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8          822      0.51%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0        67920     42.31%     42.31% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1        44667     27.83%     70.14% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2         6005      3.74%     73.88% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3         6542      4.08%     77.96% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4         1606      1.00%     78.96% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5        31384     19.55%     98.51% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6          504      0.31%     98.83% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7         1049      0.65%     99.48% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8          836      0.52%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total       160243                       # Number of insts commited each cycle
-system.cpu2.commit.count                       265754                       # Number of instructions committed
+system.cpu2.commit.committed_per_cycle::total       160513                       # Number of insts commited each cycle
+system.cpu2.commit.count                       256702                       # Number of instructions committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                        113682                       # Number of memory references committed
-system.cpu2.commit.loads                        77134                       # Number of loads committed
-system.cpu2.commit.membars                       4565                       # Number of memory barriers committed
-system.cpu2.commit.branches                     47078                       # Number of branches committed
+system.cpu2.commit.refs                        108756                       # Number of memory references committed
+system.cpu2.commit.loads                        73982                       # Number of loads committed
+system.cpu2.commit.membars                       4966                       # Number of memory barriers committed
+system.cpu2.commit.branches                     45703                       # Number of branches committed
 system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                   182876                       # Number of committed integer instructions.
+system.cpu2.commit.int_insts                   176575                       # Number of committed integer instructions.
 system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu2.commit.bw_lim_events                  822                       # number cycles where commit BW limit reached
+system.cpu2.commit.bw_lim_events                  836                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                      434812                       # The number of ROB reads
-system.cpu2.rob.rob_writes                     554033                       # The number of ROB writes
-system.cpu2.timesIdled                            231                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                           5013                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.committedInsts                     223326                       # Number of Instructions Simulated
-system.cpu2.committedInsts_total               223326                       # Number of Instructions Simulated
-system.cpu2.cpi                              0.778136                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        0.778136                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              1.285122                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        1.285122                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                  403849                       # number of integer regfile reads
-system.cpu2.int_regfile_writes                 188623                       # number of integer regfile writes
+system.cpu2.rob.rob_reads                      425864                       # The number of ROB reads
+system.cpu2.rob.rob_writes                     535611                       # The number of ROB writes
+system.cpu2.timesIdled                            232                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                           5048                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.committedInsts                     215249                       # Number of Instructions Simulated
+system.cpu2.committedInsts_total               215249                       # Number of Instructions Simulated
+system.cpu2.cpi                              0.808422                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        0.808422                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              1.236978                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        1.236978                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                  389041                       # number of integer regfile reads
+system.cpu2.int_regfile_writes                 181914                       # number of integer regfile writes
 system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                 116687                       # number of misc regfile reads
+system.cpu2.misc_regfile_reads                 111743                       # number of misc regfile reads
 system.cpu2.misc_regfile_writes                   646                       # number of misc regfile writes
-system.cpu2.icache.replacements                   323                       # number of replacements
-system.cpu2.icache.tagsinuse                85.152335                       # Cycle average of tags in use
-system.cpu2.icache.total_refs                   17658                       # Total number of references to valid blocks.
-system.cpu2.icache.sampled_refs                   429                       # Sample count of references to valid blocks.
-system.cpu2.icache.avg_refs                 41.160839                       # Average number of references to valid blocks.
+system.cpu2.icache.replacements                   321                       # number of replacements
+system.cpu2.icache.tagsinuse                85.226905                       # Cycle average of tags in use
+system.cpu2.icache.total_refs                   18578                       # Total number of references to valid blocks.
+system.cpu2.icache.sampled_refs                   427                       # Sample count of references to valid blocks.
+system.cpu2.icache.avg_refs                 43.508197                       # Average number of references to valid blocks.
 system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::0            85.152335                       # Average occupied blocks per context
-system.cpu2.icache.occ_percent::0            0.166313                       # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits                 17658                       # number of ReadReq hits
-system.cpu2.icache.demand_hits                  17658                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits                 17658                       # number of overall hits
-system.cpu2.icache.ReadReq_misses                 486                       # number of ReadReq misses
-system.cpu2.icache.demand_misses                  486                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses                 486                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency      10409000                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency       10409000                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency      10409000                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses             18144                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses              18144                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses             18144                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate         0.026786                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate          0.026786                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate         0.026786                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency 21417.695473                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency 21417.695473                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency 21417.695473                       # average overall miss latency
+system.cpu2.icache.occ_blocks::0            85.226905                       # Average occupied blocks per context
+system.cpu2.icache.occ_percent::0            0.166459                       # Average percentage of cache occupancy
+system.cpu2.icache.ReadReq_hits                 18578                       # number of ReadReq hits
+system.cpu2.icache.demand_hits                  18578                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits                 18578                       # number of overall hits
+system.cpu2.icache.ReadReq_misses                 481                       # number of ReadReq misses
+system.cpu2.icache.demand_misses                  481                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses                 481                       # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency      10446500                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency       10446500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency      10446500                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses             19059                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses              19059                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses             19059                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate         0.025237                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate          0.025237                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate         0.025237                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency 21718.295218                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency 21718.295218                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency 21718.295218                       # average overall miss latency
 system.cpu2.icache.blocked_cycles::no_mshrs        33000                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
@@ -1099,67 +1099,67 @@ system.cpu2.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.icache.writebacks                       0                       # number of writebacks
-system.cpu2.icache.ReadReq_mshr_hits               57                       # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits                57                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits               57                       # number of overall MSHR hits
-system.cpu2.icache.ReadReq_mshr_misses            429                       # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses             429                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses            429                       # number of overall MSHR misses
+system.cpu2.icache.ReadReq_mshr_hits               54                       # number of ReadReq MSHR hits
+system.cpu2.icache.demand_mshr_hits                54                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits               54                       # number of overall MSHR hits
+system.cpu2.icache.ReadReq_mshr_misses            427                       # number of ReadReq MSHR misses
+system.cpu2.icache.demand_mshr_misses             427                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.overall_mshr_misses            427                       # number of overall MSHR misses
 system.cpu2.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu2.icache.ReadReq_mshr_miss_latency      7965500                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency      7965500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency      7965500                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency      8026500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency      8026500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency      8026500                       # number of overall MSHR miss cycles
 system.cpu2.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate     0.023644                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate     0.023644                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate     0.023644                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18567.599068                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency 18567.599068                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency 18567.599068                       # average overall mshr miss latency
+system.cpu2.icache.ReadReq_mshr_miss_rate     0.022404                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate     0.022404                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate     0.022404                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18797.423888                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency 18797.423888                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency 18797.423888                       # average overall mshr miss latency
 system.cpu2.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu2.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.dcache.replacements                     2                       # number of replacements
-system.cpu2.dcache.tagsinuse                18.333268                       # Cycle average of tags in use
-system.cpu2.dcache.total_refs                   42495                       # Total number of references to valid blocks.
-system.cpu2.dcache.sampled_refs                    31                       # Sample count of references to valid blocks.
-system.cpu2.dcache.avg_refs               1370.806452                       # Average number of references to valid blocks.
+system.cpu2.dcache.tagsinuse                19.370562                       # Cycle average of tags in use
+system.cpu2.dcache.total_refs                   40685                       # Total number of references to valid blocks.
+system.cpu2.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
+system.cpu2.dcache.avg_refs               1356.166667                       # Average number of references to valid blocks.
 system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.occ_blocks::0            26.478684                       # Average occupied blocks per context
-system.cpu2.dcache.occ_blocks::1            -8.145416                       # Average occupied blocks per context
-system.cpu2.dcache.occ_percent::0            0.051716                       # Average percentage of cache occupancy
-system.cpu2.dcache.occ_percent::1           -0.015909                       # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits                 44951                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits                36350                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits                    12                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits                  81301                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits                 81301                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses                 454                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses                125                       # number of WriteReq misses
+system.cpu2.dcache.occ_blocks::0            26.582675                       # Average occupied blocks per context
+system.cpu2.dcache.occ_blocks::1            -7.212113                       # Average occupied blocks per context
+system.cpu2.dcache.occ_percent::0            0.051919                       # Average percentage of cache occupancy
+system.cpu2.dcache.occ_percent::1           -0.014086                       # Average percentage of cache occupancy
+system.cpu2.dcache.ReadReq_hits                 43568                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits                34580                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits                    13                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits                  78148                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits                 78148                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses                 459                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses                120                       # number of WriteReq misses
 system.cpu2.dcache.SwapReq_misses                  61                       # number of SwapReq misses
 system.cpu2.dcache.demand_misses                  579                       # number of demand (read+write) misses
 system.cpu2.dcache.overall_misses                 579                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency      10292500                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency      2895500                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency       1389500                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency       13188000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency      13188000                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses             45405                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses            36475                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses                73                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses              81880                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses             81880                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate         0.009999                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate        0.003427                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate         0.835616                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate          0.007071                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate         0.007071                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency 22670.704846                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency        23164                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency 22778.688525                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency 22777.202073                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency 22777.202073                       # average overall miss latency
+system.cpu2.dcache.ReadReq_miss_latency      10996500                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency      2980500                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency       1342500                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency       13977000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency      13977000                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses             44027                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses            34700                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses                74                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses              78727                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses             78727                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate         0.010425                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate        0.003458                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate         0.824324                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate          0.007355                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate         0.007355                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency 23957.516340                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency 24837.500000                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency 22008.196721                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency 24139.896373                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency 24139.896373                       # average overall miss latency
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1169,324 +1169,324 @@ system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.dcache.writebacks                       1                       # number of writebacks
-system.cpu2.dcache.ReadReq_mshr_hits              289                       # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits              297                       # number of ReadReq MSHR hits
 system.cpu2.dcache.WriteReq_mshr_hits              18                       # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits               307                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits              307                       # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses            165                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses           107                       # number of WriteReq MSHR misses
+system.cpu2.dcache.demand_mshr_hits               315                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits              315                       # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_misses            162                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses           102                       # number of WriteReq MSHR misses
 system.cpu2.dcache.SwapReq_mshr_misses             61                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses             272                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses            272                       # number of overall MSHR misses
+system.cpu2.dcache.demand_mshr_misses             264                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses            264                       # number of overall MSHR misses
 system.cpu2.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency      2342500                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency      1563000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency      1206500                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency      3905500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency      3905500                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency      2379000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency      1660000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency      1159500                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency      4039000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency      4039000                       # number of overall MSHR miss cycles
 system.cpu2.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate     0.003634                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate     0.002934                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate     0.835616                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate     0.003322                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate     0.003322                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14196.969697                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 14607.476636                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 19778.688525                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency 14358.455882                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency 14358.455882                       # average overall mshr miss latency
+system.cpu2.dcache.ReadReq_mshr_miss_rate     0.003680                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate     0.002939                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate     0.824324                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate     0.003353                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate     0.003353                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14685.185185                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16274.509804                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 19008.196721                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency 15299.242424                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency 15299.242424                       # average overall mshr miss latency
 system.cpu2.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu2.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.numCycles                          173512                       # number of cpu cycles simulated
+system.cpu3.numCycles                          173746                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.BPredUnit.lookups                   40530                       # Number of BP lookups
-system.cpu3.BPredUnit.condPredicted             37937                       # Number of conditional branches predicted
-system.cpu3.BPredUnit.condIncorrect              1057                       # Number of conditional branches incorrect
-system.cpu3.BPredUnit.BTBLookups                36753                       # Number of BTB lookups
-system.cpu3.BPredUnit.BTBHits                   34800                       # Number of BTB hits
+system.cpu3.BPredUnit.lookups                   43971                       # Number of BP lookups
+system.cpu3.BPredUnit.condPredicted             41359                       # Number of conditional branches predicted
+system.cpu3.BPredUnit.condIncorrect              1065                       # Number of conditional branches incorrect
+system.cpu3.BPredUnit.BTBLookups                40215                       # Number of BTB lookups
+system.cpu3.BPredUnit.BTBHits                   38240                       # Number of BTB hits
 system.cpu3.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu3.BPredUnit.usedRAS                     627                       # Number of times the RAS was used to get a target.
 system.cpu3.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
-system.cpu3.fetch.icacheStallCycles             33125                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                        215867                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                      40530                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches             35427                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                        83007                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                   3046                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.BlockedCycles                 45401                       # Number of cycles fetch has spent blocked
+system.cpu3.fetch.icacheStallCycles             31228                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                        238324                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                      43971                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches             38867                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                        88896                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                   3085                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.BlockedCycles                 41810                       # Number of cycles fetch has spent blocked
 system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles         6445                       # Number of stall cycles due to no active thread to fetch from
+system.cpu3.fetch.NoActiveThreadStallCycles         6387                       # Number of stall cycles due to no active thread to fetch from
 system.cpu3.fetch.PendingTrapStallCycles          706                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines                    24871                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes                  171                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples            170604                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.265310                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            1.931210                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.CacheLines                    22959                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes                  173                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples            170976                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.393903                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.001998                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                   87597     51.35%     51.35% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                   43833     25.69%     77.04% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                    8987      5.27%     82.31% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                    3510      2.06%     84.36% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                     653      0.38%     84.75% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                   21422     12.56%     97.30% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                    1319      0.77%     98.08% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                     370      0.22%     98.29% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                    2913      1.71%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0                   82080     48.01%     48.01% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                   46270     27.06%     75.07% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                    8028      4.70%     79.76% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                    3581      2.09%     81.86% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                     661      0.39%     82.25% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                   25731     15.05%     97.29% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                    1333      0.78%     98.07% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                     378      0.22%     98.30% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                    2914      1.70%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total              170604                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.233586                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       1.244104                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                   41023                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles                38920                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                    74503                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles                 7798                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles                  1915                       # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts                213126                       # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles                  1915                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                   41660                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                  23650                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles         14461                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                    67213                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles                15260                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts                211303                       # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents                    13                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LSQFullEvents                   40                       # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RenamedOperands             145000                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups               387654                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups          387654                       # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps               135623                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                    9377                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts              1053                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts          1194                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                    17810                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads               55847                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores              24229                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads            27736                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores           19680                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                    171446                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded               9173                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                   177208                       # Number of instructions issued
+system.cpu3.fetch.rateDist::total              170976                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.253076                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       1.371680                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles                   38250                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles                36210                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                    81243                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles                 6942                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles                  1944                       # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts                235564                       # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles                  1944                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles                   38898                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles                  21197                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles         14171                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                    74835                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles                13544                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts                233632                       # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents                    34                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LSQFullEvents                   44                       # Number of times rename has blocked due to LSQ full
+system.cpu3.rename.RenamedOperands             161364                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups               435904                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups          435904                       # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps               151913                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                    9451                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts              1060                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts          1201                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                    16222                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads               63587                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores              28570                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads            31149                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores           24015                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                    191265                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded               8270                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                   196039                       # Number of instructions issued
 system.cpu3.iq.iqSquashedInstsIssued                3                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined           8093                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined         7434                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved           618                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples       170604                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        1.038710                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.248224                       # Number of insts issued each cycle
+system.cpu3.iq.iqSquashedInstsExamined           8200                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined         7610                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved           629                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples       170976                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        1.146588                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.276389                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0              84759     49.68%     49.68% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1              31065     18.21%     67.89% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2              24373     14.29%     82.18% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3              25865     15.16%     97.34% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4               3284      1.92%     99.26% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5               1031      0.60%     99.87% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6                132      0.08%     99.94% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0              79237     46.34%     46.34% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1              28336     16.57%     62.92% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2              28714     16.79%     79.71% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3              30132     17.62%     97.33% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4               3289      1.92%     99.26% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5               1034      0.60%     99.86% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6                139      0.08%     99.94% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::7                 41      0.02%     99.97% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::8                 54      0.03%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total         170604                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total         170976                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                     11      4.47%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                     0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                      0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      4.47% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                    45     18.29%     22.76% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite                  190     77.24%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                     11      4.49%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                     0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                      0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      4.49% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                    44     17.96%     22.45% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite                  190     77.55%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu                90240     50.92%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     50.92% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead               63111     35.61%     86.54% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite              23857     13.46%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu                97956     49.97%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.97% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead               69913     35.66%     85.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite              28170     14.37%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total                177208                       # Type of FU issued
-system.cpu3.iq.rate                          1.021301                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                        246                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.001388                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads            525269                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes           188741                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses       176086                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total                196039                       # Type of FU issued
+system.cpu3.iq.rate                          1.128308                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                        245                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.001250                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads            563302                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes           207766                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses       194919                       # Number of integer instruction queue wakeup accesses
 system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses                177454                       # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses                196284                       # Number of integer alu accesses
 system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads           19589                       # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads           23896                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads         1676                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.squashedLoads         1728                       # Number of loads squashed
 system.cpu3.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation           29                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores          799                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation           31                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores          841                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles                  1915                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                   1524                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles                   35                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts             209347                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts              383                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts                55847                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts               24229                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts               987                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                    33                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewSquashCycles                  1944                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                   1688                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles                   45                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts             231697                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts              366                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts                63587                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts               28570                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts               992                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
 system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents            29                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect           624                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect          548                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts                1172                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts               176425                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts                55052                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts              783                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents            31                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect           631                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect          549                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts                1180                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts               195258                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts                62772                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts              781                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        28728                       # number of nop insts executed
-system.cpu3.iew.exec_refs                       78879                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                   37783                       # Number of branches executed
-system.cpu3.iew.exec_stores                     23827                       # Number of stores executed
-system.cpu3.iew.exec_rate                    1.016788                       # Inst execution rate
-system.cpu3.iew.wb_sent                        176246                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                       176086                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                    95644                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                    99967                       # num instructions consuming a value
+system.cpu3.iew.exec_nop                        32162                       # number of nop insts executed
+system.cpu3.iew.exec_refs                       90911                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                   41188                       # Number of branches executed
+system.cpu3.iew.exec_stores                     28139                       # Number of stores executed
+system.cpu3.iew.exec_rate                    1.123813                       # Inst execution rate
+system.cpu3.iew.wb_sent                        195076                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                       194919                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                   107666                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                   111983                       # num instructions consuming a value
 system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate                      1.014835                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.956756                       # average fanout of values written-back
+system.cpu3.iew.wb_rate                      1.121862                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.961450                       # average fanout of values written-back
 system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitCommittedInsts        200126                       # The number of committed instructions
-system.cpu3.commit.commitSquashedInsts           9211                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls           8555                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts             1057                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples       162245                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     1.233480                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     1.839252                       # Number of insts commited each cycle
+system.cpu3.commit.commitCommittedInsts        222278                       # The number of committed instructions
+system.cpu3.commit.commitSquashedInsts           9409                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls           7641                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts             1065                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples       162646                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     1.366637                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     1.912094                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0        86736     53.46%     53.46% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1        36031     22.21%     75.67% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2         6002      3.70%     79.37% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3         9421      5.81%     85.17% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4         1631      1.01%     86.18% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5        19977     12.31%     98.49% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6          548      0.34%     98.83% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0        80351     49.40%     49.40% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1        39427     24.24%     73.64% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2         6019      3.70%     77.34% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3         8502      5.23%     82.57% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4         1632      1.00%     83.57% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5        24254     14.91%     98.49% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6          559      0.34%     98.83% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::7         1061      0.65%     99.48% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8          838      0.52%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8          841      0.52%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total       162245                       # Number of insts commited each cycle
-system.cpu3.commit.count                       200126                       # Number of instructions committed
+system.cpu3.commit.committed_per_cycle::total       162646                       # Number of insts commited each cycle
+system.cpu3.commit.count                       222278                       # Number of instructions committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                         77601                       # Number of memory references committed
-system.cpu3.commit.loads                        54171                       # Number of loads committed
-system.cpu3.commit.membars                       7839                       # Number of memory barriers committed
-system.cpu3.commit.branches                     37226                       # Number of branches committed
+system.cpu3.commit.refs                         89588                       # Number of memory references committed
+system.cpu3.commit.loads                        61859                       # Number of loads committed
+system.cpu3.commit.membars                       6925                       # Number of memory barriers committed
+system.cpu3.commit.branches                     40615                       # Number of branches committed
 system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                   136949                       # Number of committed integer instructions.
+system.cpu3.commit.int_insts                   152323                       # Number of committed integer instructions.
 system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu3.commit.bw_lim_events                  838                       # number cycles where commit BW limit reached
+system.cpu3.commit.bw_lim_events                  841                       # number cycles where commit BW limit reached
 system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu3.rob.rob_reads                      370157                       # The number of ROB reads
-system.cpu3.rob.rob_writes                     420591                       # The number of ROB writes
-system.cpu3.timesIdled                            233                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                           2908                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.committedInsts                     164273                       # Number of Instructions Simulated
-system.cpu3.committedInsts_total               164273                       # Number of Instructions Simulated
-system.cpu3.cpi                              1.056242                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        1.056242                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              0.946753                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        0.946753                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                  294835                       # number of integer regfile reads
-system.cpu3.int_regfile_writes                 139001                       # number of integer regfile writes
+system.cpu3.rob.rob_reads                      392905                       # The number of ROB reads
+system.cpu3.rob.rob_writes                     465320                       # The number of ROB writes
+system.cpu3.timesIdled                            234                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                           2770                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.committedInsts                     183950                       # Number of Instructions Simulated
+system.cpu3.committedInsts_total               183950                       # Number of Instructions Simulated
+system.cpu3.cpi                              0.944528                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        0.944528                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              1.058729                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        1.058729                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads                  330902                       # number of integer regfile reads
+system.cpu3.int_regfile_writes                 155336                       # number of integer regfile writes
 system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu3.misc_regfile_reads                  80433                       # number of misc regfile reads
+system.cpu3.misc_regfile_reads                  92466                       # number of misc regfile reads
 system.cpu3.misc_regfile_writes                   646                       # number of misc regfile writes
 system.cpu3.icache.replacements                   318                       # number of replacements
-system.cpu3.icache.tagsinuse                80.013522                       # Cycle average of tags in use
-system.cpu3.icache.total_refs                   24405                       # Total number of references to valid blocks.
+system.cpu3.icache.tagsinuse                80.005311                       # Cycle average of tags in use
+system.cpu3.icache.total_refs                   22493                       # Total number of references to valid blocks.
 system.cpu3.icache.sampled_refs                   426                       # Sample count of references to valid blocks.
-system.cpu3.icache.avg_refs                 57.288732                       # Average number of references to valid blocks.
+system.cpu3.icache.avg_refs                 52.800469                       # Average number of references to valid blocks.
 system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::0            80.013522                       # Average occupied blocks per context
-system.cpu3.icache.occ_percent::0            0.156276                       # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits                 24405                       # number of ReadReq hits
-system.cpu3.icache.demand_hits                  24405                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits                 24405                       # number of overall hits
+system.cpu3.icache.occ_blocks::0            80.005311                       # Average occupied blocks per context
+system.cpu3.icache.occ_percent::0            0.156260                       # Average percentage of cache occupancy
+system.cpu3.icache.ReadReq_hits                 22493                       # number of ReadReq hits
+system.cpu3.icache.demand_hits                  22493                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits                 22493                       # number of overall hits
 system.cpu3.icache.ReadReq_misses                 466                       # number of ReadReq misses
 system.cpu3.icache.demand_misses                  466                       # number of demand (read+write) misses
 system.cpu3.icache.overall_misses                 466                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency       6656500                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency        6656500                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency       6656500                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses             24871                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses              24871                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses             24871                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate         0.018737                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate          0.018737                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate         0.018737                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency 14284.334764                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency 14284.334764                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency 14284.334764                       # average overall miss latency
+system.cpu3.icache.ReadReq_miss_latency       6527000                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency        6527000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency       6527000                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses             22959                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses              22959                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses             22959                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate         0.020297                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate          0.020297                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate         0.020297                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency 14006.437768                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency 14006.437768                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency 14006.437768                       # average overall miss latency
 system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1503,60 +1503,60 @@ system.cpu3.icache.ReadReq_mshr_misses            426                       # nu
 system.cpu3.icache.demand_mshr_misses             426                       # number of demand (read+write) MSHR misses
 system.cpu3.icache.overall_mshr_misses            426                       # number of overall MSHR misses
 system.cpu3.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu3.icache.ReadReq_mshr_miss_latency      4959000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency      4959000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency      4959000                       # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency      4833500                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency      4833500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency      4833500                       # number of overall MSHR miss cycles
 system.cpu3.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate     0.017128                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate     0.017128                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate     0.017128                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11640.845070                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency 11640.845070                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency 11640.845070                       # average overall mshr miss latency
+system.cpu3.icache.ReadReq_mshr_miss_rate     0.018555                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate     0.018555                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate     0.018555                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11346.244131                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency 11346.244131                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency 11346.244131                       # average overall mshr miss latency
 system.cpu3.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu3.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.dcache.replacements                     2                       # number of replacements
-system.cpu3.dcache.tagsinuse                15.701328                       # Cycle average of tags in use
-system.cpu3.dcache.total_refs                   29297                       # Total number of references to valid blocks.
+system.cpu3.dcache.tagsinuse                13.455114                       # Cycle average of tags in use
+system.cpu3.dcache.total_refs                   33581                       # Total number of references to valid blocks.
 system.cpu3.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
-system.cpu3.dcache.avg_refs               1010.241379                       # Average number of references to valid blocks.
+system.cpu3.dcache.avg_refs               1157.965517                       # Average number of references to valid blocks.
 system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.occ_blocks::0            23.466885                       # Average occupied blocks per context
-system.cpu3.dcache.occ_blocks::1            -7.765557                       # Average occupied blocks per context
-system.cpu3.dcache.occ_percent::0            0.045834                       # Average percentage of cache occupancy
-system.cpu3.dcache.occ_percent::1           -0.015167                       # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits                 35023                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits                23239                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits                    16                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits                  58262                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits                 58262                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses                 421                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses                121                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses                  54                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses                  542                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses                 542                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency       8723500                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency      2943500                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency       1375000                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency       11667000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency      11667000                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses             35444                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses            23360                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.occ_blocks::0            23.407144                       # Average occupied blocks per context
+system.cpu3.dcache.occ_blocks::1            -9.952030                       # Average occupied blocks per context
+system.cpu3.dcache.occ_percent::0            0.045717                       # Average percentage of cache occupancy
+system.cpu3.dcache.occ_percent::1           -0.019438                       # Average percentage of cache occupancy
+system.cpu3.dcache.ReadReq_hits                 38409                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits                27534                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits                    14                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits                  65943                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits                 65943                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses                 448                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses                125                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses                  56                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses                  573                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses                 573                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency       9358000                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency      2911000                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency       1350500                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency       12269000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency      12269000                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses             38857                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses            27659                       # number of WriteReq accesses(hits+misses)
 system.cpu3.dcache.SwapReq_accesses                70                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses              58804                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses             58804                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate         0.011878                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate        0.005180                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate         0.771429                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate          0.009217                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate         0.009217                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency 20720.902613                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency 24326.446281                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency 25462.962963                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency 21525.830258                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency 21525.830258                       # average overall miss latency
+system.cpu3.dcache.demand_accesses              66516                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses             66516                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate         0.011529                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate        0.004519                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate         0.800000                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate          0.008614                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate         0.008614                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency 20888.392857                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency        23288                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency 24116.071429                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency 21411.867365                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency 21411.867365                       # average overall miss latency
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1566,80 +1566,80 @@ system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.dcache.writebacks                       1                       # number of writebacks
-system.cpu3.dcache.ReadReq_mshr_hits              256                       # number of ReadReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits              19                       # number of WriteReq MSHR hits
-system.cpu3.dcache.demand_mshr_hits               275                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.overall_mshr_hits              275                       # number of overall MSHR hits
-system.cpu3.dcache.ReadReq_mshr_misses            165                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses           102                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses             54                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses             267                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses            267                       # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_hits              279                       # number of ReadReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits              17                       # number of WriteReq MSHR hits
+system.cpu3.dcache.demand_mshr_hits               296                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.overall_mshr_hits              296                       # number of overall MSHR hits
+system.cpu3.dcache.ReadReq_mshr_misses            169                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses           108                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses             56                       # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses             277                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses            277                       # number of overall MSHR misses
 system.cpu3.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency      2157000                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency      1669000                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency      1213000                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency      3826000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency      3826000                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency      2218000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency      1624500                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency      1182500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency      3842500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency      3842500                       # number of overall MSHR miss cycles
 system.cpu3.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate     0.004655                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate     0.004366                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate     0.771429                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate     0.004541                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate     0.004541                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13072.727273                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 16362.745098                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22462.962963                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency 14329.588015                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency 14329.588015                       # average overall mshr miss latency
+system.cpu3.dcache.ReadReq_mshr_miss_rate     0.004349                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate     0.003905                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate     0.800000                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate     0.004164                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate     0.004164                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13124.260355                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15041.666667                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 21116.071429                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency 13871.841155                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency 13871.841155                       # average overall mshr miss latency
 system.cpu3.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu3.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.replacements                             0                       # number of replacements
-system.l2c.tagsinuse                       428.144160                       # Cycle average of tags in use
-system.l2c.total_refs                            1448                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                       428.230348                       # Cycle average of tags in use
+system.l2c.total_refs                            1446                       # Total number of references to valid blocks.
 system.l2c.sampled_refs                           527                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          2.747628                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          2.743833                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                   347.119372                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                    10.560700                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                    63.080596                       # Average occupied blocks per context
-system.l2c.occ_blocks::3                     2.422702                       # Average occupied blocks per context
-system.l2c.occ_blocks::4                     4.960789                       # Average occupied blocks per context
+system.l2c.occ_blocks::0                   347.173687                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                    11.269498                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                    63.254207                       # Average occupied blocks per context
+system.l2c.occ_blocks::3                     1.567246                       # Average occupied blocks per context
+system.l2c.occ_blocks::4                     4.965709                       # Average occupied blocks per context
 system.l2c.occ_percent::0                    0.005297                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.000161                       # Average percentage of cache occupancy
-system.l2c.occ_percent::2                    0.000963                       # Average percentage of cache occupancy
-system.l2c.occ_percent::3                    0.000037                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.000172                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.000965                       # Average percentage of cache occupancy
+system.l2c.occ_percent::3                    0.000024                       # Average percentage of cache occupancy
 system.l2c.occ_percent::4                    0.000076                       # Average percentage of cache occupancy
 system.l2c.ReadReq_hits::0                        233                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                        425                       # number of ReadReq hits
-system.l2c.ReadReq_hits::2                        360                       # number of ReadReq hits
-system.l2c.ReadReq_hits::3                        433                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                   1451                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                        424                       # number of ReadReq hits
+system.l2c.ReadReq_hits::2                        356                       # number of ReadReq hits
+system.l2c.ReadReq_hits::3                        436                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                   1449                       # number of ReadReq hits
 system.l2c.Writeback_hits::0                        9                       # number of Writeback hits
 system.l2c.Writeback_hits::total                    9                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::0                       3                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
 system.l2c.demand_hits::0                         233                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                         425                       # number of demand (read+write) hits
-system.l2c.demand_hits::2                         360                       # number of demand (read+write) hits
-system.l2c.demand_hits::3                         433                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                    1451                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                         424                       # number of demand (read+write) hits
+system.l2c.demand_hits::2                         356                       # number of demand (read+write) hits
+system.l2c.demand_hits::3                         436                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                    1449                       # number of demand (read+write) hits
 system.l2c.overall_hits::0                        233                       # number of overall hits
-system.l2c.overall_hits::1                        425                       # number of overall hits
-system.l2c.overall_hits::2                        360                       # number of overall hits
-system.l2c.overall_hits::3                        433                       # number of overall hits
-system.l2c.overall_hits::total                   1451                       # number of overall hits
+system.l2c.overall_hits::1                        424                       # number of overall hits
+system.l2c.overall_hits::2                        356                       # number of overall hits
+system.l2c.overall_hits::3                        436                       # number of overall hits
+system.l2c.overall_hits::total                   1449                       # number of overall hits
 system.l2c.ReadReq_misses::0                      429                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                       15                       # number of ReadReq misses
-system.l2c.ReadReq_misses::2                       83                       # number of ReadReq misses
-system.l2c.ReadReq_misses::3                        6                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                       16                       # number of ReadReq misses
+system.l2c.ReadReq_misses::2                       85                       # number of ReadReq misses
+system.l2c.ReadReq_misses::3                        3                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total                  533                       # number of ReadReq misses
 system.l2c.UpgradeReq_misses::0                    21                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                    23                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::2                    19                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::3                    24                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1                    22                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::2                    22                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::3                    22                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total                87                       # number of UpgradeReq misses
 system.l2c.ReadExReq_misses::0                     94                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::1                     12                       # number of ReadExReq misses
@@ -1647,31 +1647,31 @@ system.l2c.ReadExReq_misses::2                     13                       # nu
 system.l2c.ReadExReq_misses::3                     12                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
 system.l2c.demand_misses::0                       523                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                        27                       # number of demand (read+write) misses
-system.l2c.demand_misses::2                        96                       # number of demand (read+write) misses
-system.l2c.demand_misses::3                        18                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                        28                       # number of demand (read+write) misses
+system.l2c.demand_misses::2                        98                       # number of demand (read+write) misses
+system.l2c.demand_misses::3                        15                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                   664                       # number of demand (read+write) misses
 system.l2c.overall_misses::0                      523                       # number of overall misses
-system.l2c.overall_misses::1                       27                       # number of overall misses
-system.l2c.overall_misses::2                       96                       # number of overall misses
-system.l2c.overall_misses::3                       18                       # number of overall misses
+system.l2c.overall_misses::1                       28                       # number of overall misses
+system.l2c.overall_misses::2                       98                       # number of overall misses
+system.l2c.overall_misses::3                       15                       # number of overall misses
 system.l2c.overall_misses::total                  664                       # number of overall misses
-system.l2c.ReadReq_miss_latency              27698500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency              27701000                       # number of ReadReq miss cycles
 system.l2c.UpgradeReq_miss_latency             157500                       # number of UpgradeReq miss cycles
 system.l2c.ReadExReq_miss_latency             6878000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency               34576500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency              34576500                       # number of overall miss cycles
+system.l2c.demand_miss_latency               34579000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency              34579000                       # number of overall miss cycles
 system.l2c.ReadReq_accesses::0                    662                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::1                    440                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::2                    443                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::2                    441                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::3                    439                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               1984                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total               1982                       # number of ReadReq accesses(hits+misses)
 system.l2c.Writeback_accesses::0                    9                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total                9                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::0                  24                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1                  23                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::2                  19                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::3                  24                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1                  22                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::2                  22                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::3                  22                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total              90                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::0                   94                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::1                   12                       # number of ReadExReq accesses(hits+misses)
@@ -1680,19 +1680,19 @@ system.l2c.ReadExReq_accesses::3                   12                       # nu
 system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
 system.l2c.demand_accesses::0                     756                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::1                     452                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::2                     456                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::2                     454                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::3                     451                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                2115                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total                2113                       # number of demand (read+write) accesses
 system.l2c.overall_accesses::0                    756                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                    452                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::2                    456                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::2                    454                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::3                    451                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               2115                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total               2113                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::0              0.648036                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.034091                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2              0.187359                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::3              0.013667                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.883154                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.036364                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::2              0.192744                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::3              0.006834                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.883977                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::0           0.875000                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::1                  1                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::2                  1                       # miss rate for UpgradeReq accesses
@@ -1704,40 +1704,40 @@ system.l2c.ReadExReq_miss_rate::2                   1                       # mi
 system.l2c.ReadExReq_miss_rate::3                   1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::total               4                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::0               0.691799                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.059735                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::2               0.210526                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::3               0.039911                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           1.001971                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.061947                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::2               0.215859                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::3               0.033259                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           1.002864                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::0              0.691799                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.059735                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::2              0.210526                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::3              0.039911                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          1.001971                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   64565.268065                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   1846566.666667                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2   333716.867470                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::3   4616416.666667                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 6861265.468868                       # average ReadReq miss latency
+system.l2c.overall_miss_rate::1              0.061947                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::2              0.215859                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::3              0.033259                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          1.002864                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0   64571.095571                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   1731312.500000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::2   325894.117647                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::3   9233666.666667                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 11355444.379885                       # average ReadReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::0         7500                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1  6847.826087                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2  8289.473684                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::3  6562.500000                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 29199.799771                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1  7159.090909                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::2  7159.090909                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::3  7159.090909                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 28977.272727                       # average UpgradeReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::0 73170.212766                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::1 573166.666667                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::2 529076.923077                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::3 573166.666667                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::total 1748580.469176                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    66111.854685                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    1280611.111111                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::2    360171.875000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::3    1920916.666667                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 3627811.507462                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   66111.854685                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   1280611.111111                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::2   360171.875000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::3   1920916.666667                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 3627811.507462                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::0    66116.634799                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    1234964.285714                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::2    352846.938776                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::3    2305266.666667                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 3959194.525956                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0   66116.634799                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   1234964.285714                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::2   352846.938776                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::3   2305266.666667                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 3959194.525956                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1764,14 +1764,14 @@ system.l2c.overall_mshr_miss_latency         26272500                       # nu
 system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_miss_rate::0         0.793051                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::1         1.193182                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::2         1.185102                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::2         1.190476                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::3         1.195900                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     4.367235                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     4.372609                       # mshr miss rate for ReadReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::0      3.625000                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1      3.782609                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::2      4.578947                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::3      3.625000                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total    15.611556                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1      3.954545                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::2      3.954545                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::3      3.954545                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total    15.488636                       # mshr miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::0       1.393617                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::1      10.916667                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::2      10.076923                       # mshr miss rate for ReadExReq accesses
@@ -1779,14 +1779,14 @@ system.l2c.ReadExReq_mshr_miss_rate::3      10.916667                       # ms
 system.l2c.ReadExReq_mshr_miss_rate::total    33.303873                       # mshr miss rate for ReadExReq accesses
 system.l2c.demand_mshr_miss_rate::0          0.867725                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::1          1.451327                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2          1.438596                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2          1.444934                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::3          1.454545                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      5.212194                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      5.218532                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::0         0.867725                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::1         1.451327                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2         1.438596                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2         1.444934                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::3         1.454545                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     5.212194                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     5.218532                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency 39987.619048                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency 40297.709924                       # average ReadExReq mshr miss latency