amdgpu/addrlib: add disableLinearOpt flag

diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h
index 764377a4b479b476ddac649886c622e46f3904b6..c6c46845fd5c1b86238ddd6e64c03fdea39eb921 100644 (file)
--- a/src/amd/addrlib/addrinterface.h
+++ b/src/amd/addrlib/addrinterface.h
@@ -446,7 +446,8 @@ typedef union _ADDR_SURFACE_FLAGS
                                      ///  This flag indicates we need to follow the alignment with
                                      ///  CZ families or other ASICs under PX configuration + CZ.
         UINT_32 nonSplit        : 1; ///< CI: depth texture should not be split
-        UINT_32 reserved        : 10; ///< Reserved bits
+        UINT_32 disableLinearOpt: 1; ///< Disable tile mode optimization to linear
+        UINT_32 reserved        : 9; ///< Reserved bits
     };
 
     UINT_32 value;

diff --git a/src/amd/addrlib/core/addrcommon.h b/src/amd/addrlib/core/addrcommon.h
index 88cbad0b3ba3957015900aa60ea053bcb7f2910d..60b3d818f72da1177d3aac16d9b5159163ed8b3b 100644 (file)
--- a/src/amd/addrlib/core/addrcommon.h
+++ b/src/amd/addrlib/core/addrcommon.h
@@ -133,7 +133,8 @@ union ADDR_CONFIG_FLAGS
         UINT_32 checkLast2DLevel       : 1;    ///< Check the last 2D mip sub level
         UINT_32 useHtileSliceAlign     : 1;    ///< Do htile single slice alignment
         UINT_32 allowLargeThickTile    : 1;    ///< Allow 64*thickness*bytesPerPixel > rowSize
-        UINT_32 reserved               : 23;   ///< Reserved bits for future use
+        UINT_32 disableLinearOpt       : 1;    ///< Disallow tile modes to be optimized to linear
+        UINT_32 reserved               : 22;   ///< Reserved bits for future use
     };
 
     UINT_32 value;

diff --git a/src/amd/addrlib/core/addrlib.cpp b/src/amd/addrlib/core/addrlib.cpp
index 4804b0d79d94a46b8804b3c50e8392b6e2ade3c1..f1a9fcbe30afc21d67e887b7c0e1fd1d97b508d1 100644 (file)
--- a/src/amd/addrlib/core/addrlib.cpp
+++ b/src/amd/addrlib/core/addrlib.cpp
@@ -265,6 +265,7 @@ ADDR_E_RETURNCODE AddrLib::Create(
         pLib->m_configFlags.checkLast2DLevel    = pCreateIn->createFlags.checkLast2DLevel;
         pLib->m_configFlags.useHtileSliceAlign  = pCreateIn->createFlags.useHtileSliceAlign;
         pLib->m_configFlags.allowLargeThickTile = pCreateIn->createFlags.allowLargeThickTile;
+        pLib->m_configFlags.disableLinearOpt    = FALSE;
 
         pLib->SetAddrChipFamily(pCreateIn->chipFamily, pCreateIn->chipRevision);
 
@@ -3554,7 +3555,9 @@ BOOL_32 AddrLib::OptimizeTileMode(
             (IsLinear(tileMode) == FALSE) &&
             (AddrElemLib::IsBlockCompressed(pIn->format) == FALSE) &&
             (pIn->flags.depth == FALSE) &&
-            (pIn->flags.stencil == FALSE))
+            (pIn->flags.stencil == FALSE) &&
+            (m_configFlags.disableLinearOpt == FALSE) &&
+            (pIn->flags.disableLinearOpt == FALSE))
         {
             tileMode = ADDR_TM_LINEAR_ALIGNED;
         }