re PR target/78577 (Fix define_insn operand types for vexturhlx, vexturhrx, vextuwlx...

gcc/ChangeLog:

2016-12-01  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	PR target/78577
	* config/rs6000/vsx.md (vextuhlx): Revise mode of operand 2.
	(vextuhrx): Likewise.
	(vextuwlx): Likewise.
	(vextuwrx): Likewise.

From-SVN: r243141

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b23481f457e3ed44e07b02a393a847002827914e..7f9dd0e2ed2f7d77d53d1fdab3b17f620e5551fc 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2016-12-01  Kelvin Nilsen  <kelvin@gcc.gnu.org>
+
+       PR target/78577
+       * config/rs6000/vsx.md (vextuhlx): Revise mode of operand 2.
+       (vextuhrx): Likewise.
+       (vextuwlx): Likewise.
+       (vextuwrx): Likewise.
+
 2016-12-01  David Malcolm  <dmalcolm@redhat.com>
 
        * dwarf2out.c (dwarf2out_c_finalize): Reset early_dwarf and

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 01d275d168e5a37e7438a9730260125b67ccaeda..1801bc05906396ba09374da41d2552b3ba6daca6 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3648,7 +3648,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
        (unspec:SI
         [(match_operand:SI 1 "register_operand" "r")
-         (match_operand:V16QI 2 "altivec_register_operand" "v")]
+         (match_operand:V8HI 2 "altivec_register_operand" "v")]
         UNSPEC_VEXTUHLX))]
   "TARGET_P9_VECTOR"
   "vextuhlx %0,%1,%2"
@@ -3659,7 +3659,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
        (unspec:SI
         [(match_operand:SI 1 "register_operand" "r")
-         (match_operand:V16QI 2 "altivec_register_operand" "v")]
+         (match_operand:V8HI 2 "altivec_register_operand" "v")]
         UNSPEC_VEXTUHRX))]
   "TARGET_P9_VECTOR"
   "vextuhrx %0,%1,%2"
@@ -3670,7 +3670,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
        (unspec:SI
         [(match_operand:SI 1 "register_operand" "r")
-         (match_operand:V16QI 2 "altivec_register_operand" "v")]
+         (match_operand:V4SI 2 "altivec_register_operand" "v")]
         UNSPEC_VEXTUWLX))]
   "TARGET_P9_VECTOR"
   "vextuwlx %0,%1,%2"
@@ -3681,7 +3681,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
        (unspec:SI
         [(match_operand:SI 1 "register_operand" "r")
-         (match_operand:V16QI 2 "altivec_register_operand" "v")]
+         (match_operand:V4SI 2 "altivec_register_operand" "v")]
         UNSPEC_VEXTUWRX))]
   "TARGET_P9_VECTOR"
   "vextuwrx %0,%1,%2"