strcpy(name->sysname, "Linux");
strcpy(name->nodename, "m5.eecs.umich.edu");
- strcpy(name->release, "2.4.20");
+ strcpy(name->release, "2.6.26");
strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
strcpy(name->machine, "alpha");
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/process.hh"
#include "base/loader/object_file.hh"
+#include "base/loader/elf_object.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
+#include "mem/page_table.hh"
+#include "sim/process_impl.hh"
#include "sim/system.hh"
using namespace AlphaISA;
// Set pointer for next thread stack. Reserve 8M for main stack.
next_thread_stack_base = stack_base - (8 * 1024 * 1024);
+}
+
+void
+AlphaLiveProcess::argsInit(int intSize, int pageSize)
+{
+ objFile->loadSections(initVirtMem);
+
+ typedef M5_auxv_t<uint64_t> auxv_t;
+ std::vector<auxv_t> auxv;
+
+ ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
+ if(elfObject)
+ {
+ // modern glibc uses a bunch of auxiliary vectors to set up
+ // TLS as well as do a bunch of other stuff
+ // these vectors go on the bottom of the stack, below argc/argv/envp
+ // pointers but above actual arg strings
+ // I don't have all the ones glibc looks at here, but so far it doesn't
+ // seem to be a problem.
+ // check out _dl_aux_init() in glibc/elf/dl-support.c for details
+ // --Lisa
+ auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::VMPageSize));
+ auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
+ auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
+ DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable());
+ auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
+ auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
+ auxv.push_back(auxv_t(M5_AT_UID, uid()));
+ auxv.push_back(auxv_t(M5_AT_EUID, euid()));
+ auxv.push_back(auxv_t(M5_AT_GID, gid()));
+ auxv.push_back(auxv_t(M5_AT_EGID, egid()));
+
+ }
+
+ // Calculate how much space we need for arg & env & auxv arrays.
+ int argv_array_size = intSize * (argv.size() + 1);
+ int envp_array_size = intSize * (envp.size() + 1);
+ int auxv_array_size = intSize * 2 * (auxv.size() + 1);
+
+ int arg_data_size = 0;
+ for (int i = 0; i < argv.size(); ++i) {
+ arg_data_size += argv[i].size() + 1;
+ }
+ int env_data_size = 0;
+ for (int i = 0; i < envp.size(); ++i) {
+ env_data_size += envp[i].size() + 1;
+ }
+
+ int space_needed =
+ argv_array_size +
+ envp_array_size +
+ auxv_array_size +
+ arg_data_size +
+ env_data_size;
+
+ if (space_needed < 32*1024)
+ space_needed = 32*1024;
+
+ // set bottom of stack
+ stack_min = stack_base - space_needed;
+ // align it
+ stack_min = roundDown(stack_min, pageSize);
+ stack_size = stack_base - stack_min;
+ // map memory
+ pTable->allocate(stack_min, roundUp(stack_size, pageSize));
+
+ // map out initial stack contents
+ Addr argv_array_base = stack_min + intSize; // room for argc
+ Addr envp_array_base = argv_array_base + argv_array_size;
+ Addr auxv_array_base = envp_array_base + envp_array_size;
+ Addr arg_data_base = auxv_array_base + auxv_array_size;
+ Addr env_data_base = arg_data_base + arg_data_size;
+
+ // write contents to stack
+ uint64_t argc = argv.size();
+ if (intSize == 8)
+ argc = htog((uint64_t)argc);
+ else if (intSize == 4)
+ argc = htog((uint32_t)argc);
+ else
+ panic("Unknown int size");
+
+ initVirtMem->writeBlob(stack_min, (uint8_t*)&argc, intSize);
+
+ copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
+ copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
+
+ //Copy the aux stuff
+ for(int x = 0; x < auxv.size(); x++)
+ {
+ initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize,
+ (uint8_t*)&(auxv[x].a_type), intSize);
+ initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
+ (uint8_t*)&(auxv[x].a_val), intSize);
+ }
+
+ assert(NumArgumentRegs >= 2);
+
+ ThreadContext *tc = system->getThreadContext(contextIds[0]);
+
+ tc->setIntReg(ArgumentReg[0], argc);
+ tc->setIntReg(ArgumentReg[1], argv_array_base);
+ tc->setIntReg(StackPointerReg, stack_min);
+
+ Addr prog_entry = objFile->entryPoint();
+ tc->setPC(prog_entry);
+ tc->setNextPC(prog_entry + sizeof(MachInst));
+
+#if THE_ISA != ALPHA_ISA //e.g. MIPS or Sparc
+ tc->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
+#endif
+
+
}
void
if (checkpointRestored)
return;
+ Process::startup();
+
argsInit(MachineBytes, VMPageSize);
ThreadContext *tc = system->getThreadContext(contextIds[0]);
#include "sim/process.hh"
-class ObjectFile;
-class System;
-
class AlphaLiveProcess : public LiveProcess
{
protected:
AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile);
void startup();
+
+ void argsInit(int intSize, int pageSize);
};
#endif // __ARCH_ALPHA_PROCESS_HH__
data.size = phdr.p_filesz;
data.fileImage = fileData + phdr.p_offset;
} else {
+ // If it's none of the above but is loadable,
+ // load the filesize worth of data
Segment extra;
extra.baseAddr = phdr.p_paddr;
extra.size = phdr.p_filesz;
if (objFile->getArch() != ObjectFile::Alpha)
fatal("Object file architecture does not match compiled ISA (Alpha).");
- if (objFile->hasTLS())
- fatal("Object file has a TLS section and single threaded TLS is not\n"
- " currently supported for Alpha! Please recompile your "
- "executable with \n a non-TLS toolchain.\n");
-
switch (objFile->getOpSys()) {
case ObjectFile::Tru64:
process = new AlphaTru64Process(params, objFile);
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 65718863 # Number of BTB hits
-global.BPredUnit.BTBLookups 73181378 # Number of BTB lookups
+global.BPredUnit.BTBHits 65718859 # Number of BTB hits
+global.BPredUnit.BTBLookups 73181368 # Number of BTB lookups
global.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 70112297 # Number of conditional branches predicted
-global.BPredUnit.lookups 76039028 # Number of BP lookups
+global.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted
+global.BPredUnit.lookups 76039018 # Number of BP lookups
global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target.
-host_inst_rate 204243 # Simulator instruction rate (inst/s)
-host_mem_usage 202188 # Number of bytes of host memory used
-host_seconds 2769.01 # Real time elapsed on the host
-host_tick_rate 60338522 # Simulator tick rate (ticks/s)
+host_inst_rate 193677 # Simulator instruction rate (inst/s)
+host_mem_usage 202220 # Number of bytes of host memory used
+host_seconds 2920.07 # Real time elapsed on the host
+host_tick_rate 57217081 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 126977207 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 43223597 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 565552443 # Number of instructions simulated
sim_seconds 0.167078 # Number of seconds simulated
-sim_ticks 167078186500 # Number of ticks simulated
+sim_ticks 167078146500 # Number of ticks simulated
system.cpu.commit.COM:branches 62547159 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 322711309
+system.cpu.commit.COM:committed_per_cycle.samples 322711249
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 108088817 3349.40%
+ 0 108088757 3349.40%
1 100475751 3113.49%
2 37367184 1157.91%
3 9733028 301.60%
4 10676883 330.85%
- 5 22147835 686.30%
+ 5 22147835 686.31%
6 13251874 410.64%
7 3269687 101.32%
8 17700250 548.49%
system.cpu.commit.branchMispredicts 4206223 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 61418223 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 61418165 # The number of squashed insts skipped by commit
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
system.cpu.cpi 0.590849 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.590849 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 113146791 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 19647.218520 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.236909 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 112293702 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 16760826000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_accesses 113146786 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 19647.173839 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.243845 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 112293703 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 16760670000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.007540 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 853089 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 636812 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1688309500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses 853083 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 636806 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1688311000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001911 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 216277 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs 6922.723577 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets 21318.181818 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 317.179200 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 317.179202 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 123 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 11 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 851495 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 234500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 152598112 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 29275.568696 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 24763.762399 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 149415338 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 93177518881 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_accesses 152598107 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 29275.574871 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 149415339 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 93177362881 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.020857 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 3182774 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2629219 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 13708104495 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_misses 3182768 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2629213 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 13708105995 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003628 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 553555 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 152598112 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 29275.568696 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 24763.762399 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 152598107 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 29275.574871 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 149415338 # number of overall hits
-system.cpu.dcache.overall_miss_latency 93177518881 # number of overall miss cycles
+system.cpu.dcache.overall_hits 149415339 # number of overall hits
+system.cpu.dcache.overall_miss_latency 93177362881 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 3182774 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 2629219 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 13708104495 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_misses 3182768 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 2629213 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 13708105995 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003628 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements 468828 # number of replacements
system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.202443 # Cycle average of tags in use
-system.cpu.dcache.total_refs 150001656 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 126621000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tagsinuse 4094.203417 # Cycle average of tags in use
+system.cpu.dcache.total_refs 150001657 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 126581000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 334123 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 49202535 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BlockedCycles 49202518 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 4158991 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 689696251 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 144199512 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 123896072 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 9869869 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:DecodedInsts 689696194 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 144199483 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 123896058 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 9869862 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 163077395 # DTB accesses
+system.cpu.dtb.accesses 163077390 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 163013885 # DTB hits
+system.cpu.dtb.hits 163013880 # DTB hits
system.cpu.dtb.misses 63510 # DTB misses
-system.cpu.dtb.read_accesses 122284114 # DTB read accesses
+system.cpu.dtb.read_accesses 122284109 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 122260501 # DTB read hits
+system.cpu.dtb.read_hits 122260496 # DTB read hits
system.cpu.dtb.read_misses 23613 # DTB read misses
system.cpu.dtb.write_accesses 40793281 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 40753384 # DTB write hits
system.cpu.dtb.write_misses 39897 # DTB write misses
-system.cpu.fetch.Branches 76039028 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 66014416 # Number of cache lines fetched
-system.cpu.fetch.Cycles 197129359 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Branches 76039018 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 66014406 # Number of cache lines fetched
+system.cpu.fetch.Cycles 197129335 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1352914 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 698864070 # Number of instructions fetch has processed
+system.cpu.fetch.Insts 698864013 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 4233116 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.227555 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 66014416 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 67411082 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.091428 # Number of inst fetches per cycle
+system.cpu.fetch.icacheStallCycles 66014406 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 67411078 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.091429 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 332581179
+system.cpu.fetch.rateDist.samples 332581112
system.cpu.fetch.rateDist.min_value 0
- 0 201466276 6057.66%
- 1 10360751 311.53%
- 2 15882086 477.54%
+ 0 201466223 6057.66%
+ 1 10360747 311.53%
+ 2 15882081 477.54%
3 14599006 438.96%
4 12362950 371.73%
- 5 14822133 445.67%
+ 5 14822134 445.67%
6 6008311 180.66%
7 3307530 99.45%
- 8 53772136 1616.81%
+ 8 53772130 1616.81%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 66014416 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 36203.165098 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35497.228381 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 66013247 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 42321500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 66014406 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 36214.713430 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35498.337029 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 66013237 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 42335000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1169 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 267 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 32018500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 32019500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 73185.417960 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 73185.406874 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 66014416 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 36203.165098 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35497.228381 # average overall mshr miss latency
-system.cpu.icache.demand_hits 66013247 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 42321500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 66014406 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 36214.713430 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency
+system.cpu.icache.demand_hits 66013237 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 42335000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
system.cpu.icache.demand_misses 1169 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 32018500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 32019500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 66014416 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 36203.165098 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35497.228381 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 66014406 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 66013247 # number of overall hits
-system.cpu.icache.overall_miss_latency 42321500 # number of overall miss cycles
+system.cpu.icache.overall_hits 66013237 # number of overall hits
+system.cpu.icache.overall_miss_latency 42335000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
system.cpu.icache.overall_misses 1169 # number of overall misses
system.cpu.icache.overall_mshr_hits 267 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 32018500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 32019500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 34 # number of replacements
system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 769.803769 # Cycle average of tags in use
-system.cpu.icache.total_refs 66013247 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 769.803945 # Cycle average of tags in use
+system.cpu.icache.total_refs 66013237 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 1575195 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 67316863 # Number of branches executed
+system.cpu.idleCycles 1575182 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 67316859 # Number of branches executed
system.cpu.iew.EXEC:nop 42997381 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.793347 # Inst execution rate
-system.cpu.iew.EXEC:refs 164017998 # number of memory reference insts executed
+system.cpu.iew.EXEC:refs 164017993 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 41189464 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 487237026 # num instructions consuming a value
-system.cpu.iew.WB:count 596051181 # cumulative count of insts written-back
+system.cpu.iew.WB:consumers 487237002 # num instructions consuming a value
+system.cpu.iew.WB:count 596051147 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.811465 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 395375822 # num instructions producing a value
-system.cpu.iew.WB:rate 1.783749 # insts written-back per cycle
-system.cpu.iew.WB:sent 597227214 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 4671564 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 2251991 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 126977207 # Number of dispatched load instructions
+system.cpu.iew.WB:producers 395375802 # num instructions producing a value
+system.cpu.iew.WB:rate 1.783750 # insts written-back per cycle
+system.cpu.iew.WB:sent 597227180 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 4671561 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 2251979 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 126977202 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 3270425 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 43223597 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 663380014 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 122828534 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 6459967 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 599258177 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 2444 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewDispatchedInsts 663379957 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 122828529 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 6459968 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 599258144 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 2443 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 34441 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 9869869 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 84553 # Number of cycles IEW is unblocking
+system.cpu.iew.iewSquashCycles 9869862 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 84552 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 207 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 9107751 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 29567 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 5881 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 11927697 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedLoads 11927692 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 3411074 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 29567 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 540318 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 540315 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.692478 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.692478 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 605718144 # Type of FU issued
+system.cpu.ipc 1.692479 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.692479 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 605718112 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 0 0.00% # Type of FU issued
- IntAlu 438834867 72.45% # Type of FU issued
+ IntAlu 438834840 72.45% # Type of FU issued
IntMult 6546 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 29 0.00% # Type of FU issued
FloatMult 4 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 124855458 20.61% # Type of FU issued
+ MemRead 124855453 20.61% # Type of FU issued
MemWrite 42021230 6.94% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 7232327 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_cnt 7232323 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 5390835 74.54% # attempts to use FU when none available
+ IntAlu 5390831 74.54% # attempts to use FU when none available
IntMult 67 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 332581179
+system.cpu.iq.ISSUE:issued_per_cycle.samples 332581112
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 92203834 2772.37%
- 1 67051351 2016.09%
- 2 80133785 2409.45%
- 3 36043476 1083.75%
+ 0 92203773 2772.37%
+ 1 67051353 2016.09%
+ 2 80133780 2409.45%
+ 3 36043478 1083.75%
4 30084945 904.59%
5 14579095 438.36%
- 6 10850498 326.25%
+ 6 10850493 326.25%
7 1143008 34.37%
8 491187 14.77%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate
-system.cpu.iq.iqInstsAdded 620382610 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 605718144 # Number of instructions issued
+system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 53519343 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 53519286 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 29313590 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 66014456 # ITB accesses
+system.cpu.iq.iqSquashedOperandsExamined 29313548 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 66014446 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 66014416 # ITB hits
+system.cpu.itb.hits 66014406 # ITB hits
system.cpu.itb.misses 40 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 256647 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 217179 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34303.958543 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.588334 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34303.986479 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.630238 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 181383 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1227944500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 1227945500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.164823 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 35796 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1110234000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1110235500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164823 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 35796 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 80643 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34265.680834 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.122014 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34265.684253 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 181383 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 10020758500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 10020759500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.617195 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 292443 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 9102616500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 9102618000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.617195 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 292443 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34265.680834 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.122014 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 181383 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 10020758500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 10020759500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 292443 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 9102616500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 9102618000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.replacements 85262 # number of replacements
system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16333.158558 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 16333.162457 # Cycle average of tags in use
system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 63236 # number of writebacks
-system.cpu.numCycles 334156374 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 15214869 # Number of cycles rename is blocking
+system.cpu.numCycles 334156294 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 15214853 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 31587364 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 151899466 # Number of cycles rename is idle
+system.cpu.rename.RENAME:IQFullEvents 31587363 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 151899436 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 2286618 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 896816435 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 680424801 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 519473844 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 116401000 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 9869869 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 39195269 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 55618955 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:RenameLookups 896816353 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 680424744 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 519473797 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 116400987 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 9869862 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 39195268 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 55618908 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 706 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 77660301 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 77660298 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 26 # count of temporary serializing insts renamed
-system.cpu.timesIdled 36535 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 36534 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 21:40:15
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:25:12
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 3818661 # Simulator instruction rate (inst/s)
-host_mem_usage 193720 # Number of bytes of host memory used
-host_seconds 157.61 # Real time elapsed on the host
-host_tick_rate 1909343313 # Simulator tick rate (ticks/s)
+host_inst_rate 3417919 # Simulator instruction rate (inst/s)
+host_mem_usage 193752 # Number of bytes of host memory used
+host_seconds 176.09 # Real time elapsed on the host
+host_tick_rate 1708971531 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.300931 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 19:05:35
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:47
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 1993278 # Simulator instruction rate (inst/s)
-host_mem_usage 201176 # Number of bytes of host memory used
-host_seconds 301.94 # Real time elapsed on the host
-host_tick_rate 2576653236 # Simulator tick rate (ticks/s)
+host_inst_rate 1797646 # Simulator instruction rate (inst/s)
+host_mem_usage 201208 # Number of bytes of host memory used
+host_seconds 334.80 # Real time elapsed on the host
+host_tick_rate 2323765799 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.778004 # Number of seconds simulated
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 673.225224 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 673.225223 # Cycle average of tags in use
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 19:08:13
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:45
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
global.BPredUnit.lookups 5530798 # Number of BP lookups
global.BPredUnit.usedRAS 690318 # Number of times the RAS was used to get a target.
global.BPredUnit.usedRAS 415111 # Number of times the RAS was used to get a target.
-host_inst_rate 130617 # Simulator instruction rate (inst/s)
-host_mem_usage 292856 # Number of bytes of host memory used
-host_seconds 429.91 # Real time elapsed on the host
-host_tick_rate 4437424208 # Simulator tick rate (ticks/s)
+host_inst_rate 121094 # Simulator instruction rate (inst/s)
+host_mem_usage 292872 # Number of bytes of host memory used
+host_seconds 463.72 # Real time elapsed on the host
+host_tick_rate 4113887240 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 2050196 # Number of conflicting loads.
memdepunit.memDep.conflictingLoads 902547 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 1831551 # Number of conflicting stores.
All Rights Reserved
-M5 compiled Nov 5 2008 22:27:11
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:30:16
+M5 compiled Dec 4 2008 21:30:58
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:35:52
M5 executing on zizzer
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
global.BPredUnit.condPredicted 12127533 # Number of conditional branches predicted
global.BPredUnit.lookups 14559443 # Number of BP lookups
global.BPredUnit.usedRAS 1032470 # Number of times the RAS was used to get a target.
-host_inst_rate 200905 # Simulator instruction rate (inst/s)
-host_mem_usage 290800 # Number of bytes of host memory used
-host_seconds 264.07 # Real time elapsed on the host
-host_tick_rate 7071490969 # Simulator tick rate (ticks/s)
+host_inst_rate 123231 # Simulator instruction rate (inst/s)
+host_mem_usage 290820 # Number of bytes of host memory used
+host_seconds 430.51 # Real time elapsed on the host
+host_tick_rate 4337505567 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 3072758 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 2866670 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 11041732 # Number of loads inserted to the mem dependence unit.
All Rights Reserved
-M5 compiled Nov 5 2008 22:27:11
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:28:27
+M5 compiled Dec 4 2008 21:30:58
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:31:00
M5 executing on zizzer
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
global.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted
global.BPredUnit.lookups 62209737 # Number of BP lookups
global.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target.
-host_inst_rate 185748 # Simulator instruction rate (inst/s)
-host_mem_usage 209620 # Number of bytes of host memory used
-host_seconds 2021.96 # Real time elapsed on the host
-host_tick_rate 66765374 # Simulator tick rate (ticks/s)
+host_inst_rate 151728 # Simulator instruction rate (inst/s)
+host_mem_usage 209656 # Number of bytes of host memory used
+host_seconds 2475.31 # Real time elapsed on the host
+host_tick_rate 54537175 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 73961217 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 54131405 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit.
system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 95501309 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 33012.273524 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 33016.637478 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31966.971545 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 95499598 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 56484000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_hits 95499596 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 56557500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1711 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 727 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_misses 1713 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 729 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 31455500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 984 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 3309 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs 3249.700000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 40460.273163 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 40460.272684 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 32497 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 169022038 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 30545.096938 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency 30545.726047 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 169002314 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 602471492 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_hits 169002312 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 602544992 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 19724 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 15431 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_misses 19726 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 15433 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 151230997 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 4293 # number of demand (read+write) MSHR misses
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 169022038 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 30545.096938 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 30545.726047 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 169002314 # number of overall hits
-system.cpu.dcache.overall_miss_latency 602471492 # number of overall miss cycles
+system.cpu.dcache.overall_hits 169002312 # number of overall hits
+system.cpu.dcache.overall_miss_latency 602544992 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 19724 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 15431 # number of overall MSHR hits
+system.cpu.dcache.overall_misses 19726 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 15433 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 151230997 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 4293 # number of overall MSHR misses
system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3293.970402 # Cycle average of tags in use
-system.cpu.dcache.total_refs 169002561 # Total number of references to valid blocks.
+system.cpu.dcache.total_refs 169002559 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 635 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 18875032 # Number of cycles decode is blocked
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 140725 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 50976852 # Number of branches executed
+system.cpu.iew.EXEC:branches 50976851 # Number of branches executed
system.cpu.iew.EXEC:nop 27164335 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.553144 # Inst execution rate
system.cpu.iew.EXEC:refs 191842297 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 80676625 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 285463488 # num instructions consuming a value
-system.cpu.iew.WB:count 415481244 # cumulative count of insts written-back
+system.cpu.iew.WB:consumers 285463485 # num instructions consuming a value
+system.cpu.iew.WB:count 415481237 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.703314 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 200770523 # num instructions producing a value
+system.cpu.iew.WB:producers 200770520 # num instructions producing a value
system.cpu.iew.WB:rate 1.538857 # insts written-back per cycle
-system.cpu.iew.WB:sent 416287471 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 6390314 # Number of branch mispredicts detected at execute
+system.cpu.iew.WB:sent 416287464 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 6390313 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 2178518 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 124841223 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispStoreInsts 92324076 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 493447669 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 111165672 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 10261542 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 419338657 # Number of executed instructions
+system.cpu.iew.iewExecSquashedInsts 10261544 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 419338652 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 25079 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 23746 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.lsq.thread.0.squashedStores 18792674 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 436213 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 847804 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 5542510 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 5542509 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.391052 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.391052 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 429600199 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0 429600196 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 33581 0.01% # Type of FU issued
- IntAlu 166319017 38.71% # Type of FU issued
+ IntAlu 166319014 38.71% # Type of FU issued
IntMult 2152935 0.50% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 35077566 8.17% # Type of FU issued
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 99465935 3685.94%
1 57766030 2140.65%
- 2 39984555 1481.72%
- 3 29664957 1099.30%
- 4 23966119 888.12%
- 5 10452564 387.34%
- 6 5712017 211.67%
+ 2 39984554 1481.72%
+ 3 29664959 1099.30%
+ 4 23966120 888.12%
+ 5 10452563 387.34%
+ 6 5712016 211.67%
7 2252970 83.49%
8 587500 21.77%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:rate 1.591151 # Inst issue rate
system.cpu.iq.iqInstsAdded 466283095 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 429600199 # Number of instructions issued
+system.cpu.iq.iqInstsIssued 429600196 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 89615992 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 918381 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 68228106 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 68228113 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 63866476 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 63866189 # ITB hits
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 18:33:01
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:46
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 3323718 # Simulator instruction rate (inst/s)
-host_mem_usage 201288 # Number of bytes of host memory used
-host_seconds 119.95 # Real time elapsed on the host
-host_tick_rate 1661856596 # Simulator tick rate (ticks/s)
+host_inst_rate 3407773 # Simulator instruction rate (inst/s)
+host_mem_usage 201328 # Number of bytes of host memory used
+host_seconds 116.99 # Real time elapsed on the host
+host_tick_rate 1703884563 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664595 # Number of instructions simulated
sim_seconds 0.199332 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 19:13:17
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:26:02
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 1753697 # Simulator instruction rate (inst/s)
-host_mem_usage 208744 # Number of bytes of host memory used
-host_seconds 227.33 # Real time elapsed on the host
-host_tick_rate 2495737915 # Simulator tick rate (ticks/s)
+host_inst_rate 1526276 # Simulator instruction rate (inst/s)
+host_mem_usage 208780 # Number of bytes of host memory used
+host_seconds 261.20 # Real time elapsed on the host
+host_tick_rate 2172088412 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664609 # Number of instructions simulated
sim_seconds 0.567352 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 18:58:04
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:22:18
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
global.BPredUnit.RASInCorrect 3593 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 29107758 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted
-global.BPredUnit.lookups 349424732 # Number of BP lookups
-global.BPredUnit.usedRAS 49888257 # Number of times the RAS was used to get a target.
-host_inst_rate 250324 # Simulator instruction rate (inst/s)
-host_mem_usage 209520 # Number of bytes of host memory used
-host_seconds 7282.75 # Real time elapsed on the host
-host_tick_rate 96826033 # Simulator tick rate (ticks/s)
+global.BPredUnit.lookups 349424731 # Number of BP lookups
+global.BPredUnit.usedRAS 49888256 # Number of times the RAS was used to get a target.
+host_inst_rate 157306 # Simulator instruction rate (inst/s)
+host_mem_usage 209560 # Number of bytes of host memory used
+host_seconds 11589.17 # Real time elapsed on the host
+host_tick_rate 60846406 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 118847053 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 21034746 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 655954744 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 655954745 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 303651290 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1823043370 # Number of instructions simulated
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 1310002800
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 603585598 4607.51%
- 1 273587002 2088.45%
+ 0 603585596 4607.51%
+ 1 273587005 2088.45%
2 174037133 1328.52%
- 3 65399709 499.23%
- 4 48333002 368.95%
- 5 34003109 259.57%
- 6 18481317 141.08%
- 7 23715686 181.04%
+ 3 65399708 499.23%
+ 4 48333001 368.95%
+ 5 34003110 259.57%
+ 6 18481318 141.08%
+ 7 23715685 181.04%
8 68860244 525.65%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.branchMispredicts 29095954 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 696013928 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 696013930 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
system.cpu.cpi 0.773607 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.773607 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 6 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 6 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 465737270 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 37550.777258 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses 465737269 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 37550.774879 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34829.991989 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 463802713 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 72644119000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_hits 463802710 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 72644189500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.004154 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1934557 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 475264 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_misses 1934559 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 475266 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 50827163500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003133 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1459293 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 74781 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs 5124.928571 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets 18000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 440.284638 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 440.284636 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 28 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 143498 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 18000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 676532166 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 37782.431371 # average overall miss latency
+system.cpu.dcache.demand_accesses 676532165 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 37782.429340 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 674038254 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 94226058985 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_hits 674038251 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 94226129485 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.003686 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2493912 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 959838 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_misses 2493914 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 959840 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 53558520998 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002268 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1534074 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 676532166 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 37782.431371 # average overall miss latency
+system.cpu.dcache.overall_accesses 676532165 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 37782.429340 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 674038254 # number of overall hits
-system.cpu.dcache.overall_miss_latency 94226058985 # number of overall miss cycles
+system.cpu.dcache.overall_hits 674038251 # number of overall hits
+system.cpu.dcache.overall_miss_latency 94226129485 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.003686 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2493912 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 959838 # number of overall MSHR hits
+system.cpu.dcache.overall_misses 2493914 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 959840 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 53558520998 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002268 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1534074 # number of overall MSHR misses
system.cpu.dcache.sampled_refs 1530943 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.104513 # Cycle average of tags in use
-system.cpu.dcache.total_refs 674050685 # Total number of references to valid blocks.
+system.cpu.dcache.total_refs 674050682 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 274499000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 74589 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 32190527 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 12129 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 30585324 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 2936172394 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 716337475 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 561391035 # Number of cycles decode is running
+system.cpu.decode.DECODE:DecodedInsts 2936172402 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 716337474 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 561391036 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 100159084 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 45706 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 83764 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 775959989 # DTB accesses
+system.cpu.dtb.accesses 775959987 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 775335045 # DTB hits
+system.cpu.dtb.hits 775335043 # DTB hits
system.cpu.dtb.misses 624944 # DTB misses
-system.cpu.dtb.read_accesses 516992086 # DTB read accesses
+system.cpu.dtb.read_accesses 516992085 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 516404964 # DTB read hits
+system.cpu.dtb.read_hits 516404963 # DTB read hits
system.cpu.dtb.read_misses 587122 # DTB read misses
-system.cpu.dtb.write_accesses 258967903 # DTB write accesses
+system.cpu.dtb.write_accesses 258967902 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 258930081 # DTB write hits
+system.cpu.dtb.write_hits 258930080 # DTB write hits
system.cpu.dtb.write_misses 37822 # DTB write misses
-system.cpu.fetch.Branches 349424732 # Number of branches that fetch encountered
+system.cpu.fetch.Branches 349424731 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 348447899 # Number of cache lines fetched
system.cpu.fetch.Cycles 928021937 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 4387629 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 3030218621 # Number of instructions fetch has processed
+system.cpu.fetch.Insts 3030218619 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 29544622 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.247763 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 348447899 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 290350353 # Number of branches that fetch has predicted taken
+system.cpu.fetch.predictedBranches 290350352 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.148605 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 1410161885
1 53463106 379.13%
2 39766072 282.00%
3 63538024 450.57%
- 4 121390718 860.83%
+ 4 121390719 860.83%
5 35256321 250.02%
- 6 38761683 274.87%
+ 6 38761682 274.87%
7 6988644 49.56%
8 220409277 1563.01%
system.cpu.fetch.rateDist.max_value 8
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 157025 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 274534146 # Number of branches executed
+system.cpu.iew.EXEC:branches 274534145 # Number of branches executed
system.cpu.iew.EXEC:nop 329178061 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.421117 # Inst execution rate
-system.cpu.iew.EXEC:refs 776495505 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 258968901 # Number of stores executed
+system.cpu.iew.EXEC:refs 776495503 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 258968900 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1631503181 # num instructions consuming a value
-system.cpu.iew.WB:count 2002130592 # cumulative count of insts written-back
+system.cpu.iew.WB:consumers 1631503179 # num instructions consuming a value
+system.cpu.iew.WB:count 2002130585 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.696431 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1136229271 # num instructions producing a value
+system.cpu.iew.WB:producers 1136229268 # num instructions producing a value
system.cpu.iew.WB:rate 1.419630 # insts written-back per cycle
-system.cpu.iew.WB:sent 2003425038 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 31680134 # Number of branch mispredicts detected at execute
+system.cpu.iew.WB:sent 2003425032 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 31680133 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 3459468 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 655954744 # Number of dispatched load instructions
+system.cpu.iew.iewDispLoadInsts 655954745 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 57 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 62125 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispSquashedInsts 62130 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 303651290 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 2715209776 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 517526604 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 85279851 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 2004227959 # Number of executed instructions
+system.cpu.iew.iewDispatchedInsts 2715209778 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 517526603 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 85279852 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 2004227953 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 131519 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 3361 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 3589 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 4102 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 144359442 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedLoads 144359443 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 92856159 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 3589 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 816990 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 30863144 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 30863143 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.292646 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.292646 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 2089507810 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0 2089507805 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 2752 0.00% # Type of FU issued
- IntAlu 1204412682 57.64% # Type of FU issued
+ IntAlu 1204412678 57.64% # Type of FU issued
IntMult 17591 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 27851349 1.33% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 557993260 26.70% # Type of FU issued
- MemWrite 283770832 13.58% # Type of FU issued
+ MemWrite 283770831 13.58% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 37093549 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_cnt 37093546 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.017752 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 28032979 75.57% # attempts to use FU when none available
- MemWrite 9052279 24.40% # attempts to use FU when none available
+ MemRead 28032977 75.57% # attempts to use FU when none available
+ MemWrite 9052278 24.40% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 1410161885
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 537278440 3810.05%
- 1 285217725 2022.59%
- 2 273546794 1939.83%
- 3 154810622 1097.82%
- 4 63341839 449.18%
- 5 51438518 364.77%
- 6 32491112 230.41%
- 7 9036667 64.08%
+ 0 537278436 3810.05%
+ 1 285217724 2022.59%
+ 2 273546804 1939.83%
+ 3 154810620 1097.82%
+ 4 63341841 449.18%
+ 5 51438515 364.77%
+ 6 32491109 230.41%
+ 7 9036668 64.08%
8 3000168 21.28%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.481585 # Inst issue rate
-system.cpu.iq.iqInstsAdded 2386031658 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 2089507810 # Number of instructions issued
+system.cpu.iq.iqInstsAdded 2386031660 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 2089507805 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 562621265 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 12403595 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 562621267 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 12403599 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 516017441 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 516017454 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 348448092 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 348447899 # ITB hits
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 19:15:35
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:45
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 5368625 # Simulator instruction rate (inst/s)
-host_mem_usage 200452 # Number of bytes of host memory used
-host_seconds 374.21 # Real time elapsed on the host
-host_tick_rate 2684890322 # Simulator tick rate (ticks/s)
+host_inst_rate 3237524 # Simulator instruction rate (inst/s)
+host_mem_usage 200500 # Number of bytes of host memory used
+host_seconds 620.53 # Real time elapsed on the host
+host_tick_rate 1619110797 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 1.004711 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 19:06:43
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:26:39
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 2795907 # Simulator instruction rate (inst/s)
-host_mem_usage 207904 # Number of bytes of host memory used
-host_seconds 718.55 # Real time elapsed on the host
-host_tick_rate 3917565207 # Simulator tick rate (ticks/s)
+host_inst_rate 1407375 # Simulator instruction rate (inst/s)
+host_mem_usage 207960 # Number of bytes of host memory used
+host_seconds 1427.47 # Real time elapsed on the host
+host_tick_rate 1971983298 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 2.814951 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 21:28:15
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:44
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 8039248 # Number of BTB hits
-global.BPredUnit.BTBLookups 14256738 # Number of BTB lookups
+global.BPredUnit.BTBHits 8039250 # Number of BTB hits
+global.BPredUnit.BTBLookups 14256744 # Number of BTB lookups
global.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 10551562 # Number of conditional branches predicted
-global.BPredUnit.lookups 16249458 # Number of BP lookups
+global.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted
+global.BPredUnit.lookups 16249463 # Number of BP lookups
global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target.
-host_inst_rate 272001 # Simulator instruction rate (inst/s)
-host_mem_usage 212988 # Number of bytes of host memory used
-host_seconds 292.62 # Real time elapsed on the host
-host_tick_rate 92731689 # Simulator tick rate (ticks/s)
+host_inst_rate 155507 # Simulator instruction rate (inst/s)
+host_mem_usage 212996 # Number of bytes of host memory used
+host_seconds 511.82 # Real time elapsed on the host
+host_tick_rate 53016132 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 23001211 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 16328870 # Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 16328872 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.027135 # Number of seconds simulated
-sim_ticks 27134783500 # Number of ticks simulated
+sim_ticks 27134794500 # Number of ticks simulated
system.cpu.commit.COM:branches 13754477 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 3320893 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 51751153
+system.cpu.commit.COM:committed_per_cycle.samples 51751168
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 22506428 4348.97%
- 1 11357580 2194.65%
+ 0 22506445 4348.97%
+ 1 11357579 2194.65%
2 5114502 988.29%
3 3560855 688.07%
- 4 2552506 493.23%
- 5 1532718 296.17%
- 6 1008932 194.96%
+ 4 2552504 493.23%
+ 5 1532717 296.17%
+ 6 1008933 194.96%
7 796739 153.96%
- 8 3320893 641.70%
+ 8 3320894 641.70%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 8296832 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 8296858 # The number of squashed insts skipped by commit
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 20425511 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 30386.313820 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses 20425513 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 30386.330224 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 20275871 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4547008000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_hits 20275869 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4547132000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 149640 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 88104 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_misses 149644 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 88108 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs 3166.333333 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets 27000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 165.103746 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 165.103737 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 6 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 18998 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 27000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 35038888 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 32023.264084 # average overall miss latency
+system.cpu.dcache.demand_accesses 35038890 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 32023.260673 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 33838927 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 38426667994 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_hits 33838925 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 38426791994 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1199961 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 988636 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_misses 1199965 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 988640 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 35038888 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 32023.264084 # average overall miss latency
+system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 33838927 # number of overall hits
-system.cpu.dcache.overall_miss_latency 38426667994 # number of overall miss cycles
+system.cpu.dcache.overall_hits 33838925 # number of overall hits
+system.cpu.dcache.overall_miss_latency 38426791994 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1199961 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 988636 # number of overall MSHR hits
+system.cpu.dcache.overall_misses 1199965 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 988640 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses
system.cpu.dcache.replacements 200933 # number of replacements
system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4077.325791 # Cycle average of tags in use
-system.cpu.dcache.total_refs 33851056 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 183212000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tagsinuse 4077.324152 # Cycle average of tags in use
+system.cpu.dcache.total_refs 33851054 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 183223000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147760 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 3553972 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BlockedCycles 3553993 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 3655574 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 101758297 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 28531772 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 19520692 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 1290098 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:BranchResolved 3655575 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 101758318 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 28531763 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 19520694 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1290101 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 144718 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 36599686 # DTB accesses
+system.cpu.decode.DECODE:UnblockCycles 144719 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 36599689 # DTB accesses
system.cpu.dtb.acv 39 # DTB access violations
-system.cpu.dtb.hits 36425478 # DTB hits
+system.cpu.dtb.hits 36425481 # DTB hits
system.cpu.dtb.misses 174208 # DTB misses
-system.cpu.dtb.read_accesses 21541286 # DTB read accesses
+system.cpu.dtb.read_accesses 21541288 # DTB read accesses
system.cpu.dtb.read_acv 37 # DTB read access violations
-system.cpu.dtb.read_hits 21383018 # DTB read hits
+system.cpu.dtb.read_hits 21383020 # DTB read hits
system.cpu.dtb.read_misses 158268 # DTB read misses
-system.cpu.dtb.write_accesses 15058400 # DTB write accesses
+system.cpu.dtb.write_accesses 15058401 # DTB write accesses
system.cpu.dtb.write_acv 2 # DTB write access violations
-system.cpu.dtb.write_hits 15042460 # DTB write hits
+system.cpu.dtb.write_hits 15042461 # DTB write hits
system.cpu.dtb.write_misses 15940 # DTB write misses
-system.cpu.fetch.Branches 16249458 # Number of branches that fetch encountered
+system.cpu.fetch.Branches 16249463 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched
-system.cpu.fetch.Cycles 33247227 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Cycles 33247230 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 103308047 # Number of instructions fetch has processed
+system.cpu.fetch.Insts 103308065 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 567638 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 9981177 # Number of branches that fetch has predicted taken
+system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 53041252
+system.cpu.fetch.rateDist.samples 53041270
system.cpu.fetch.rateDist.min_value 0
- 0 33206262 6260.46%
+ 0 33206277 6260.46%
1 1871594 352.86%
2 1529415 288.34%
3 1809626 341.17%
4 3985239 751.35%
- 5 1867237 352.03%
+ 5 1867239 352.04%
6 695846 131.19%
7 1111736 209.60%
- 8 6964297 1313.00%
+ 8 6964298 1313.00%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 9527.365371 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 9527.179672 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 13297365 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 845144000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_hits 13297366 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 845118000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 88707 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 2771 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_misses 88706 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 2770 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 154.737476 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 154.737488 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 9527.365371 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency 9527.179672 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency
-system.cpu.icache.demand_hits 13297365 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 845144000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_hits 13297366 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 845118000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses
-system.cpu.icache.demand_misses 88707 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 2771 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_misses 88706 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 2770 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 9527.365371 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 13297365 # number of overall hits
-system.cpu.icache.overall_miss_latency 845144000 # number of overall miss cycles
+system.cpu.icache.overall_hits 13297366 # number of overall hits
+system.cpu.icache.overall_miss_latency 845118000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses
-system.cpu.icache.overall_misses 88707 # number of overall misses
-system.cpu.icache.overall_mshr_hits 2771 # number of overall MSHR hits
+system.cpu.icache.overall_misses 88706 # number of overall misses
+system.cpu.icache.overall_mshr_hits 2770 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses
system.cpu.icache.replacements 83888 # number of replacements
system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1916.994932 # Cycle average of tags in use
-system.cpu.icache.total_refs 13297365 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1916.994169 # Cycle average of tags in use
+system.cpu.icache.total_refs 13297366 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 1228316 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 14745483 # Number of branches executed
+system.cpu.idleCycles 1228320 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 14745486 # Number of branches executed
system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.562958 # Inst execution rate
-system.cpu.iew.EXEC:refs 36941990 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 15291391 # Number of stores executed
+system.cpu.iew.EXEC:rate 1.562957 # Inst execution rate
+system.cpu.iew.EXEC:refs 36941993 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 15291392 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 42302247 # num instructions consuming a value
-system.cpu.iew.WB:count 84351843 # cumulative count of insts written-back
+system.cpu.iew.WB:consumers 42302279 # num instructions consuming a value
+system.cpu.iew.WB:count 84351875 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 32396966 # num instructions producing a value
+system.cpu.iew.WB:producers 32396987 # num instructions producing a value
system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle
-system.cpu.iew.WB:sent 84585242 # cumulative count of insts sent to commit
+system.cpu.iew.WB:sent 84585274 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 627280 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 23001211 # Number of dispatched load instructions
+system.cpu.iew.iewBlockCycles 627293 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 23001213 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 16328870 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 98972071 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 21650599 # Number of load instructions executed
+system.cpu.iew.iewDispStoreInsts 16328872 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 98972097 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 21650601 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 84821030 # Number of executed instructions
+system.cpu.iew.iewExecutedInsts 84821059 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 1290098 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 44030 # Number of cycles IEW is unblocking
+system.cpu.iew.iewSquashCycles 1290101 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 44031 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 2621812 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 1484251 # Number of stores squashed
+system.cpu.iew.lsq.thread.0.squashedLoads 2621814 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 1484253 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 85346316 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0 85346345 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 0 0.00% # Type of FU issued
- IntAlu 47898540 56.12% # Type of FU issued
+ IntAlu 47898565 56.12% # Type of FU issued
IntMult 42953 0.05% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 121655 0.14% # Type of FU issued
FloatMult 53 0.00% # Type of FU issued
FloatDiv 38535 0.05% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 21753620 25.49% # Type of FU issued
- MemWrite 15368768 18.01% # Type of FU issued
+ MemRead 21753622 25.49% # Type of FU issued
+ MemWrite 15368770 18.01% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 979635 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_cnt 979640 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 97095 9.91% # attempts to use FU when none available
+ IntAlu 97100 9.91% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 53041252
+system.cpu.iq.ISSUE:issued_per_cycle.samples 53041270
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 17563400 3311.27%
- 1 13937997 2627.77%
- 2 8266118 1558.43%
- 3 4784811 902.09%
- 4 4627571 872.45%
- 5 2066742 389.65%
- 6 1112371 209.72%
- 7 454506 85.69%
- 8 227736 42.94%
+ 0 17563410 3311.27%
+ 1 13937999 2627.76%
+ 2 8266125 1558.43%
+ 3 4784809 902.09%
+ 4 4627568 872.45%
+ 5 2066740 389.65%
+ 6 1112374 209.72%
+ 7 454507 85.69%
+ 8 227738 42.94%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate
-system.cpu.iq.iqInstsAdded 89571411 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 85346316 # Number of instructions issued
+system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 9777285 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 49836 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 9777311 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 49841 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 6793888 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 6793875 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 13412237 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
system.cpu.itb.hits 13386072 # ITB hits
system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.558180 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.569397 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1383427500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1383428000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.312616 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 5865241000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 5865241500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.312616 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 102894 # number of overall hits
system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 188071 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 5865241000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 5865241500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.replacements 148779 # number of replacements
system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18483.932532 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 18483.925058 # Cycle average of tags in use
system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 120647 # number of writebacks
-system.cpu.numCycles 54269568 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 2047036 # Number of cycles rename is blocking
+system.cpu.numCycles 54269590 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 2047052 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 64601 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 28934159 # Number of cycles rename is idle
+system.cpu.rename.RENAME:IQFullEvents 64606 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 28934151 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 121625281 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 100952073 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 60736821 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 19265133 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 1290098 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1421425 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 8189940 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:RenameLookups 121625306 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 100952091 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 60736832 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 19265135 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1290101 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1421430 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 8189951 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 2801985 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 2801993 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed
system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 18:42:31
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:27:20
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 5277091 # Simulator instruction rate (inst/s)
-host_mem_usage 203864 # Number of bytes of host memory used
-host_seconds 16.74 # Real time elapsed on the host
-host_tick_rate 2641544350 # Simulator tick rate (ticks/s)
+host_inst_rate 3156054 # Simulator instruction rate (inst/s)
+host_mem_usage 203904 # Number of bytes of host memory used
+host_seconds 27.99 # Real time elapsed on the host
+host_tick_rate 1579824710 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.044221 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 19:13:00
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:24:43
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 1704355 # Simulator instruction rate (inst/s)
-host_mem_usage 211324 # Number of bytes of host memory used
-host_seconds 51.83 # Real time elapsed on the host
-host_tick_rate 2607795037 # Simulator tick rate (ticks/s)
+host_inst_rate 1655989 # Simulator instruction rate (inst/s)
+host_mem_usage 211348 # Number of bytes of host memory used
+host_seconds 53.35 # Real time elapsed on the host
+host_tick_rate 2533794438 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.135169 # Number of seconds simulated
-sim_ticks 135168711000 # Number of ticks simulated
+sim_ticks 135168766000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 37874.302641 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.302641 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2301432000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_avg_miss_latency 37874.600928 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.600928 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 2301488000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2119137000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 2119190000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 50768.923527 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 47768.923527 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 34679457 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10689803000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 50768.948371 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 10689859000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 210558 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 10058129000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 10058182000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 210558 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 50768.923527 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 47768.923527 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 50768.948371 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 34679457 # number of overall hits
-system.cpu.dcache.overall_miss_latency 10689803000 # number of overall miss cycles
+system.cpu.dcache.overall_hits 34679456 # number of overall hits
+system.cpu.dcache.overall_miss_latency 10689859000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 210558 # number of overall misses
+system.cpu.dcache.overall_misses 210559 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 10058129000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 10058182000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 210558 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 200247 # number of replacements
-system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 200248 # number of replacements
+system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4078.869222 # Cycle average of tags in use
-system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 947580000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tagsinuse 4078.872537 # Cycle average of tags in use
+system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 947635000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147714 # number of writebacks
system.cpu.dtb.accesses 34987415 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
system.cpu.icache.replacements 74391 # number of replacements
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1871.769418 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1871.768668 # Cycle average of tags in use
system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 137201 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 2251392000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.315566 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 43296 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1731840000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315566 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 43296 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency 2251444000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.315571 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 43297 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1731880000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315571 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 43297 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.630834 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.630830 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 9717448000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.665555 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 186874 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency 9717500000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.665557 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 186875 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 7474960000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.665555 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 186874 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 7475000000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.665557 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 186875 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 280779 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 93905 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 9717448000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.665555 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 186874 # number of overall misses
+system.cpu.l2cache.overall_miss_latency 9717500000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.665557 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 186875 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 7474960000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.665555 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 186874 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 7475000000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.665557 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 186875 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 147560 # number of replacements
-system.cpu.l2cache.sampled_refs 172765 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 147561 # number of replacements
+system.cpu.l2cache.sampled_refs 172766 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18255.753819 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 18255.825674 # Cycle average of tags in use
system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 120634 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 270337422 # number of cpu cycles simulated
+system.cpu.numCycles 270337532 # number of cpu cycles simulated
system.cpu.num_insts 88340673 # Number of instructions executed
system.cpu.num_refs 35321418 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 21:27:23
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:28:00
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
global.BPredUnit.condPredicted 266741494 # Number of conditional branches predicted
global.BPredUnit.lookups 345502589 # Number of BP lookups
global.BPredUnit.usedRAS 23750300 # Number of times the RAS was used to get a target.
-host_inst_rate 152874 # Simulator instruction rate (inst/s)
-host_mem_usage 201972 # Number of bytes of host memory used
-host_seconds 11356.03 # Real time elapsed on the host
-host_tick_rate 65366964 # Simulator tick rate (ticks/s)
+host_inst_rate 178472 # Simulator instruction rate (inst/s)
+host_mem_usage 202004 # Number of bytes of host memory used
+host_seconds 9727.25 # Real time elapsed on the host
+host_tick_rate 76312348 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 127392983 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 67515291 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 621608435 # Number of loads inserted to the mem dependence unit.
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 19:13:16
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:46
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 3454414 # Simulator instruction rate (inst/s)
-host_mem_usage 193640 # Number of bytes of host memory used
-host_seconds 526.80 # Real time elapsed on the host
-host_tick_rate 1733469179 # Simulator tick rate (ticks/s)
+host_inst_rate 3337847 # Simulator instruction rate (inst/s)
+host_mem_usage 193672 # Number of bytes of host memory used
+host_seconds 545.20 # Real time elapsed on the host
+host_tick_rate 1674974438 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780127 # Number of instructions simulated
sim_seconds 0.913189 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 18:32:56
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:45
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 2843037 # Simulator instruction rate (inst/s)
-host_mem_usage 201092 # Number of bytes of host memory used
-host_seconds 640.08 # Real time elapsed on the host
-host_tick_rate 4261930074 # Simulator tick rate (ticks/s)
+host_inst_rate 1294592 # Simulator instruction rate (inst/s)
+host_mem_usage 201124 # Number of bytes of host memory used
+host_seconds 1405.68 # Real time elapsed on the host
+host_tick_rate 1940692275 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780127 # Number of instructions simulated
sim_seconds 2.727991 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 18:47:24
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:45
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted
global.BPredUnit.lookups 19468548 # Number of BP lookups
global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target.
-host_inst_rate 134854 # Simulator instruction rate (inst/s)
-host_mem_usage 207240 # Number of bytes of host memory used
-host_seconds 624.23 # Real time elapsed on the host
-host_tick_rate 65390701 # Simulator tick rate (ticks/s)
+host_inst_rate 123995 # Simulator instruction rate (inst/s)
+host_mem_usage 207276 # Number of bytes of host memory used
+host_seconds 678.90 # Real time elapsed on the host
+host_tick_rate 60124800 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit.
sim_seconds 0.040819 # Number of seconds simulated
sim_ticks 40818658500 # Number of ticks simulated
system.cpu.commit.COM:branches 10240685 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 2855803 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 2855802 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 73457195
+system.cpu.commit.COM:committed_per_cycle.samples 73457196
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 36278942 4938.79%
- 1 18156305 2471.69%
- 2 7455514 1014.95%
- 3 3880418 528.26%
+ 0 36278941 4938.79%
+ 1 18156304 2471.68%
+ 2 7455517 1014.95%
+ 3 3880419 528.26%
4 2046448 278.59%
5 1301140 177.13%
6 721823 98.26%
7 760802 103.57%
- 8 2855803 388.77%
+ 8 2855802 388.77%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 23402422 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 30625.144175 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32084.980237 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 30623.414072 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32082.015810 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 23401555 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 26552000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 26550500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 867 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 361 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 16235000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 16233500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 29903525 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 35255.478247 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35297.410692 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 35255.314688 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency
system.cpu.dcache.demand_hits 29894354 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 323327991 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 323326491 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000307 # miss rate for demand accesses
system.cpu.dcache.demand_misses 9171 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 6814 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 83195997 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 83194497 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2357 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 29903525 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 35255.478247 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35297.410692 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 35255.314688 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 29894354 # number of overall hits
-system.cpu.dcache.overall_miss_latency 323327991 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 323326491 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000307 # miss rate for overall accesses
system.cpu.dcache.overall_misses 9171 # number of overall misses
system.cpu.dcache.overall_mshr_hits 6814 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 83195997 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 83194497 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2357 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements 159 # number of replacements
system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1458.381237 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 1458.398369 # Cycle average of tags in use
system.cpu.dcache.total_refs 29894629 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 105 # number of writebacks
system.cpu.decode.DECODE:BranchMispred 12597 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3039308 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 162679523 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 39569073 # Number of cycles decode is idle
+system.cpu.decode.DECODE:IdleCycles 39569074 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 29917869 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 8071146 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 45156 # Number of squashed instructions handled by decode
system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.052430 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 81528342
+system.cpu.fetch.rateDist.samples 81528343
system.cpu.fetch.rateDist.min_value 0
- 0 50560377 6201.57%
+ 0 50560378 6201.57%
1 3114212 381.98%
2 2012618 246.86%
3 3505366 429.96%
system.cpu.icache.total_refs 19218965 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 108976 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 108975 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 12812003 # Number of branches executed
system.cpu.iew.EXEC:nop 12599027 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.247521 # Inst execution rate
system.cpu.iew.EXEC:refs 31962516 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 7194632 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 90937299 # num instructions consuming a value
+system.cpu.iew.WB:consumers 90937302 # num instructions consuming a value
system.cpu.iew.WB:count 99943821 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.723990 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 65837671 # num instructions producing a value
+system.cpu.iew.WB:producers 65837672 # num instructions producing a value
system.cpu.iew.WB:rate 1.224242 # insts written-back per cycle
system.cpu.iew.WB:sent 100859242 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 2125730 # Number of branch mispredicts detected at execute
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 81528342
+system.cpu.iq.ISSUE:issued_per_cycle.samples 81528343
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 35305774 4330.49%
- 1 18904883 2318.81%
- 2 11574998 1419.75%
+ 1 18904885 2318.81%
+ 2 11574997 1419.75%
3 6762756 829.50%
4 5075415 622.53%
5 2394533 293.71%
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 10561 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34278.518519 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.296296 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34278.222222 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 7186 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 115690000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 115689000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.319572 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3375 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 104896000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 104895000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319572 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3375 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 12296 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34416.634051 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.234834 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34416.438356 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 7186 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 175869000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 175868000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.415582 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5110 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 159586500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 159585500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.415582 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5110 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34416.634051 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.234834 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34416.438356 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 7186 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 175869000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 175868000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.415582 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5110 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 159586500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 159585500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.415582 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5110 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3331 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2244.752447 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 2244.769579 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 964182 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 40833182 # Number of cycles rename is idle
+system.cpu.rename.RENAME:IdleCycles 40833183 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 973065 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 202958583 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 157334532 # Number of instructions processed by rename
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 21:16:59
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:29:52
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/o3-timing
-Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
-Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 5620505 # Simulator instruction rate (inst/s)
-host_mem_usage 198560 # Number of bytes of host memory used
-host_seconds 16.35 # Real time elapsed on the host
-host_tick_rate 2810224606 # Simulator tick rate (ticks/s)
+host_inst_rate 2797283 # Simulator instruction rate (inst/s)
+host_mem_usage 198592 # Number of bytes of host memory used
+host_seconds 32.85 # Real time elapsed on the host
+host_tick_rate 1398634763 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.045952 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 19:15:18
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:45
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-atomic
-Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sav
-Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 1922347 # Simulator instruction rate (inst/s)
-host_mem_usage 206016 # Number of bytes of host memory used
-host_seconds 47.81 # Real time elapsed on the host
-host_tick_rate 2483835101 # Simulator tick rate (ticks/s)
+host_inst_rate 1637033 # Simulator instruction rate (inst/s)
+host_mem_usage 206044 # Number of bytes of host memory used
+host_seconds 56.14 # Real time elapsed on the host
+host_tick_rate 2115189911 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
sim_seconds 0.118747 # Number of seconds simulated
-sim_ticks 118747191000 # Number of ticks simulated
+sim_ticks 118747246000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 51303.797468 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48303.797468 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 24318000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 22896000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11923.977948 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55045.863695 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52045.863695 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 26494968 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 128422000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 55046.272494 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 128478000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2333 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 121423000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 121476000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2333 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55045.863695 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52045.863695 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55046.272494 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 26494968 # number of overall hits
-system.cpu.dcache.overall_miss_latency 128422000 # number of overall miss cycles
+system.cpu.dcache.overall_hits 26494967 # number of overall hits
+system.cpu.dcache.overall_miss_latency 128478000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2333 # number of overall misses
+system.cpu.dcache.overall_misses 2334 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 121423000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 121476000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2333 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 157 # number of replacements
-system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1441.023190 # Cycle average of tags in use
-system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 1442.022508 # Cycle average of tags in use
+system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 104 # number of writebacks
system.cpu.dtb.accesses 26497334 # DTB accesses
system.cpu.icache.replacements 6681 # number of replacements
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1418.026644 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1418.025998 # Cycle average of tags in use
system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_miss_latency 69920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 8984 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 158184000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.338602 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 3042 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 121680000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338602 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 3042 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.970090 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 1.969435 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 249080000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.446329 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 4790 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency 249132000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.446380 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 4791 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 191600000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.446329 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 4790 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 191640000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.446380 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 4791 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 10732 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 5942 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 249080000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.446329 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 4790 # number of overall misses
+system.cpu.l2cache.overall_miss_latency 249132000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.446380 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 4791 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 191600000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.446329 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 4790 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 191640000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.446380 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 4791 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 3009 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 3010 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2021.060296 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 2022.059349 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 237494382 # number of cpu cycles simulated
+system.cpu.numCycles 237494492 # number of cpu cycles simulated
system.cpu.num_insts 91903056 # Number of instructions executed
system.cpu.num_refs 26537141 # Number of memory references
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 18:41:43
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:28:54
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/70.twolf/alpha/tru64/simple-timing
-Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav
-Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 649 # Number of BTB hits
-global.BPredUnit.BTBLookups 1748 # Number of BTB lookups
+global.BPredUnit.BTBHits 806 # Number of BTB hits
+global.BPredUnit.BTBLookups 1937 # Number of BTB lookups
global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1246 # Number of conditional branches predicted
-global.BPredUnit.lookups 2108 # Number of BP lookups
-global.BPredUnit.usedRAS 301 # Number of times the RAS was used to get a target.
-host_inst_rate 86240 # Simulator instruction rate (inst/s)
-host_mem_usage 198988 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
-host_tick_rate 169229614 # Simulator tick rate (ticks/s)
+global.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 1370 # Number of conditional branches predicted
+global.BPredUnit.lookups 2263 # Number of BP lookups
+global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target.
+host_inst_rate 7058 # Simulator instruction rate (inst/s)
+host_mem_usage 199016 # Number of bytes of host memory used
+host_seconds 0.90 # Real time elapsed on the host
+host_tick_rate 13784618 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 28 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2214 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1262 # Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.conflictingStores 29 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 2287 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1266 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 6297 # Number of instructions simulated
+sim_insts 6386 # Number of instructions simulated
sim_seconds 0.000012 # Number of seconds simulated
-sim_ticks 12391500 # Number of ticks simulated
-system.cpu.commit.COM:branches 1012 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 120 # number cycles where commit BW limit reached
+sim_ticks 12474500 # Number of ticks simulated
+system.cpu.commit.COM:branches 1051 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 12114
+system.cpu.commit.COM:committed_per_cycle.samples 12416
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 9249 7634.97%
- 1 1607 1326.56%
- 2 479 395.41%
- 3 271 223.71%
- 4 137 113.09%
- 5 121 99.88%
- 6 87 71.82%
- 7 43 35.50%
- 8 120 99.06%
+ 0 9513 7661.89%
+ 1 1627 1310.41%
+ 2 488 393.04%
+ 3 267 215.05%
+ 4 153 123.23%
+ 5 104 83.76%
+ 6 96 77.32%
+ 7 53 42.69%
+ 8 115 92.62%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
-system.cpu.commit.COM:count 6314 # Number of instructions committed
-system.cpu.commit.COM:loads 1168 # Number of loads committed
+system.cpu.commit.COM:count 6403 # Number of instructions committed
+system.cpu.commit.COM:loads 1185 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 2030 # Number of memory references committed
+system.cpu.commit.COM:refs 2050 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 6314 # The number of committed instructions
+system.cpu.commit.branchMispredicts 367 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4365 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 6297 # Number of Instructions Simulated
-system.cpu.committedInsts_total 6297 # Number of Instructions Simulated
-system.cpu.cpi 3.935842 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.935842 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1738 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 34857.142857 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.373737 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1577 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 5612000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.092635 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 161 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 62 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 3587500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.056962 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 99 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 35059.055118 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35660.919540 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 481 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 13357500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.441995 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 381 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 294 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 3102500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses
+system.cpu.commit.commitSquashedInsts 4640 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 6386 # Number of Instructions Simulated
+system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
+system.cpu.cpi 3.906984 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.906984 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1793 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 34316.091954 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.623762 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1619 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 5971000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.097044 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 174 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 3660000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.056330 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 35168.421053 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35747.126437 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 13364000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 3110000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 12.156977 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 12.281609 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2600 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 34999.077491 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35967.741935 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2058 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 18969500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.208462 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 542 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 6690000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.071538 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 2658 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 34900.722022 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 2104 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 19335000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.208427 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 554 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 366 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 6770000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.070730 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2600 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 34999.077491 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35967.741935 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2058 # number of overall hits
-system.cpu.dcache.overall_miss_latency 18969500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.208462 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 542 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 6690000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.071538 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 186 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 2104 # number of overall hits
+system.cpu.dcache.overall_miss_latency 19335000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.208427 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 554 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 366 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 6770000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.070730 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 172 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 109.051613 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2091 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 110.270477 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2137 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 1043 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 71 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 168 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 11945 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 8815 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2203 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 855 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 208 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:BlockedCycles 1058 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 74 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 192 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 12405 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 8939 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 2366 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 897 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 2892 # DTB accesses
+system.cpu.dtb.accesses 2951 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 2831 # DTB hits
+system.cpu.dtb.hits 2890 # DTB hits
system.cpu.dtb.misses 61 # DTB misses
-system.cpu.dtb.read_accesses 1821 # DTB read accesses
+system.cpu.dtb.read_accesses 1876 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 1785 # DTB read hits
+system.cpu.dtb.read_hits 1840 # DTB read hits
system.cpu.dtb.read_misses 36 # DTB read misses
-system.cpu.dtb.write_accesses 1071 # DTB write accesses
+system.cpu.dtb.write_accesses 1075 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 1046 # DTB write hits
+system.cpu.dtb.write_hits 1050 # DTB write hits
system.cpu.dtb.write_misses 25 # DTB write misses
-system.cpu.fetch.Branches 2108 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1704 # Number of cache lines fetched
-system.cpu.fetch.Cycles 4044 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 12761 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.085055 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1704 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 950 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.514889 # Number of inst fetches per cycle
+system.cpu.fetch.Branches 2263 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched
+system.cpu.fetch.Cycles 4308 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 13251 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.090701 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.531102 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 12970
+system.cpu.fetch.rateDist.samples 13314
system.cpu.fetch.rateDist.min_value 0
- 0 10663 8221.28%
- 1 241 185.81%
- 2 214 165.00%
- 3 169 130.30%
- 4 208 160.37%
- 5 163 125.67%
- 6 215 165.77%
- 7 128 98.69%
- 8 969 747.11%
+ 0 10844 8144.81%
+ 1 252 189.27%
+ 2 238 178.76%
+ 3 230 172.75%
+ 4 272 204.30%
+ 5 162 121.68%
+ 6 232 174.25%
+ 7 129 96.89%
+ 8 955 717.29%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 1704 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35319.248826 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35254.870130 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1278 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 15046000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.250000 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 118 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 10858500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.180751 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 1802 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35400.943396 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35286.644951 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1378 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 15010000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.235294 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 424 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 117 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 10833000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.170366 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 4.149351 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 4.488599 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1704 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35319.248826 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35254.870130 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1278 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 15046000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.250000 # miss rate for demand accesses
-system.cpu.icache.demand_misses 426 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 118 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 10858500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.180751 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 308 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 1802 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35400.943396 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1378 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 15010000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.235294 # miss rate for demand accesses
+system.cpu.icache.demand_misses 424 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 117 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 10833000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.170366 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1704 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35319.248826 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35254.870130 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1278 # number of overall hits
-system.cpu.icache.overall_miss_latency 15046000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.250000 # miss rate for overall accesses
-system.cpu.icache.overall_misses 426 # number of overall misses
-system.cpu.icache.overall_mshr_hits 118 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 10858500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.180751 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 308 # number of overall MSHR misses
+system.cpu.icache.overall_hits 1378 # number of overall hits
+system.cpu.icache.overall_miss_latency 15010000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.235294 # miss rate for overall accesses
+system.cpu.icache.overall_misses 424 # number of overall misses
+system.cpu.icache.overall_mshr_hits 117 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 10833000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.170366 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 308 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 160.409405 # Cycle average of tags in use
-system.cpu.icache.total_refs 1278 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 158.550695 # Cycle average of tags in use
+system.cpu.icache.total_refs 1378 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 11814 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 1375 # Number of branches executed
-system.cpu.iew.EXEC:nop 76 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.355148 # Inst execution rate
-system.cpu.iew.EXEC:refs 2900 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 1073 # Number of stores executed
+system.cpu.idleCycles 11636 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 1450 # Number of branches executed
+system.cpu.iew.EXEC:nop 82 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.362325 # Inst execution rate
+system.cpu.iew.EXEC:refs 2959 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 1077 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5878 # num instructions consuming a value
-system.cpu.iew.WB:count 8512 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.747873 # average fanout of values written-back
+system.cpu.iew.WB:consumers 6020 # num instructions consuming a value
+system.cpu.iew.WB:count 8734 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.746013 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4396 # num instructions producing a value
-system.cpu.iew.WB:rate 0.343447 # insts written-back per cycle
-system.cpu.iew.WB:sent 8611 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 406 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 66 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2214 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 181 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1262 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 10713 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 1827 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 299 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 8802 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 4491 # num instructions producing a value
+system.cpu.iew.WB:rate 0.350060 # insts written-back per cycle
+system.cpu.iew.WB:sent 8835 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 102 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 11078 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 1882 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 305 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 9040 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 855 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking
+system.cpu.iew.iewSquashCycles 897 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1046 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 400 # Number of stores squashed
+system.cpu.iew.lsq.thread.0.squashedLoads 1102 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 401 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.254075 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.254075 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 9101 # Type of FU issued
+system.cpu.iew.predictedTakenIncorrect 138 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.255952 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.255952 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 9345 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 2 0.02% # Type of FU issued
- IntAlu 6072 66.72% # Type of FU issued
+ IntAlu 6254 66.92% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1928 21.18% # Type of FU issued
- MemWrite 1096 12.04% # Type of FU issued
+ MemRead 1986 21.25% # Type of FU issued
+ MemWrite 1100 11.77% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 93 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.010219 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.011236 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 2 2.15% # attempts to use FU when none available
+ IntAlu 14 13.33% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 56 60.22% # attempts to use FU when none available
- MemWrite 35 37.63% # attempts to use FU when none available
+ MemRead 56 53.33% # attempts to use FU when none available
+ MemWrite 35 33.33% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 12970
+system.cpu.iq.ISSUE:issued_per_cycle.samples 13314
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 8890 6854.28%
- 1 1667 1285.27%
- 2 1037 799.54%
- 3 696 536.62%
- 4 340 262.14%
- 5 189 145.72%
- 6 103 79.41%
- 7 35 26.99%
- 8 13 10.02%
+ 0 9113 6844.67%
+ 1 1716 1288.87%
+ 2 1071 804.42%
+ 3 725 544.54%
+ 4 355 266.64%
+ 5 172 129.19%
+ 6 115 86.38%
+ 7 34 25.54%
+ 8 13 9.76%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 0.367213 # Inst issue rate
-system.cpu.iq.iqInstsAdded 10614 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 9101 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3909 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2399 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 1737 # ITB accesses
+system.cpu.iq.ISSUE:rate 0.374549 # Inst issue rate
+system.cpu.iq.iqInstsAdded 10972 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 9345 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 4189 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 2547 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 1838 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 1704 # ITB hits
-system.cpu.itb.misses 33 # ITB misses
+system.cpu.itb.hits 1802 # ITB hits
+system.cpu.itb.misses 36 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.109589 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31294.520548 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2511500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.945205 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31465.753425 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 2522000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2284500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 407 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34399.014778 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31224.137931 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34421.375921 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31240.786241 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 13966000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.997543 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 406 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 12677000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997543 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 406 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency 14009500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 12715000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34357.142857 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31142.857143 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 481000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.002551 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 480 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34399.791232 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31234.864301 # average overall mshr miss latency
+system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34440.625000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31275 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 16477500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.997917 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 479 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency 16531500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 14961500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.997917 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 479 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 15012000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 480 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34399.791232 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31234.864301 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 16477500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.997917 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 479 # number of overall misses
+system.cpu.l2cache.overall_miss_latency 16531500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 480 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 14961500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.997917 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 479 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 15012000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 392 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 215.607487 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 214.901533 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 24784 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 319 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4537 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 8963 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 264 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14577 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11538 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8602 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 2108 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 855 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 294 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4065 # Number of HB maps that are undone due to squashing
+system.cpu.numCycles 24950 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 371 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 9094 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 226 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 15058 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 11988 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 8902 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 2263 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 897 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 258 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 4319 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 719 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 663 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed
-system.cpu.timesIdled 242 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 237 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 19:13:15
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:44
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 12391500 because target called exit()
+Exiting @ tick 12474500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 598748 # Simulator instruction rate (inst/s)
-host_mem_usage 190820 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 294136747 # Simulator tick rate (ticks/s)
+host_inst_rate 6758 # Simulator instruction rate (inst/s)
+host_mem_usage 190848 # Number of bytes of host memory used
+host_seconds 0.95 # Real time elapsed on the host
+host_tick_rate 3391912 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 6315 # Number of instructions simulated
+sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
-sim_ticks 3170500 # Number of ticks simulated
-system.cpu.dtb.accesses 2040 # DTB accesses
+sim_ticks 3215000 # Number of ticks simulated
+system.cpu.dtb.accesses 2060 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 2030 # DTB hits
+system.cpu.dtb.hits 2050 # DTB hits
system.cpu.dtb.misses 10 # DTB misses
-system.cpu.dtb.read_accesses 1175 # DTB read accesses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 1168 # DTB read hits
+system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
-system.cpu.dtb.write_accesses 865 # DTB write accesses
+system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 862 # DTB write hits
+system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 6342 # ITB accesses
+system.cpu.itb.accesses 6431 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 6325 # ITB hits
+system.cpu.itb.hits 6414 # ITB hits
system.cpu.itb.misses 17 # ITB misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 6342 # number of cpu cycles simulated
-system.cpu.num_insts 6315 # Number of instructions executed
-system.cpu.num_refs 2040 # Number of memory references
+system.cpu.numCycles 6431 # number of cpu cycles simulated
+system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.num_refs 2060 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 21:40:14
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:44
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 3170500 because target called exit()
+Exiting @ tick 3215000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 472326 # Simulator instruction rate (inst/s)
-host_mem_usage 198180 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 2462369543 # Simulator tick rate (ticks/s)
+host_inst_rate 68165 # Simulator instruction rate (inst/s)
+host_mem_usage 198212 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
+host_tick_rate 358563073 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 6315 # Number of instructions simulated
+sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000034 # Number of seconds simulated
-sim_ticks 33503000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 1168 # number of ReadReq accesses(hits+misses)
+sim_ticks 33777000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1076 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 5152000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.078767 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 4876000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.078767 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 5320000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 5035000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 775 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 4872000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.100928 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.303030 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2030 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1851 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10024000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.088177 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 179 # number of demand (read+write) misses
+system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 10192000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 9487000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.088177 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 179 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 9646000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2030 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1851 # number of overall hits
-system.cpu.dcache.overall_miss_latency 10024000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.088177 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 179 # number of overall misses
+system.cpu.dcache.overall_hits 1868 # number of overall hits
+system.cpu.dcache.overall_miss_latency 10192000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 182 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 9487000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.088177 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 179 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 9646000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 102.087516 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1865 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 104.111261 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dtb.accesses 2040 # DTB accesses
+system.cpu.dtb.accesses 2060 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 2030 # DTB hits
+system.cpu.dtb.hits 2050 # DTB hits
system.cpu.dtb.misses 10 # DTB misses
-system.cpu.dtb.read_accesses 1175 # DTB read accesses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 1168 # DTB read hits
+system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
-system.cpu.dtb.write_accesses 865 # DTB write accesses
+system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 862 # DTB write hits
+system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
-system.cpu.icache.ReadReq_accesses 6326 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 6047 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.044104 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.044104 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 21.673835 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 6326 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
-system.cpu.icache.demand_hits 6047 # number of demand (read+write) hits
+system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.044104 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses
system.cpu.icache.demand_misses 279 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.044104 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate 0.043492 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 6326 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 6047 # number of overall hits
+system.cpu.icache.overall_hits 6136 # number of overall hits
system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.044104 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses
system.cpu.icache.overall_misses 279 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.044104 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate 0.043492 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 129.637082 # Cycle average of tags in use
-system.cpu.icache.total_refs 6047 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 128.649737 # Cycle average of tags in use
+system.cpu.icache.total_refs 6136 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 6343 # ITB accesses
+system.cpu.itb.accesses 6432 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 6326 # ITB hits
+system.cpu.itb.hits 6415 # ITB hits
system.cpu.itb.misses 17 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 371 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses 374 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 19240000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.997305 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 370 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 14800000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997305 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency 19396000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.997326 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 373 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.002809 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.002786 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 23036000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.997748 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 443 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency 23192000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 17720000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.997748 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 443 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 23036000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.997748 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 443 # number of overall misses
+system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 446 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 17720000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.997748 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 443 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 356 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 178.910312 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 179.928092 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 67006 # number of cpu cycles simulated
-system.cpu.num_insts 6315 # Number of instructions executed
-system.cpu.num_refs 2040 # Number of memory references
+system.cpu.numCycles 67554 # number of cpu cycles simulated
+system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.num_refs 2060 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 19:13:17
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:46
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 33503000 because target called exit()
+Exiting @ tick 33777000 because target called exit()
global.BPredUnit.condPredicted 447 # Number of conditional branches predicted
global.BPredUnit.lookups 859 # Number of BP lookups
global.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target.
-host_inst_rate 5854 # Simulator instruction rate (inst/s)
-host_mem_usage 197984 # Number of bytes of host memory used
-host_seconds 0.41 # Real time elapsed on the host
-host_tick_rate 17609622 # Simulator tick rate (ticks/s)
+host_inst_rate 31288 # Simulator instruction rate (inst/s)
+host_mem_usage 198012 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
+host_tick_rate 93885607 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 738 # Number of loads inserted to the mem dependence unit.
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 18:32:55
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:29:52
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 229372 # Simulator instruction rate (inst/s)
-host_mem_usage 189868 # Number of bytes of host memory used
+host_inst_rate 334328 # Simulator instruction rate (inst/s)
+host_mem_usage 189900 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 113875724 # Simulator tick rate (ticks/s)
+host_tick_rate 162370166 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 19:15:35
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:24:43
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 251832 # Simulator instruction rate (inst/s)
-host_mem_usage 197320 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 1657349995 # Simulator tick rate (ticks/s)
+host_inst_rate 59950 # Simulator instruction rate (inst/s)
+host_mem_usage 197352 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
+host_tick_rate 402241104 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000017 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 19:15:17
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:46
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 854 # Number of BTB hits
-global.BPredUnit.BTBLookups 4386 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 172 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 1443 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 2855 # Number of conditional branches predicted
-global.BPredUnit.lookups 5041 # Number of BP lookups
-global.BPredUnit.usedRAS 646 # Number of times the RAS was used to get a target.
-host_inst_rate 76947 # Simulator instruction rate (inst/s)
-host_mem_usage 199748 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
-host_tick_rate 85614119 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 23 # Number of conflicting loads.
-memdepunit.memDep.conflictingLoads 42 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 9 # Number of conflicting stores.
-memdepunit.memDep.conflictingStores 25 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2327 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedLoads 2333 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1262 # Number of stores inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1249 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 916 # Number of BTB hits
+global.BPredUnit.BTBLookups 4733 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 1595 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 3153 # Number of conditional branches predicted
+global.BPredUnit.lookups 5548 # Number of BP lookups
+global.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target.
+host_inst_rate 85524 # Simulator instruction rate (inst/s)
+host_mem_usage 199540 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
+host_tick_rate 95322021 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads.
+memdepunit.memDep.conflictingLoads 58 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 4 # Number of conflicting stores.
+memdepunit.memDep.conflictingStores 32 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 2431 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 2520 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1282 # Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1303 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 12595 # Number of instructions simulated
+sim_insts 12773 # Number of instructions simulated
sim_seconds 0.000014 # Number of seconds simulated
-sim_ticks 14029500 # Number of ticks simulated
-system.cpu.commit.COM:branches 2024 # Number of branches committed
-system.cpu.commit.COM:branches_0 1012 # Number of branches committed
-system.cpu.commit.COM:branches_1 1012 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 158 # number cycles where commit BW limit reached
+sim_ticks 14251500 # Number of ticks simulated
+system.cpu.commit.COM:branches 2102 # Number of branches committed
+system.cpu.commit.COM:branches_0 1051 # Number of branches committed
+system.cpu.commit.COM:branches_1 1051 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 122 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 21929
+system.cpu.commit.COM:committed_per_cycle.samples 22837
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 16145 7362.40%
- 1 3000 1368.05%
- 2 1194 544.48%
- 3 576 262.67%
- 4 357 162.80%
- 5 253 115.37%
- 6 166 75.70%
- 7 80 36.48%
- 8 158 72.05%
+ 0 16880 7391.51%
+ 1 3016 1320.66%
+ 2 1386 606.91%
+ 3 576 252.22%
+ 4 326 142.75%
+ 5 268 117.35%
+ 6 170 74.44%
+ 7 93 40.72%
+ 8 122 53.42%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
-system.cpu.commit.COM:count 12629 # Number of instructions committed
-system.cpu.commit.COM:count_0 6314 # Number of instructions committed
-system.cpu.commit.COM:count_1 6315 # Number of instructions committed
-system.cpu.commit.COM:loads 2336 # Number of loads committed
-system.cpu.commit.COM:loads_0 1168 # Number of loads committed
-system.cpu.commit.COM:loads_1 1168 # Number of loads committed
+system.cpu.commit.COM:count 12807 # Number of instructions committed
+system.cpu.commit.COM:count_0 6403 # Number of instructions committed
+system.cpu.commit.COM:count_1 6404 # Number of instructions committed
+system.cpu.commit.COM:loads 2370 # Number of loads committed
+system.cpu.commit.COM:loads_0 1185 # Number of loads committed
+system.cpu.commit.COM:loads_1 1185 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed
system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 4060 # Number of memory references committed
-system.cpu.commit.COM:refs_0 2030 # Number of memory references committed
-system.cpu.commit.COM:refs_1 2030 # Number of memory references committed
+system.cpu.commit.COM:refs 4100 # Number of memory references committed
+system.cpu.commit.COM:refs_0 2050 # Number of memory references committed
+system.cpu.commit.COM:refs_1 2050 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed
system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 1061 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 12629 # The number of committed instructions
+system.cpu.commit.branchMispredicts 1166 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 9861 # The number of squashed insts skipped by commit
-system.cpu.committedInsts_0 6297 # Number of Instructions Simulated
-system.cpu.committedInsts_1 6298 # Number of Instructions Simulated
-system.cpu.committedInsts_total 12595 # Number of Instructions Simulated
-system.cpu.cpi_0 4.456090 # CPI: Cycles Per Instruction
-system.cpu.cpi_1 4.455383 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.227868 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 3746 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses_0 3746 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency_0 35521.212121 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 36972.222222 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 3416 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits_0 3416 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 11722000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency_0 11722000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate_0 0.088094 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 330 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses_0 330 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 132 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits_0 132 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 7320500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency_0 7320500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052856 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 198 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses_0 198 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 1724 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses_0 1724 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency_0 33638.157895 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 35974.137931 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 964 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits_0 964 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 25565000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency_0 25565000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate_0 0.440835 # miss rate for WriteReq accesses
+system.cpu.commit.commitSquashedInsts 10895 # The number of squashed insts skipped by commit
+system.cpu.committedInsts_0 6386 # Number of Instructions Simulated
+system.cpu.committedInsts_1 6387 # Number of Instructions Simulated
+system.cpu.committedInsts_total 12773 # Number of Instructions Simulated
+system.cpu.cpi_0 4.463514 # CPI: Cycles Per Instruction
+system.cpu.cpi_1 4.462815 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.231582 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 3925 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses_0 3925 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency_0 35473.913043 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 36849.514563 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 3580 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits_0 3580 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 12238500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency_0 12238500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate_0 0.087898 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 345 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses_0 345 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 139 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits_0 139 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency_0 7591000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052484 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 206 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses_0 206 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses_0 1730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency_0 33703.947368 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 36103.448276 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 970 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits_0 970 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 25615000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency_0 25615000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate_0 0.439306 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses_0 760 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 586 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits_0 586 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 6259500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency_0 6259500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100928 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_latency 6282000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency_0 6282000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100578 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 12.915698 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 13.102273 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 5470 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses_0 5470 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses 5655 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses_0 5655 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency_0 34208.256881 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency_0 34256.561086 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency_0 36505.376344 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.demand_hits 4380 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits_0 4380 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits 4550 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits_0 4550 # number of demand (read+write) hits
system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 37287000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency_0 37287000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 37853500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency_0 37853500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate_0 0.199269 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate_0 0.195402 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1090 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses_0 1090 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses 1105 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses_0 1105 # number of demand (read+write) misses
system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 718 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits_0 718 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits 725 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits_0 725 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 13580000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency_0 13580000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 13873000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency_0 13873000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate_0 0.068007 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate_0 0.067197 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 372 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses_0 372 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 380 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses_0 380 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 5470 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses_0 5470 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses 5655 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses_0 5655 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency_0 34208.256881 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency_0 34256.561086 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency_0 36505.376344 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 4380 # number of overall hits
-system.cpu.dcache.overall_hits_0 4380 # number of overall hits
+system.cpu.dcache.overall_hits 4550 # number of overall hits
+system.cpu.dcache.overall_hits_0 4550 # number of overall hits
system.cpu.dcache.overall_hits_1 0 # number of overall hits
-system.cpu.dcache.overall_miss_latency 37287000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency_0 37287000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 37853500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency_0 37853500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate_0 0.199269 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate_0 0.195402 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1090 # number of overall misses
-system.cpu.dcache.overall_misses_0 1090 # number of overall misses
+system.cpu.dcache.overall_misses 1105 # number of overall misses
+system.cpu.dcache.overall_misses_0 1105 # number of overall misses
system.cpu.dcache.overall_misses_1 0 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 718 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits_0 718 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits 725 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits_0 725 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 13580000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency_0 13580000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 13873000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency_0 13873000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate_0 0.068007 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate_0 0.067197 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 372 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses_0 372 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses 380 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses_0 380 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.replacements_0 0 # number of replacements
system.cpu.dcache.replacements_1 0 # number of replacements
-system.cpu.dcache.sampled_refs 344 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 352 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 218.241072 # Cycle average of tags in use
-system.cpu.dcache.total_refs 4443 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 223.700041 # Cycle average of tags in use
+system.cpu.dcache.total_refs 4612 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dcache.writebacks_0 0 # number of writebacks
system.cpu.dcache.writebacks_1 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 5036 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 400 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 534 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 25996 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 32008 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 4597 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 1938 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 558 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 173 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 6094 # DTB accesses
+system.cpu.decode.DECODE:BlockedCycles 5062 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 441 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 602 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 27492 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 33392 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 4878 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 2128 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 668 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 186 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 6300 # DTB accesses
system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 5949 # DTB hits
+system.cpu.dtb.hits 6155 # DTB hits
system.cpu.dtb.misses 145 # DTB misses
-system.cpu.dtb.read_accesses 3938 # DTB read accesses
+system.cpu.dtb.read_accesses 4144 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 3853 # DTB read hits
-system.cpu.dtb.read_misses 85 # DTB read misses
+system.cpu.dtb.read_hits 4056 # DTB read hits
+system.cpu.dtb.read_misses 88 # DTB read misses
system.cpu.dtb.write_accesses 2156 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 2096 # DTB write hits
-system.cpu.dtb.write_misses 60 # DTB write misses
-system.cpu.fetch.Branches 5041 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 3820 # Number of cache lines fetched
-system.cpu.fetch.Cycles 8809 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 621 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 28977 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 1559 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.179651 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 3820 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 1500 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.032680 # Number of inst fetches per cycle
+system.cpu.dtb.write_hits 2099 # DTB write hits
+system.cpu.dtb.write_misses 57 # DTB write misses
+system.cpu.fetch.Branches 5548 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 4113 # Number of cache lines fetched
+system.cpu.fetch.Cycles 9444 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 613 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 30949 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 1714 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.194639 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 4113 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 1597 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.085777 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 21971
+system.cpu.fetch.rateDist.samples 22904
system.cpu.fetch.rateDist.min_value 0
- 0 17033 7752.49%
- 1 423 192.53%
- 2 326 148.38%
- 3 380 172.96%
- 4 411 187.06%
- 5 313 142.46%
- 6 429 195.26%
- 7 269 122.43%
- 8 2387 1086.43%
+ 0 17622 7693.85%
+ 1 416 181.63%
+ 2 353 154.12%
+ 3 477 208.26%
+ 4 425 185.56%
+ 5 349 152.38%
+ 6 442 192.98%
+ 7 261 113.95%
+ 8 2559 1117.27%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 3820 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses_0 3820 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency_0 35987.893462 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 35566.129032 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 2994 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits_0 2994 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 29726000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency_0 29726000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate_0 0.216230 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 826 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses_0 826 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 206 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits_0 206 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 22051000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency_0 22051000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate_0 0.162304 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 620 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses_0 620 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 4113 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses_0 4113 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency_0 35793.697979 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 35516.155089 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 3272 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits_0 3272 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 30102500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency_0 30102500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate_0 0.204474 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 841 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses_0 841 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 222 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits_0 222 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 21984500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency_0 21984500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate_0 0.150498 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 4.829032 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 5.285945 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 3820 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses_0 3820 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses 4113 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses_0 4113 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency_0 35987.893462 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency_0 35793.697979 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency_0 35566.129032 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
-system.cpu.icache.demand_hits 2994 # number of demand (read+write) hits
-system.cpu.icache.demand_hits_0 2994 # number of demand (read+write) hits
+system.cpu.icache.demand_hits 3272 # number of demand (read+write) hits
+system.cpu.icache.demand_hits_0 3272 # number of demand (read+write) hits
system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 29726000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency_0 29726000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 30102500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency_0 30102500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate_0 0.216230 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate_0 0.204474 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
-system.cpu.icache.demand_misses 826 # number of demand (read+write) misses
-system.cpu.icache.demand_misses_0 826 # number of demand (read+write) misses
+system.cpu.icache.demand_misses 841 # number of demand (read+write) misses
+system.cpu.icache.demand_misses_0 841 # number of demand (read+write) misses
system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 206 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits_0 206 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits 222 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits_0 222 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 22051000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency_0 22051000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 21984500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency_0 21984500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate_0 0.162304 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate_0 0.150498 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 620 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses_0 620 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 3820 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses_0 3820 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses 4113 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses_0 4113 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency_0 35987.893462 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency_0 35793.697979 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency_0 35566.129032 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 2994 # number of overall hits
-system.cpu.icache.overall_hits_0 2994 # number of overall hits
+system.cpu.icache.overall_hits 3272 # number of overall hits
+system.cpu.icache.overall_hits_0 3272 # number of overall hits
system.cpu.icache.overall_hits_1 0 # number of overall hits
-system.cpu.icache.overall_miss_latency 29726000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency_0 29726000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 30102500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency_0 30102500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles
system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate_0 0.216230 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate_0 0.204474 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
-system.cpu.icache.overall_misses 826 # number of overall misses
-system.cpu.icache.overall_misses_0 826 # number of overall misses
+system.cpu.icache.overall_misses 841 # number of overall misses
+system.cpu.icache.overall_misses_0 841 # number of overall misses
system.cpu.icache.overall_misses_1 0 # number of overall misses
-system.cpu.icache.overall_mshr_hits 206 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits_0 206 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits 222 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits_0 222 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 22051000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency_0 22051000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 21984500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency_0 21984500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate_0 0.162304 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate_0 0.150498 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 620 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses_0 620 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 6 # number of replacements
system.cpu.icache.replacements_0 6 # number of replacements
system.cpu.icache.replacements_1 0 # number of replacements
-system.cpu.icache.sampled_refs 620 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 322.256979 # Cycle average of tags in use
-system.cpu.icache.total_refs 2994 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 321.284131 # Cycle average of tags in use
+system.cpu.icache.total_refs 3272 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.writebacks_0 0 # number of writebacks
system.cpu.icache.writebacks_1 0 # number of writebacks
-system.cpu.idleCycles 6089 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 2958 # Number of branches executed
-system.cpu.iew.EXEC:branches_0 1488 # Number of branches executed
-system.cpu.iew.EXEC:branches_1 1470 # Number of branches executed
-system.cpu.iew.EXEC:nop 133 # number of nop insts executed
+system.cpu.idleCycles 5600 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 3160 # Number of branches executed
+system.cpu.iew.EXEC:branches_0 1573 # Number of branches executed
+system.cpu.iew.EXEC:branches_1 1587 # Number of branches executed
+system.cpu.iew.EXEC:nop 135 # number of nop insts executed
system.cpu.iew.EXEC:nop_0 70 # number of nop insts executed
-system.cpu.iew.EXEC:nop_1 63 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.660299 # Inst execution rate
-system.cpu.iew.EXEC:refs 6116 # number of memory reference insts executed
-system.cpu.iew.EXEC:refs_0 3062 # number of memory reference insts executed
-system.cpu.iew.EXEC:refs_1 3054 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 2176 # Number of stores executed
-system.cpu.iew.EXEC:stores_0 1102 # Number of stores executed
-system.cpu.iew.EXEC:stores_1 1074 # Number of stores executed
+system.cpu.iew.EXEC:nop_1 65 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.673940 # Inst execution rate
+system.cpu.iew.EXEC:refs 6321 # number of memory reference insts executed
+system.cpu.iew.EXEC:refs_0 3132 # number of memory reference insts executed
+system.cpu.iew.EXEC:refs_1 3189 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 2175 # Number of stores executed
+system.cpu.iew.EXEC:stores_0 1090 # Number of stores executed
+system.cpu.iew.EXEC:stores_1 1085 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed
system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 11542 # num instructions consuming a value
-system.cpu.iew.WB:consumers_0 5820 # num instructions consuming a value
-system.cpu.iew.WB:consumers_1 5722 # num instructions consuming a value
-system.cpu.iew.WB:count 17828 # cumulative count of insts written-back
-system.cpu.iew.WB:count_0 8981 # cumulative count of insts written-back
-system.cpu.iew.WB:count_1 8847 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 1.545155 # average fanout of values written-back
-system.cpu.iew.WB:fanout_0 0.771649 # average fanout of values written-back
-system.cpu.iew.WB:fanout_1 0.773506 # average fanout of values written-back
+system.cpu.iew.WB:consumers 11901 # num instructions consuming a value
+system.cpu.iew.WB:consumers_0 5984 # num instructions consuming a value
+system.cpu.iew.WB:consumers_1 5917 # num instructions consuming a value
+system.cpu.iew.WB:count 18426 # cumulative count of insts written-back
+system.cpu.iew.WB:count_0 9221 # cumulative count of insts written-back
+system.cpu.iew.WB:count_1 9205 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 1.552811 # average fanout of values written-back
+system.cpu.iew.WB:fanout_0 0.776404 # average fanout of values written-back
+system.cpu.iew.WB:fanout_1 0.776407 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 8917 # num instructions producing a value
-system.cpu.iew.WB:producers_0 4491 # num instructions producing a value
-system.cpu.iew.WB:producers_1 4426 # num instructions producing a value
-system.cpu.iew.WB:rate 0.635353 # insts written-back per cycle
-system.cpu.iew.WB:rate_0 0.320064 # insts written-back per cycle
-system.cpu.iew.WB:rate_1 0.315289 # insts written-back per cycle
-system.cpu.iew.WB:sent 18058 # cumulative count of insts sent to commit
-system.cpu.iew.WB:sent_0 9082 # cumulative count of insts sent to commit
-system.cpu.iew.WB:sent_1 8976 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 1215 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 1067 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 4660 # Number of dispatched load instructions
+system.cpu.iew.WB:producers 9240 # num instructions producing a value
+system.cpu.iew.WB:producers_0 4646 # num instructions producing a value
+system.cpu.iew.WB:producers_1 4594 # num instructions producing a value
+system.cpu.iew.WB:rate 0.646436 # insts written-back per cycle
+system.cpu.iew.WB:rate_0 0.323498 # insts written-back per cycle
+system.cpu.iew.WB:rate_1 0.322937 # insts written-back per cycle
+system.cpu.iew.WB:sent 18664 # cumulative count of insts sent to commit
+system.cpu.iew.WB:sent_0 9324 # cumulative count of insts sent to commit
+system.cpu.iew.WB:sent_1 9340 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 1342 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 1080 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 4951 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 801 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 2511 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 22574 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 3940 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts_0 1960 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts_1 1980 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1001 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 18528 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewDispSquashedInsts 727 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 2585 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 23775 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 4146 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts_0 2042 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts_1 2104 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1180 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 19210 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 1938 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 2128 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 66 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1159 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 400 # Number of stores squashed
+system.cpu.iew.lsq.thread.0.squashedLoads 1246 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 417 # Number of stores squashed
system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.1.forwLoads 58 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.1.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.1.forwLoads 72 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.1.memOrderViolation 61 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.1.memOrderViolation 68 # Number of memory ordering violations
system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.1.squashedLoads 1165 # Number of loads squashed
-system.cpu.iew.lsq.thread.1.squashedStores 387 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 127 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 964 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 251 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc_0 0.224412 # IPC: Instructions Per Cycle
-system.cpu.ipc_1 0.224448 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.448860 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 9816 # Type of FU issued
+system.cpu.iew.lsq.thread.1.squashedLoads 1335 # Number of loads squashed
+system.cpu.iew.lsq.thread.1.squashedStores 438 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 136 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 1080 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc_0 0.224039 # IPC: Instructions Per Cycle
+system.cpu.ipc_1 0.224074 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.448113 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 10179 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 2 0.02% # Type of FU issued
- IntAlu 6598 67.22% # Type of FU issued
+ IntAlu 6830 67.10% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 2077 21.16% # Type of FU issued
- MemWrite 1136 11.57% # Type of FU issued
+ MemRead 2173 21.35% # Type of FU issued
+ MemWrite 1171 11.50% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:FU_type_1 9713 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_1 10211 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_1.start_dist
No_OpClass 2 0.02% # Type of FU issued
- IntAlu 6508 67.00% # Type of FU issued
+ IntAlu 6842 67.01% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 2085 21.47% # Type of FU issued
- MemWrite 1115 11.48% # Type of FU issued
+ MemRead 2230 21.84% # Type of FU issued
+ MemWrite 1134 11.11% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_1.end_dist
-system.cpu.iq.ISSUE:FU_type 19529 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type 20390 # Type of FU issued
system.cpu.iq.ISSUE:FU_type.start_dist
No_OpClass 4 0.02% # Type of FU issued
- IntAlu 13106 67.11% # Type of FU issued
+ IntAlu 13672 67.05% # Type of FU issued
IntMult 2 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 4 0.02% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 4162 21.31% # Type of FU issued
- MemWrite 2251 11.53% # Type of FU issued
+ MemRead 4403 21.59% # Type of FU issued
+ MemWrite 2305 11.30% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 165 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_cnt_0 86 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_cnt_1 79 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.008449 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_busy_rate_0 0.004404 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_busy_rate_1 0.004045 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 172 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_cnt_0 87 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_cnt_1 85 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.008436 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate_0 0.004267 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate_1 0.004169 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 5 3.03% # attempts to use FU when none available
+ IntAlu 13 7.56% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 94 56.97% # attempts to use FU when none available
- MemWrite 66 40.00% # attempts to use FU when none available
+ MemRead 96 55.81% # attempts to use FU when none available
+ MemWrite 63 36.63% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 21971
+system.cpu.iq.ISSUE:issued_per_cycle.samples 22904
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 13541 6163.12%
- 1 3190 1451.91%
- 2 2253 1025.44%
- 3 1351 614.90%
- 4 834 379.59%
- 5 490 223.02%
- 6 205 93.30%
- 7 92 41.87%
- 8 15 6.83%
+ 0 14156 6180.58%
+ 1 3289 1435.99%
+ 2 2351 1026.46%
+ 3 1373 599.46%
+ 4 854 372.86%
+ 5 535 233.58%
+ 6 261 113.95%
+ 7 57 24.89%
+ 8 28 12.22%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 0.695973 # Inst issue rate
-system.cpu.iq.iqInstsAdded 22397 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 19529 # Number of instructions issued
+system.cpu.iq.ISSUE:rate 0.715338 # Inst issue rate
+system.cpu.iq.iqInstsAdded 23596 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 20390 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 8499 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 76 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 9662 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 4789 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 3871 # ITB accesses
+system.cpu.iq.iqSquashedOperandsExamined 5422 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 4162 # ITB accesses
system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 3820 # ITB hits
-system.cpu.itb.misses 51 # ITB misses
+system.cpu.itb.hits 4113 # ITB hits
+system.cpu.itb.misses 49 # ITB misses
system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34517.123288 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 31445.205479 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 5039500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency_0 5039500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34643.835616 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 31589.041096 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 5058000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency_0 5058000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses_0 146 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 4591000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 4591000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 4612000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 4612000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 146 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses_0 146 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 818 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses_0 818 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency_0 34572.916667 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 31431.372549 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_accesses 825 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses_0 825 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency_0 34555.285541 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 31414.337789 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 28211500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency_0 28211500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate_0 0.997555 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 816 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses_0 816 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 25648000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency_0 25648000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997555 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 816 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses_0 816 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency 28439000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency_0 28439000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate_0 0.997576 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 823 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses_0 823 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 25854000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency_0 25854000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997576 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 823 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses_0 823 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses_0 28 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 34410.714286 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 31232.142857 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 963500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency_0 963500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 34482.142857 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 31357.142857 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 965500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency_0 965500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses_0 28 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 874500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 874500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 878000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 878000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses_0 28 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs 6750 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.002538 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.002516 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 4 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 27000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 964 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses_0 964 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses 971 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses_0 971 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency_0 34564.449064 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency_0 34568.627451 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency_0 31433.471933 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 33251000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency_0 33251000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 33497000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency_0 33497000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate_0 0.997925 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate_0 0.997940 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 962 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses_0 962 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses 969 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses_0 969 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 30239000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency_0 30239000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 30466000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency_0 30466000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate_0 0.997925 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate_0 0.997940 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 962 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses_0 962 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses 969 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses_0 969 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated
system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 964 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses_0 964 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses 971 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses_0 971 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency_0 34564.449064 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency_0 34568.627451 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency_0 31433.471933 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.overall_hits_0 2 # number of overall hits
system.cpu.l2cache.overall_hits_1 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 33251000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency_0 33251000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 33497000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency_0 33497000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate_0 0.997925 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate_0 0.997940 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 962 # number of overall misses
-system.cpu.l2cache.overall_misses_0 962 # number of overall misses
+system.cpu.l2cache.overall_misses 969 # number of overall misses
+system.cpu.l2cache.overall_misses_0 969 # number of overall misses
system.cpu.l2cache.overall_misses_1 0 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 30239000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency_0 30239000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 30466000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency_0 30466000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate_0 0.997925 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate_0 0.997940 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 962 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses_0 962 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses 969 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses_0 969 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.replacements_0 0 # number of replacements
system.cpu.l2cache.replacements_1 0 # number of replacements
-system.cpu.l2cache.sampled_refs 788 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 795 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 431.449507 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 435.713880 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.writebacks_0 0 # number of writebacks
system.cpu.l2cache.writebacks_1 0 # number of writebacks
-system.cpu.numCycles 28060 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 2889 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 9074 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 32446 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 1291 # Number of times rename has blocked due to LSQ full
+system.cpu.numCycles 28504 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 2835 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IdleCycles 33866 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 1399 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 31166 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 24765 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 18538 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 4270 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 1938 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1355 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 9464 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 854 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:RenameLookups 32685 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 26128 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 19538 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 4546 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 2128 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1422 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 10372 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 849 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 3364 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 3399 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed
-system.cpu.timesIdled 254 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls
system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 18:30:32
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:28:54
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Hello world!
-Exiting @ tick 14029500 because target called exit()
+Exiting @ tick 14251500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 4457341 # Simulator instruction rate (inst/s)
-host_mem_usage 291000 # Number of bytes of host memory used
-host_seconds 14.16 # Real time elapsed on the host
-host_tick_rate 132088621816 # Simulator tick rate (ticks/s)
+host_inst_rate 3333474 # Simulator instruction rate (inst/s)
+host_mem_usage 290708 # Number of bytes of host memory used
+host_seconds 18.93 # Real time elapsed on the host
+host_tick_rate 98784311223 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 63113507 # Number of instructions simulated
sim_seconds 1.870336 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 22:27:11
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:32:52
+M5 compiled Dec 4 2008 21:30:58
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:37:23
M5 executing on zizzer
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 2960159 # Simulator instruction rate (inst/s)
-host_mem_usage 289760 # Number of bytes of host memory used
-host_seconds 20.27 # Real time elapsed on the host
-host_tick_rate 90209540739 # Simulator tick rate (ticks/s)
+host_inst_rate 2786128 # Simulator instruction rate (inst/s)
+host_mem_usage 289464 # Number of bytes of host memory used
+host_seconds 21.53 # Real time elapsed on the host
+host_tick_rate 84905818409 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 59995351 # Number of instructions simulated
sim_seconds 1.828356 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 22:27:11
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:28:06
+M5 compiled Dec 4 2008 21:30:58
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:37:01
M5 executing on zizzer
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 1529547 # Simulator instruction rate (inst/s)
-host_mem_usage 287776 # Number of bytes of host memory used
-host_seconds 38.82 # Real time elapsed on the host
-host_tick_rate 50799321587 # Simulator tick rate (ticks/s)
+host_inst_rate 1388930 # Simulator instruction rate (inst/s)
+host_mem_usage 287800 # Number of bytes of host memory used
+host_seconds 42.75 # Real time elapsed on the host
+host_tick_rate 46129218174 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 59379829 # Number of instructions simulated
sim_seconds 1.972135 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 22:27:11
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:29:36
+M5 compiled Dec 4 2008 21:30:58
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:38:12
M5 executing on zizzer
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 1640475 # Simulator instruction rate (inst/s)
-host_mem_usage 286536 # Number of bytes of host memory used
-host_seconds 34.24 # Real time elapsed on the host
-host_tick_rate 56375976626 # Simulator tick rate (ticks/s)
+host_inst_rate 1283720 # Simulator instruction rate (inst/s)
+host_mem_usage 286560 # Number of bytes of host memory used
+host_seconds 43.75 # Real time elapsed on the host
+host_tick_rate 44115985890 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 56165112 # Number of instructions simulated
sim_seconds 1.930166 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 22:27:11
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:27:38
+M5 compiled Dec 4 2008 21:30:58
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:37:43
M5 executing on zizzer
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 3131465 # Simulator instruction rate (inst/s)
-host_mem_usage 189960 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
-host_tick_rate 1563505663 # Simulator tick rate (ticks/s)
+host_inst_rate 4911987 # Simulator instruction rate (inst/s)
+host_mem_usage 189996 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
+host_tick_rate 2448419888 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500001 # Number of instructions simulated
sim_seconds 0.000250 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 19:15:34
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:27:20
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 1653831 # Simulator instruction rate (inst/s)
-host_mem_usage 197344 # Number of bytes of host memory used
-host_seconds 0.30 # Real time elapsed on the host
-host_tick_rate 2436827913 # Simulator tick rate (ticks/s)
+host_inst_rate 883179 # Simulator instruction rate (inst/s)
+host_mem_usage 197372 # Number of bytes of host memory used
+host_seconds 0.57 # Real time elapsed on the host
+host_tick_rate 1301859777 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500001 # Number of instructions simulated
sim_seconds 0.000737 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 19:15:35
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:29:51
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-host_inst_rate 1660926 # Simulator instruction rate (inst/s)
-host_seconds 1.20 # Real time elapsed on the host
-host_tick_rate 207598549 # Simulator tick rate (ticks/s)
+host_inst_rate 2958551 # Simulator instruction rate (inst/s)
+host_mem_usage 1121980 # Number of bytes of host memory used
+host_seconds 0.68 # Real time elapsed on the host
+host_tick_rate 369689554 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2000004 # Number of instructions simulated
sim_seconds 0.000250 # Number of seconds simulated
-0: system.remote_gdb.listener: listening for remote gdb on port 7002
-0: system.remote_gdb.listener: listening for remote gdb on port 7003
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-0: system.remote_gdb.listener: listening for remote gdb on port 7001
+warn: Sockets disabled, not accepting gdb connections
warn: be nice to actually delete the event here
gzip: stdout: Broken pipe
All Rights Reserved
-M5 compiled Nov 5 2008 17:12:56
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 17:19:26
-M5 executing on dhcp128036150089.central.yale.edu
-command line: build/ALPHA_SE/m5.fast -d simple-atomic wrapper.py
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:45
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re --stdout-file stdout --stderr-file stderr tests/run.py quick/30.eio-mp/alpha/eio/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
---------- Begin Simulation Statistics ----------
-host_inst_rate 803390 # Simulator instruction rate (inst/s)
-host_seconds 2.49 # Real time elapsed on the host
-host_tick_rate 296594923 # Simulator tick rate (ticks/s)
+host_inst_rate 1370296 # Simulator instruction rate (inst/s)
+host_mem_usage 204468 # Number of bytes of host memory used
+host_seconds 1.46 # Real time elapsed on the host
+host_tick_rate 505820394 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1999941 # Number of instructions simulated
sim_seconds 0.000738 # Number of seconds simulated
-0: system.remote_gdb.listener: listening for remote gdb on port 7002
-0: system.remote_gdb.listener: listening for remote gdb on port 7003
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-0: system.remote_gdb.listener: listening for remote gdb on port 7001
+warn: Sockets disabled, not accepting gdb connections
warn: be nice to actually delete the event here
gzip: stdout: Broken pipe
All Rights Reserved
-M5 compiled Nov 5 2008 17:12:56
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 17:26:45
-M5 executing on dhcp128036150089.central.yale.edu
-command line: build/ALPHA_SE/m5.fast -d output wrapper.py
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:30:50
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re --stdout-file stdout --stderr-file stderr tests/run.py quick/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
---------- Begin Simulation Statistics ----------
-host_mem_usage 324448 # Number of bytes of host memory used
-host_seconds 222.79 # Real time elapsed on the host
-host_tick_rate 1207024 # Simulator tick rate (ticks/s)
+host_mem_usage 324480 # Number of bytes of host memory used
+host_seconds 257.27 # Real time elapsed on the host
+host_tick_rate 1045249 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_seconds 0.000269 # Number of seconds simulated
sim_ticks 268915439 # Number of ticks simulated
All Rights Reserved
-M5 compiled Nov 5 2008 18:30:06
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 19:01:52
+M5 compiled Dec 4 2008 21:21:43
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:21:45
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re --stdout-file stdout --stderr-file stderr tests/run.py quick/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second
mem_mode=atomic
pal=/dist/m5/system/binaries/ts_osfpal
physmem=drivesys.physmem
-readfile=/z/hsul/work/m5/m5/configs/boot/netperf-server.rcS
+readfile=/z/hsul/work/m5/m5-tls/configs/boot/netperf-server.rcS
symbolfile=
system_rev=1024
system_type=34
mem_mode=atomic
pal=/dist/m5/system/binaries/ts_osfpal
physmem=testsys.physmem
-readfile=/z/hsul/work/m5/m5/configs/boot/netperf-stream-client.rcS
+readfile=/z/hsul/work/m5/m5-tls/configs/boot/netperf-stream-client.rcS
symbolfile=
system_rev=1024
system_type=34
drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted
drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-host_inst_rate 161007148 # Simulator instruction rate (inst/s)
-host_mem_usage 478492 # Number of bytes of host memory used
-host_seconds 1.70 # Real time elapsed on the host
-host_tick_rate 117815722486 # Simulator tick rate (ticks/s)
+host_inst_rate 200792296 # Simulator instruction rate (inst/s)
+host_mem_usage 476644 # Number of bytes of host memory used
+host_seconds 1.36 # Real time elapsed on the host
+host_tick_rate 146922204609 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 273294177 # Number of instructions simulated
sim_seconds 0.200001 # Number of seconds simulated
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-host_inst_rate 142489143379 # Simulator instruction rate (inst/s)
-host_mem_usage 478492 # Number of bytes of host memory used
+host_inst_rate 214516622449 # Simulator instruction rate (inst/s)
+host_mem_usage 476644 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
-host_tick_rate 385850761 # Simulator tick rate (ticks/s)
+host_tick_rate 582637509 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 273294177 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
All Rights Reserved
-M5 compiled Nov 5 2008 22:27:11
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 5 2008 22:28:13
+M5 compiled Dec 4 2008 21:30:58
+M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
+M5 commit date Thu Dec 04 18:04:32 2008 -0500
+M5 started Dec 4 2008 21:38:27
M5 executing on zizzer
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
projects / gem5.git / commitdiff