Added AIGER back-end to automatic back-end detection

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 08fee97419178fb900250bf10fb5aa92d5d1b0fe..3d0aca78e9988e368c8603ba0d4383c78d3b2d23 100644 (file)
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -903,6 +903,8 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig
                        command = "verilog";
                else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il")
                        command = "ilang";
+               else if (filename.size() > 4 && filename.substr(filename.size()-4) == ".aig")
+                       command = "aiger";
                else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".blif")
                        command = "blif";
                else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".edif")