+2014-08-22 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ PR target/62195
+ * doc/md.texi (Machine Constraints): Update PowerPC wi constraint
+ documentation to state it is only for VSX operations.
+
+ * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Make wi
+ constraint only active if VSX.
+
+ * config/rs6000/rs6000.md (lfiwax): Use wj constraint instead of
+ wi cosntraint for ISA 2.07 lxsiwax/lxsiwzx instructions.
+ (lfiwzx): Likewise.
+
2014-08-22 David Malcolm <dmalcolm@redhat.com>
* fwprop.c (single_def_use_dom_walker::before_dom_children):
;; At present, DImode is not allowed in the Altivec registers. If in the
;; future it is allowed, wi/wj can be set to VSX_REGS instead of FLOAT_REGS.
(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]"
- "FP or VSX register to hold 64-bit integers or NO_REGS.")
+ "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.")
(define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]"
"FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.")
wf - Preferred register class for V4SFmode.
wg - Float register for power6x move insns.
wh - FP register for direct move instructions.
- wi - FP or VSX register to hold 64-bit integers.
+ wi - FP or VSX register to hold 64-bit integers for VSX insns.
wj - FP or VSX register to hold 64-bit integers for direct moves.
wk - FP or VSX register to hold 64-bit doubles for direct moves.
wl - Float register if we can do 32-bit signed int loads.
rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
- {
- rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
- rs6000_constraints[RS6000_CONSTRAINT_wi] = FLOAT_REGS; /* DImode */
- }
+ rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
if (TARGET_VSX)
{
rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
+ rs6000_constraints[RS6000_CONSTRAINT_wi] = FLOAT_REGS; /* DImode */
if (TARGET_VSX_TIMODE)
rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
; We don't define lfiwax/lfiwzx with the normal definition, because we
; don't want to support putting SImode in FPR registers.
(define_insn "lfiwax"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,!wj")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
UNSPEC_LFIWAX))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
(set_attr "type" "fpload")])
(define_insn "lfiwzx"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,!wj")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
UNSPEC_LFIWZX))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
Floating point register if direct moves are available, or NO_REGS.
@item wi
-FP or VSX register to hold 64-bit integers or NO_REGS.
+FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
@item wj
FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.