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tools/litex_sim: use default integrated_rom_size
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 13 Jan 2020 16:39:23 +0000 (17:39 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 13 Jan 2020 16:39:23 +0000 (17:39 +0100)
litex/tools/litex_sim.py patch | blob | history

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 99a0e1694c37b9bc5eb460f467c037c80e224790..ecf3edf6304558e122e8da493bbc943f663d28b9 100755 (executable)
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -107,7 +107,6 @@ class SimSoC(SoCSDRAM):
 
         # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-            integrated_rom_size = 0x8000,
             ident               = "LiteX Simulation", ident_version=True,
             with_uart           = False,
             **kwargs)