arch: Eliminate the unused HasUnalignedMemAcc constant.

Change-Id: Iaf9346df57336216c09979fe1d931701c6b7ddf6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32923
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index 0ce38bcc9d69a201bf2bb5ef42ab2a0c0c74226d..2f8b634dfdeef1dc892fc1789f3d3c2488d2c116 100644 (file)
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -92,9 +92,6 @@ namespace ArmISA
 
     const uint32_t HighVecs = 0xFFFF0000;
 
-    // Memory accesses cannot be unaligned
-    const bool HasUnalignedMemAcc = true;
-
     enum InterruptTypes
     {
         INT_RST,

diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index 9b44d8649216ca93d3f08bc1129ae88e90eddf0a..b97828fef68fd1c8c5e8bf1bfe1aa3a71c1a5a68 100644 (file)
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -136,8 +136,6 @@ enum mode_type
 const int ANNOTE_NONE = 0;
 const uint32_t ITOUCH_ANNOTE = 0xffffffff;
 
-const bool HasUnalignedMemAcc = true;
-
 } // namespace MipsISA
 
 #endif // __ARCH_MIPS_ISA_TRAITS_HH__

diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index 89bfa6bb5abe1c01f388e3f26a2aaa830baa82a6..0c82af2e0f691abbfc4e5630370e53aab0233400 100644 (file)
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -54,9 +54,6 @@ const Addr PteMask = NPtePage - 1;
 
 const int MachineBytes = 4;
 
-// Memory accesses can be unaligned
-const bool HasUnalignedMemAcc = true;
-
 } // namespace PowerISA
 
 #endif // __ARCH_POWER_ISA_TRAITS_HH__

diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index 8ba2e0cdc07a6adde195120bd4a1ff9c211b59e3..a228a90718404627abb4379313826a31d7f20267 100644 (file)
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -54,9 +54,6 @@ const ByteOrder GuestByteOrder = LittleEndianByteOrder;
 const Addr PageShift = 12;
 const Addr PageBytes = ULL(1) << PageShift;
 
-// Memory accesses can be unaligned (at least for double-word memory accesses)
-const bool HasUnalignedMemAcc = true;
-
 }
 
 #endif //__ARCH_RISCV_ISA_TRAITS_HH__

diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 79891076262fcd0749785b0dbcbd7401130a5ec0..ad9cf0881d085eceb3f8fe489ec5acf9bd10b873 100644 (file)
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -44,9 +44,6 @@ const Addr PageBytes = ULL(1) << PageShift;
 
 StaticInstPtr decodeInst(ExtMachInst);
 
-// Memory accesses cannot be unaligned
-const bool HasUnalignedMemAcc = false;
-
 }
 
 #endif // __ARCH_SPARC_ISA_TRAITS_HH__

diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 98a2dc843ddf3cfe63db26e7d1e4d82b0cf2af2c..1f7a590b87867cfa6a7dcaa029aa153ce6dfceb7 100644 (file)
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -49,9 +49,6 @@ namespace X86ISA
 
     const Addr PageShift = 12;
     const Addr PageBytes = ULL(1) << PageShift;
-
-    // Memory accesses can be unaligned
-    const bool HasUnalignedMemAcc = true;
 }
 
 #endif // __ARCH_X86_ISATRAITS_HH__