fprintf(stderr, "r300: Warning: Unknown chipset 0x%x\n",
caps->pci_id);
}
+
+ caps->is_rv350 = caps->family >= CHIP_FAMILY_RV350;
}
unsigned num_tex_units;
/* Whether or not TCL is physically present */
boolean has_tcl;
- /* Whether or not this is R400. The differences compared to their R3xx
+ /* Whether or not this is RV350 or newer, including all r400 and r500
+ * chipsets. The differences compared to the oldest r300 chips are:
+ * - Blend LTE/GTE thresholds
+ * - Better MACRO_SWITCH in texture tiling
+ * - Half float vertex
+ * - More HyperZ optimizations */
+ boolean is_rv350;
+ /* Whether or not this is R400. The differences compared their rv350
* cousins are:
* - Extended fragment shader registers
- * - Blend LTE/GTE thresholds */
+ * - 3DC texture compression (RGTC2) */
boolean is_r400;
/* Whether or not this is an RV515 or newer; R500s have many differences
- * that require extra consideration, compared to their R3xx cousins:
+ * that require extra consideration, compared to their rv350 cousins:
* - Extra bit of width and height on texture sizes
* - Blend color is split across two registers
- * - Blend LTE/GTE thresholds
* - Universal Shader (US) block used for fragment shaders
- * - FP16 blending and multisampling */
+ * - FP16 blending and multisampling
+ * - Full RGTC texture compression
+ * - 24-bit depth textures
+ * - Stencil back-face reference value
+ * - Ability to render up to 2^24 - 1 vertices with signed index offset */
boolean is_r500;
/* Whether or not the second pixel pipe is accessed with the high bit */
boolean high_second_pipe;
void r300_emit_invariant_state(struct r300_context* r300,
unsigned size, void* state)
{
- struct r300_capabilities* caps = &r300_screen(r300->context.screen)->caps;
CS_LOCALS(r300);
- BEGIN_CS(12 + (caps->has_tcl ? 2: 0));
+ BEGIN_CS(12 + (r300->screen->caps.has_tcl ? 2 : 0));
/*** Graphics Backend (GB) ***/
/* Subpixel multisampling for AA
/* Sign/normalize control */
OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
/* TCL-only stuff */
- if (caps->has_tcl) {
+ if (r300->screen->caps.has_tcl) {
/* Amount of time to wait for vertex fetches in PVS */
OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
}
END_CS;
/* XXX unsorted stuff from surface_fill */
- BEGIN_CS(38 + (caps->has_tcl ? 7 : 0) +
- (caps->family >= CHIP_FAMILY_RV350 ? 4 : 0));
+ BEGIN_CS(38 + (r300->screen->caps.has_tcl ? 7 : 0) +
+ (r300->screen->caps.is_rv350 ? 4 : 0));
- if (caps->has_tcl) {
+ if (r300->screen->caps.has_tcl) {
/*Flushing PVS is required before the VAP_GB registers can be changed*/
OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525);
OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000);
- if (caps->family >= CHIP_FAMILY_RV350) {
+ if (r300->screen->caps.is_rv350) {
OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x01010101);
OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFEFEFEFE);
}
{
struct pipe_resource* base = &tex->b.b;
unsigned stride, size, layer_size, nblocksy, i;
- boolean rv350_mode = screen->caps.family >= CHIP_FAMILY_RV350;
+ boolean rv350_mode = screen->caps.is_rv350;
SCREEN_DBG(screen, DBG_TEX, "r300: Making miptree for texture, format %s\n",
util_format_name(base->format));
{
struct r300_winsys_screen *rws = (struct r300_winsys_screen *)screen->winsys;
enum pipe_format format = tex->b.b.format;
- boolean rv350_mode = r300_screen(screen)->caps.family >= CHIP_FAMILY_RV350;
+ boolean rv350_mode = r300_screen(screen)->caps.is_rv350;
boolean is_zb = util_format_is_depth_or_stencil(format);
boolean dbg_no_tiling = SCREEN_DBG_ON(r300_screen(screen), DBG_NO_TILING);