If d_bit already in sigbit_chain_next, create extra wire

diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index 21dfe96198c43a252575bb6483c2fd062b241328..46f6a79fb47a7a7cb1276b280cd559ae81cf3680 100644 (file)
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -293,10 +293,13 @@ struct ShregmapWorker
 
                                if (opts.init || sigbit_init.count(q_bit) == 0)
                                {
-                                       if (sigbit_chain_next.count(d_bit)) {
+                                       auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell));
+                                       if (!r.second) {
                                                sigbit_with_non_chain_users.insert(d_bit);
-                                       } else
-                                               sigbit_chain_next[d_bit] = cell;
+                                               Wire *wire = module->addWire(NEW_ID);
+                                               module->connect(wire, d_bit);
+                                               sigbit_chain_next.insert(std::make_pair(wire, cell));
+                                       }
 
                                        sigbit_chain_prev[q_bit] = cell;
                                        continue;