X86 Regressions: Update stats due to introduction of TSO
authorNilay Vaish <nilay@cs.wisc.edu>
Sun, 29 Jan 2012 01:09:17 +0000 (19:09 -0600)
committerNilay Vaish <nilay@cs.wisc.edu>
Sun, 29 Jan 2012 01:09:17 +0000 (19:09 -0600)
19 files changed:
tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
tests/long/00.gzip/ref/x86/linux/o3-timing/simout
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
tests/long/10.mcf/ref/x86/linux/o3-timing/simout
tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
tests/long/20.parser/ref/x86/linux/o3-timing/simout
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
tests/long/70.twolf/ref/x86/linux/o3-timing/simout
tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
tests/quick/00.hello/ref/x86/linux/o3-timing/simout
tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt

index 42f7aa66f120da8d79100969d5e099751b7e11fd..6e971ebcf616430a537575d8dd37e93b266ef280 100644 (file)
@@ -80,6 +80,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=true
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -502,7 +503,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
index 48ae315a042aba9748a54228fbd8679c9c4575f9..bff73f5f1a22fc13c311d52f757f83556233e4ae 100755 (executable)
+Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:28:24
-gem5 executing on zizzer
+gem5 compiled Jan 28 2012 12:11:40
+gem5 started Jan 28 2012 12:12:43
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
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 Loading Input Data
 Duplicating 262144 bytes
 Duplicating 524288 bytes
@@ -1039,9 +17,11 @@ Input data 1048576 bytes in length
 Compressing Input Data, level 1
 Compressed data 108074 bytes in length
 Uncompressing Data
+info: Increasing stack size by one page.
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Compressing Input Data, level 3
+info: Increasing stack size by one page.
 Compressed data 97831 bytes in length
 Uncompressing Data
 Uncompressed data 1048576 bytes in length
@@ -1062,4 +42,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 586294224000 because target called exit()
+Exiting @ tick 588785308000 because target called exit()
index 802bd6f5d6c32c41d4a25ba688387e1f20ca7ccd..f7c59f027203237473ac0893433c3a8aaeb1f4c5 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.586294                       # Number of seconds simulated
-sim_ticks                                586294224000                       # Number of ticks simulated
-final_tick                               586294224000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.588785                       # Number of seconds simulated
+sim_ticks                                588785308000                       # Number of ticks simulated
+final_tick                               588785308000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 145094                       # Simulator instruction rate (inst/s)
-host_tick_rate                               52462700                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215548                       # Number of bytes of host memory used
-host_seconds                                 11175.48                       # Real time elapsed on the host
+host_inst_rate                                 112730                       # Simulator instruction rate (inst/s)
+host_tick_rate                               40933847                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 244824                       # Number of bytes of host memory used
+host_seconds                                 14383.83                       # Real time elapsed on the host
 sim_insts                                  1621493982                       # Number of instructions simulated
-system.physmem.bytes_read                     5880640                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  56960                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                  3744192                       # Number of bytes written to this memory
-system.physmem.num_reads                        91885                       # Number of read requests responded to by this memory
-system.physmem.num_writes                       58503                       # Number of write requests responded to by this memory
+system.physmem.bytes_read                     5878272                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  57216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  3742528                       # Number of bytes written to this memory
+system.physmem.num_reads                        91848                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       58477                       # Number of write requests responded to by this memory
 system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       10030186                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                     97153                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       6386200                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      16416386                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read                        9983727                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                     97176                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       6356354                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      16340082                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   48                       # Number of system calls
-system.cpu.numCycles                       1172588449                       # number of cpu cycles simulated
+system.cpu.numCycles                       1177570617                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                142448982                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          142448982                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            7804844                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             134509888                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                133615988                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                141882222                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          141882222                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            7459322                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             135523268                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                134664780                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          143149229                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1143761054                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   142448982                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          133615988                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     330199440                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                57554993                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              649541012                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   52                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           331                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 137027209                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                996742                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1172439660                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.784546                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.109877                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          141519405                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1135188232                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   141882222                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          134664780                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     328423216                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                56273795                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              658902879                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   48                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           302                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 135738609                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                998788                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1177479353                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.766783                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.096310                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                845244296     72.09%     72.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 17110181      1.46%     73.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 18043141      1.54%     75.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 16408368      1.40%     76.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 23340182      1.99%     78.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 16629602      1.42%     79.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 21855680      1.86%     81.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 28257046      2.41%     84.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                185551164     15.83%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                852058955     72.36%     72.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 15948065      1.35%     73.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 17931063      1.52%     75.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 17495755      1.49%     76.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 23352779      1.98%     78.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 16626553      1.41%     80.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 22402886      1.90%     82.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 28214099      2.40%     84.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                183449198     15.58%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1172439660                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.121483                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.975416                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                240695556                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             558473143                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 228947071                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              94774294                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               49549596                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2070409567                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               49549596                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                290323713                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               132525789                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           3175                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 256725592                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             443311795                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2043122328                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  2634                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents              278313629                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents             129499394                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2031527322                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            4954653611                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       4954649391                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              4220                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1177479353                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.120487                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.964009                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                241266448                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             565597424                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 225300633                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              96681345                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               48633503                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2058834896                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               48633503                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                289994325                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               136667782                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           3607                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 255841310                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             446338826                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2031094400                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   199                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              278357951                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             133112570                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2019296537                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            4928551600                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       4928548640                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              2960                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1617994650                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                413532672                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 91                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             91                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 793190427                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            519090632                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           226808407                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         354951645                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        148937436                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1986583516                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 218                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1781630004                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            180825                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       364939190                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    670712329                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            168                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1172439660                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.519592                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.333662                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                401301887                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 93                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             93                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 797995614                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            517349896                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           226176362                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         355062669                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        148977960                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1979799927                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 215                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1779311117                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            175082                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       358154503                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    654941515                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            165                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1177479353                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.511119                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.319645                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           271921709     23.19%     23.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           416937499     35.56%     58.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           234725234     20.02%     78.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           156776493     13.37%     92.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            54385701      4.64%     96.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            21203892      1.81%     98.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            14378982      1.23%     99.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1804798      0.15%     99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              305352      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           271443176     23.05%     23.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           420511572     35.71%     58.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           239784716     20.36%     79.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           159545639     13.55%     92.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            48751983      4.14%     96.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            21481111      1.82%     98.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            13897994      1.18%     99.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1713551      0.15%     99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              349611      0.03%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1172439660                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1177479353                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  179772      6.92%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2269895     87.35%     94.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                148998      5.73%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  183781      6.86%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2344413     87.49%     94.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                151333      5.65%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass          26894248      1.51%      1.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1102052869     61.86%     63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass          26390474      1.48%      1.48% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1101178190     61.89%     63.37% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     63.37% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     63.37% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     63.37% # Type of FU issued
@@ -178,85 +178,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     63.37% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     63.37% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     63.37% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            457985397     25.71%     89.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           194697490     10.93%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            457060255     25.69%     89.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           194682198     10.94%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1781630004                       # Type of FU issued
-system.cpu.iq.rate                           1.519399                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2598665                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.001459                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4738479063                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2351732069                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1760053765                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                  95                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                542                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total             1779311117                       # Type of FU issued
+system.cpu.iq.rate                           1.511002                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2679527                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.001506                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4738956161                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2338163322                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1758678242                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                  35                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                458                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           12                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1757334381                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                      40                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        205665909                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses             1755600151                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      19                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        207757708                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    100048507                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        60622                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       216417                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     38622350                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     98307771                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        75876                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       215687                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     37990305                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads          849                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         34395                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         1126                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               49549596                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1308890                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                133908                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1986583734                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            659432                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             519090632                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            226808407                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 86                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  64911                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    28                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         216417                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        4603219                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3388875                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              7992094                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1768232808                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             452047218                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          13397196                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               48633503                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1923683                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                157688                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1979800142                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            665872                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             517349896                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            226176362                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 85                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  70768                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    44                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         215687                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4604749                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3040457                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              7645206                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1766024784                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             451208749                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          13286333                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    645919458                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                112169596                       # Number of branches executed
-system.cpu.iew.exec_stores                  193872240                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.507974                       # Inst execution rate
-system.cpu.iew.wb_sent                     1766226829                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1760053777                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1336567337                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2003494286                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    645051015                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                112022135                       # Number of branches executed
+system.cpu.iew.exec_stores                  193842266                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.499719                       # Inst execution rate
+system.cpu.iew.wb_sent                     1764443624                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1758678254                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1332033031                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1982428848                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.500999                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.667118                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.493480                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.671920                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts     1621493982                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       365103312                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       358308768                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              50                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           7804888                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1122890064                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.444036                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.662985                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           7459361                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1128845850                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.436418                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.651874                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    346724877     30.88%     30.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    438665808     39.07%     69.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     94902960      8.45%     78.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3    133728922     11.91%     90.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     36854784      3.28%     93.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     26115374      2.33%     95.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     22565758      2.01%     97.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      8207714      0.73%     98.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     15123867      1.35%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    347283519     30.76%     30.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    441725058     39.13%     69.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     99623372      8.83%     78.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3    136537223     12.10%     90.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     31770740      2.81%     93.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     26056867      2.31%     95.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     22501724      1.99%     97.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      8245904      0.73%     98.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     15101443      1.34%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1122890064                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1128845850                       # Number of insts commited each cycle
 system.cpu.commit.count                    1621493982                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      607228182                       # Number of memory references committed
@@ -266,48 +266,48 @@ system.cpu.commit.branches                  107161579                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1621354492                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              15123867                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              15101443                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3094363491                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4022764791                       # The number of ROB writes
-system.cpu.timesIdled                           43542                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          148789                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3093547157                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4008258633                       # The number of ROB writes
+system.cpu.timesIdled                           21053                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           91264                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1621493982                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1621493982                       # Number of Instructions Simulated
-system.cpu.cpi                               0.723153                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.723153                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.382833                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.382833                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3273039620                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1756091292                       # number of integer regfile writes
+system.cpu.cpi                               0.726226                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.726226                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.376982                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.376982                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3270153545                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1754693299                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        12                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               908871445                       # number of misc regfile reads
+system.cpu.misc_regfile_reads               907833056                       # number of misc regfile reads
 system.cpu.icache.replacements                     12                       # number of replacements
-system.cpu.icache.tagsinuse                810.394392                       # Cycle average of tags in use
-system.cpu.icache.total_refs                137025977                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    893                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               153444.543113                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                808.459907                       # Cycle average of tags in use
+system.cpu.icache.total_refs                135737385                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    897                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               151323.729097                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            810.394392                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.395700                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              137025977                       # number of ReadReq hits
-system.cpu.icache.demand_hits               137025977                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              137025977                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1232                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1232                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1232                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       43328500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        43328500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       43328500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          137027209                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           137027209                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          137027209                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0            808.459907                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.394756                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              135737385                       # number of ReadReq hits
+system.cpu.icache.demand_hits               135737385                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              135737385                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1224                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1224                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1224                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       43199000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        43199000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       43199000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          135738609                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           135738609                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          135738609                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000009                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate           0.000009                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate          0.000009                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 35169.237013                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 35169.237013                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 35169.237013                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 35293.300654                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35293.300654                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35293.300654                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -317,159 +317,159 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               339                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                339                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               339                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             893                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              893                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             893                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits               327                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                327                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               327                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses             897                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses              897                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses             897                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     31560500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     31560500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     31560500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     31683500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     31683500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     31683500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000007                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000007                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate     0.000007                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35342.105263                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35342.105263                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35342.105263                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35321.627648                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35321.627648                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35321.627648                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 459077                       # number of replacements
-system.cpu.dcache.tagsinuse               4094.907333                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                433034493                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 463173                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 934.930346                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              317767000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4094.907333                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999733                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              246142702                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             186891791                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               433034493                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              433034493                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               217277                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1294266                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               1511543                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              1511543                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     2206130500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   25062764496                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     27268894996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    27268894996                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          246359979                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                 459032                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.268658                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                431168175                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 463128                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 930.991378                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              416529000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4094.268658                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999577                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              243231636                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             187936539                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               431168175                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              431168175                       # number of overall hits
+system.cpu.dcache.ReadReq_misses               217117                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              249518                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                466635                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses               466635                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency     2193700500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    3216393000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency      5410093500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency     5410093500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          243448753                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses         188186057                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           434546036                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          434546036                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000882                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.006878                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.003478                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.003478                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 10153.539031                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 19364.461785                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 18040.436161                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 18040.436161                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      1883000                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets    482947000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               482                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           32670                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  3906.639004                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 14782.583410                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses           431634810                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          431634810                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000892                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.001326                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.001081                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.001081                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 10103.771239                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 12890.424739                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 11593.844225                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 11593.844225                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   410037                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits              3648                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1044720                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1048368                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1048368                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          213629                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         249546                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           463175                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          463175                       # number of overall MSHR misses
+system.cpu.dcache.writebacks                   409997                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits              3467                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits               38                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits               3505                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits              3505                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses          213650                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         249480                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses           463130                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses          463130                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1533480500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   2506697000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   4040177500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   4040177500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   1524751500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   2467190000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   3991941500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   3991941500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000867                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000878                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate     0.001326                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.001066                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.001066                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7178.241250                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10045.029774                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  8722.788363                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  8722.788363                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate      0.001073                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.001073                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7136.679148                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency  9889.329806                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  8619.483730                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  8619.483730                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                 73618                       # number of replacements
-system.cpu.l2cache.tagsinuse             17964.500601                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  452679                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 89237                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  5.072773                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                 73588                       # number of replacements
+system.cpu.l2cache.tagsinuse             17962.176251                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  452941                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 89203                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.077643                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1976.098849                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15988.401752                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.060306                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.487927                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                181359                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              410037                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              190824                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 372183                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                372183                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               33163                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             58722                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                91885                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               91885                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1130840000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   2017374000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     3148214000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    3148214000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            214522                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          410037                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          249546                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             464068                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            464068                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.154590                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.235315                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.197999                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.197999                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34099.448180                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34354.654133                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34262.545573                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34262.545573                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs       202000                       # number of cycles access was blocked
+system.cpu.l2cache.occ_blocks::0          1977.761332                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         15984.414919                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.060356                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.487806                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                181391                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits              409997                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits              190788                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                 372179                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                372179                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               33152                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses             58696                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                91848                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               91848                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1130561500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   2008268500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     3138830000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    3138830000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses            214543                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses          409997                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          249484                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses             464027                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses            464027                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.154524                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.235270                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.197937                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.197937                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34102.361848                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34214.742061                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34174.179078                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34174.179078                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs              122                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  1655.737705                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   58503                       # number of writebacks
+system.cpu.l2cache.writebacks                   58477                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          33163                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        58722                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           91885                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          91885                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses          33152                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        58696                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           91848                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          91848                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1028236500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1828595500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   2856832000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   2856832000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1027873500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   1819617000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   2847490500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   2847490500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.154590                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235315                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.197999                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.197999                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.533275                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31139.870917                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31091.385972                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31091.385972                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.154524                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235270                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.197937                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.197937                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.871501                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.698514                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31002.204730                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31002.204730                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index f406247a4dceb7a6993c6ea6b72ed2163a4708ee..9b8aaf5ddd92c02ec0a9a4dfefe74dec56a155dc 100644 (file)
@@ -15,7 +15,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=timing
 memories=system.physmem
@@ -122,6 +122,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=true
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -1311,7 +1312,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1331,7 +1332,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
index 873e1bea257da5deb87d17ce644f8d176b0d1843..9036859eb7cbee1b9ace62eac9793fd41e0e158d 100755 (executable)
@@ -1,13 +1,15 @@
+Redirecting stdout to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing/simout
+Redirecting stderr to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:12:17
-gem5 started Jan 23 2012 08:29:15
-gem5 executing on zizzer
+gem5 compiled Jan 28 2012 16:24:13
+gem5 started Jan 28 2012 16:29:18
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5161177988500 because m5_exit instruction encountered
+Exiting @ tick 5164643202500 because m5_exit instruction encountered
index c625269852cdb6045b2cf3251d7ca5f1046a1869..9cc68e765ef0af20e226c6796e4529cfe47e1719 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.161178                       # Number of seconds simulated
-sim_ticks                                5161177988500                       # Number of ticks simulated
-final_tick                               5161177988500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.164643                       # Number of seconds simulated
+sim_ticks                                5164643202500                       # Number of ticks simulated
+final_tick                               5164643202500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 290092                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1780684720                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 364016                       # Number of bytes of host memory used
-host_seconds                                  2898.42                       # Real time elapsed on the host
-sim_insts                                   840808469                       # Number of instructions simulated
-system.physmem.bytes_read                    16106624                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                1233856                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 12115136                       # Number of bytes written to this memory
-system.physmem.num_reads                       251666                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      189299                       # Number of write requests responded to by this memory
+host_inst_rate                                 258156                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1586008699                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 390600                       # Number of bytes of host memory used
+host_seconds                                  3256.38                       # Real time elapsed on the host
+sim_insts                                   840653382                       # Number of instructions simulated
+system.physmem.bytes_read                    15885120                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                1235904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 12075328                       # Number of bytes written to this memory
+system.physmem.num_reads                       248205                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      188677                       # Number of write requests responded to by this memory
 system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        3120726                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    239065                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       2347359                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                       5468085                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        169467                       # number of replacements
-system.l2c.tagsinuse                     38339.786444                       # Cycle average of tags in use
-system.l2c.total_refs                         3812924                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        204660                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         18.630529                       # Average number of references to valid blocks.
+system.physmem.bw_read                        3075744                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    239301                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                       2338076                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       5413820                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        166524                       # number of replacements
+system.l2c.tagsinuse                     37860.019471                       # Cycle average of tags in use
+system.l2c.total_refs                         3791499                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        201257                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         18.839091                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                 11950.408174                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 26389.378270                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.182349                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.402670                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    2335607                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     145488                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2481095                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                  1594493                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1594493                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                     327                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 327                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0                   150672                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               150672                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     2486279                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      145488                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2631767                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    2486279                       # number of overall hits
-system.l2c.overall_hits::1                     145488                       # number of overall hits
-system.l2c.overall_hits::total                2631767                       # number of overall hits
-system.l2c.ReadReq_misses::0                    66850                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                      109                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                66959                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  3932                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3932                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                 142221                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             142221                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    209071                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                       109                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                209180                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   209071                       # number of overall misses
-system.l2c.overall_misses::1                      109                       # number of overall misses
-system.l2c.overall_misses::total               209180                       # number of overall misses
-system.l2c.ReadReq_miss_latency            3511861000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency           38996000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          7442399000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency            10954260000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency           10954260000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                2402457                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 145597                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2548054                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0              1594493                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1594493                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                4259                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            4259                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               292893                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           292893                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 2695350                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  145597                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2840947                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                2695350                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 145597                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2840947                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.027826                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.000749                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.028574                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.923221                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.485573                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.077567                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.000749                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.078316                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.077567                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.000749                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.078316                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   52533.448018                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   32218908.256881                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 32271441.704899                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0  9917.599186                       # average UpgradeReq miss latency
+system.l2c.occ_blocks::0                 11072.402172                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 26787.617299                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.168951                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.408747                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0                    2329446                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                     146092                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                2475538                       # number of ReadReq hits
+system.l2c.Writeback_hits::0                  1599025                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1599025                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                     316                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 316                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::0                   151571                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               151571                       # number of ReadExReq hits
+system.l2c.demand_hits::0                     2481017                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                      146092                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2627109                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                    2481017                       # number of overall hits
+system.l2c.overall_hits::1                     146092                       # number of overall hits
+system.l2c.overall_hits::total                2627109                       # number of overall hits
+system.l2c.ReadReq_misses::0                    64214                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                      107                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                64321                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                  5085                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              5085                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::0                 141328                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             141328                       # number of ReadExReq misses
+system.l2c.demand_misses::0                    205542                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                       107                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                205649                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                   205542                       # number of overall misses
+system.l2c.overall_misses::1                      107                       # number of overall misses
+system.l2c.overall_misses::total               205649                       # number of overall misses
+system.l2c.ReadReq_miss_latency            3375006500                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency           39785500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency          7360156500                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency            10735163000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency           10735163000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::0                2393660                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                 146199                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2539859                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0              1599025                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          1599025                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0                5401                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            5401                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0               292899                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           292899                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0                 2686559                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                  146199                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2832758                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::0                2686559                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                 146199                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2832758                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0              0.026827                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.000732                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.027559                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.941492                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0            0.482514                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.076508                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.000732                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.077239                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::0              0.076508                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.000732                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.077239                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0   52558.733298                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   31542116.822430                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 31594675.555728                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0  7824.090462                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52329.817678                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 52078.544238                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    52394.928039                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    100497798.165138                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 100550193.093176                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   52394.928039                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   100497798.165138                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 100550193.093176                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::0    52228.561559                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    100328626.168224                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 100380854.729784                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0   52228.561559                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   100328626.168224                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 100380854.729784                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -111,88 +111,88 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          142631                       # number of writebacks
+system.l2c.writebacks                          142010                       # number of writebacks
 system.l2c.ReadReq_mshr_hits                        2                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits                         2                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits                        2                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                  66957                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                3932                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               142221                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  209178                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 209178                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_misses                  64319                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                5085                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses               141328                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses                  205647                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                 205647                       # number of overall MSHR misses
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency       2695362500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency     157637000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     5708607000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency        8403969500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency       8403969500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency  59978490000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency   1230737500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency  61209227500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.027870                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         0.459879                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.487749                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      0.923221                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadReq_mshr_miss_latency       2589128000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency     203766500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency     5654353000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency        8243481000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency       8243481000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency  59975261500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency   1228545000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency  61203806500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.026871                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         0.439941                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.466812                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0      0.941492                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       0.485573                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0       0.482514                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.077607                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          1.436692                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      1.514299                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.077607                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         1.436692                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     1.514299                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40255.126424                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40090.793489                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40138.987913                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40176.163363                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40176.163363                       # average overall mshr miss latency
+system.l2c.demand_mshr_miss_rate::0          0.076547                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          1.406624                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      1.483170                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0         0.076547                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         1.406624                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     1.483170                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 40254.481568                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40072.074730                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40008.724386                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency  40085.588411                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40085.588411                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.replacements                     47573                       # number of replacements
-system.iocache.tagsinuse                     0.195398                       # Cycle average of tags in use
+system.iocache.replacements                     47574                       # number of replacements
+system.iocache.tagsinuse                     0.187855                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     47589                       # Sample count of references to valid blocks.
+system.iocache.sampled_refs                     47590                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              4994542788000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1                 0.195398                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.012212                       # Average percentage of cache occupancy
+system.iocache.warmup_cycle              4996389374000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::1                 0.187855                       # Average occupied blocks per context
+system.iocache.occ_percent::1                0.011741                       # Average percentage of cache occupancy
 system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
 system.iocache.overall_hits::0                      0                       # number of overall hits
 system.iocache.overall_hits::1                      0                       # number of overall hits
 system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.ReadReq_misses::1                  907                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              907                       # number of ReadReq misses
+system.iocache.ReadReq_misses::1                  909                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              909                       # number of ReadReq misses
 system.iocache.WriteReq_misses::1               46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
 system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 47627                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47627                       # number of demand (read+write) misses
+system.iocache.demand_misses::1                 47629                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47629                       # number of demand (read+write) misses
 system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                47627                       # number of overall misses
-system.iocache.overall_misses::total            47627                       # number of overall misses
-system.iocache.ReadReq_miss_latency         113669932                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency       6372391160                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency         6486061092                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency        6486061092                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::1                907                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            907                       # number of ReadReq accesses(hits+misses)
+system.iocache.overall_misses::1                47629                       # number of overall misses
+system.iocache.overall_misses::total            47629                       # number of overall misses
+system.iocache.ReadReq_miss_latency         113959932                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency       6369072160                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency         6483032092                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency        6483032092                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::1                909                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            909                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::1             46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               47627                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47627                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::1               47629                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47629                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              47627                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47627                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::1              47629                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47629                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
@@ -202,37 +202,37 @@ system.iocache.overall_miss_rate::0          no_value                       # mi
 system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 125325.173098                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 125368.462046                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 136395.358733                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 136324.318493                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
 system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 136184.540114                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 136115.225850                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 136184.540114                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 136115.225850                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs      68679532                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs      68773500                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                11251                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                11260                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  6104.304684                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6107.770870                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                       46668                       # number of writebacks
+system.iocache.writebacks                       46667                       # number of writebacks
 system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
 system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.ReadReq_mshr_misses                907                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses                909                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses             46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses               47627                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses              47627                       # number of overall MSHR misses
+system.iocache.demand_mshr_misses               47629                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses              47629                       # number of overall MSHR misses
 system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.ReadReq_mshr_miss_latency     66482982                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency   3942637876                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency    4009120858                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency   4009120858                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency     66668982                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3939322842                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    4005991824                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   4005991824                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
@@ -246,10 +246,10 @@ system.iocache.demand_mshr_miss_rate::total          inf                       #
 system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency 73299.869901                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 84388.653168                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency 84177.480379                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency 84177.480379                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency 73343.214521                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 84317.697817                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 84108.249680                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 84108.249680                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
@@ -266,416 +266,415 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu.numCycles                        449878562                       # number of cpu cycles simulated
+system.cpu.numCycles                        462648122                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 91189820                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           91189820                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1250253                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              90006318                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 83822675                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 91002231                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           91002231                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1246819                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              89740071                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 83586488                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           28390554                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      451032028                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    91189820                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           83822675                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     171638033                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6092005                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     127923                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               86885537                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                36685                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         38090                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          283                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9866979                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                541048                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    3553                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          291873782                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.039474                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.398963                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           29047716                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      449719579                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    91002231                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           83586488                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     171232175                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 5868826                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     136581                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles              101975708                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                37095                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         37068                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles          258                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9677008                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                518282                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    3472                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          307050159                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.882718                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.377693                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                120818032     41.39%     41.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1855546      0.64%     42.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72826244     24.95%     66.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1422491      0.49%     67.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1829890      0.63%     68.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4020066      1.38%     69.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1590838      0.55%     70.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1683069      0.58%     70.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 85827606     29.41%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                136328655     44.40%     44.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1837704      0.60%     45.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72797609     23.71%     68.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1414382      0.46%     69.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1803500      0.59%     69.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  3975077      1.29%     71.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1554877      0.51%     71.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1662423      0.54%     72.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 85675932     27.90%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            291873782                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.202699                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.002564                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 33589176                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              83124342                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 166020087                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               4383500                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4756677                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              883216023                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   571                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4756677                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 37852860                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                55892656                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles        9911063                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 165583689                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              17876837                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              878703692                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 12652                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               12602978                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               2126989                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents               10                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           880098416                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1724229495                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1724229039                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               456                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             843418783                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 36679626                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             488930                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         489908                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  44000804                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             19727758                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10753359                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1338256                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1089668                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  870922009                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1727938                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 867227375                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            177419                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        30993538                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     45221667                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         207753                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     291873782                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.971241                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.381572                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            307050159                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.196699                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.972055                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 34173588                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              98204152                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 165547565                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               4541296                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4583558                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              881331819                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   622                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4583558                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 38558977                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                67835236                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       11414000                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 165163218                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              19495170                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              877018517                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 10722                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               12485969                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               3867736                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           878675009                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1719931818                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1719931354                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               464                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             843258778                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 35416224                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             488329                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         492601                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  46069220                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             19448734                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10510676                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1191191                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           913743                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  869530177                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1725186                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 866447166                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            122007                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        29731249                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     42741048                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         205599                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     307050159                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.821842                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.403845                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            86148709     29.52%     29.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            24105973      8.26%     37.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            13574297      4.65%     42.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             9676822      3.32%     45.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            79595279     27.27%     73.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             5022101      1.72%     74.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72958833     25.00%     99.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              636421      0.22%     99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              155347      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           100227598     32.64%     32.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            25342786      8.25%     40.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            13946244      4.54%     45.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             9645579      3.14%     48.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            79515480     25.90%     74.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4843126      1.58%     76.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72836741     23.72%     99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              563681      0.18%     99.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              128924      0.04%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       291873782                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       307050159                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  202428      8.97%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1851752     82.02%     90.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                203495      9.01%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  189288      8.89%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1772779     83.25%     92.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                167484      7.86%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            306567      0.04%      0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             831752185     95.91%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             25621043      2.95%     98.90% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9547580      1.10%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            305473      0.04%      0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             831218521     95.93%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     95.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             25430215      2.93%     98.90% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9492957      1.10%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              867227375                       # Type of FU issued
-system.cpu.iq.rate                           1.927692                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2257675                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.002603                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2028918942                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         903653765                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    856397776                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 194                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                210                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           50                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              869178395                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                      88                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1343949                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              866447166                       # Type of FU issued
+system.cpu.iq.rate                           1.872799                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2129551                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.002458                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2042346945                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         900997029                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    855808882                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 195                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                212                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           51                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              868271157                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      87                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1634079                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4393917                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        17180                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        11337                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2321478                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4122999                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        16974                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        11449                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2081373                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      7817249                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        160526                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      7821312                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          4401                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4756677                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                34884624                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               6122535                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           872649947                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            301193                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              19727758                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10753386                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             894363                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                5389997                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 26295                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          11337                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         906001                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       524480                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1430481                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             865094857                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25131798                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2132517                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                4583558                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                45537576                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               6145383                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           871255363                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            286386                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              19448734                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10510706                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             890989                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                5371019                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 12371                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          11449                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         894854                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       527277                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1422131                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             864388820                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              24990007                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2058345                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     34436194                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 86723634                       # Number of branches executed
-system.cpu.iew.exec_stores                    9304396                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.922952                       # Inst execution rate
-system.cpu.iew.wb_sent                      864455877                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     856397826                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 671292665                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1171999804                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     34246643                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 86674452                       # Number of branches executed
+system.cpu.iew.exec_stores                    9256636                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.868350                       # Inst execution rate
+system.cpu.iew.wb_sent                      863858871                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     855808933                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 670117555                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1169388275                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.903620                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.572775                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.849805                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.573050                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      840808469                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        31735206                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1520183                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1254406                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    287133088                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.928288                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.869814                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts      840653382                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        30493739                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1519585                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           1250852                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    302482532                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.779180                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.862928                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    107529680     37.45%     37.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     13316862      4.64%     42.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3946452      1.37%     43.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     76651474     26.70%     70.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4051645      1.41%     71.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1852261      0.65%     72.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1054561      0.37%     72.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     71992194     25.07%     97.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6737959      2.35%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    121705322     40.24%     40.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     14450311      4.78%     45.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4296632      1.42%     46.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     76653351     25.34%     71.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3954227      1.31%     73.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1803566      0.60%     73.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1076627      0.36%     74.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     71984714     23.80%     97.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6557782      2.17%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    287133088                       # Number of insts commited each cycle
-system.cpu.commit.count                     840808469                       # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total    302482532                       # Number of insts commited each cycle
+system.cpu.commit.count                     840653382                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       23765746                       # Number of memory references committed
-system.cpu.commit.loads                      15333838                       # Number of loads committed
-system.cpu.commit.membars                      781579                       # Number of memory barriers committed
-system.cpu.commit.branches                   85539454                       # Number of branches committed
+system.cpu.commit.refs                       23755065                       # Number of memory references committed
+system.cpu.commit.loads                      15325732                       # Number of loads committed
+system.cpu.commit.membars                      781571                       # Number of memory barriers committed
+system.cpu.commit.branches                   85522464                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 768627958                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 768481836                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               6737959                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               6557782                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1152856114                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1749856645                       # The number of ROB writes
-system.cpu.timesIdled                         3066243                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       158004780                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9872474852                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   840808469                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             840808469                       # Number of Instructions Simulated
-system.cpu.cpi                               0.535055                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.535055                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.868968                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.868968                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1407444841                       # number of integer regfile reads
-system.cpu.int_regfile_writes               857665866                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        50                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               282350765                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 410137                       # number of misc regfile writes
-system.cpu.icache.replacements                1031767                       # number of replacements
-system.cpu.icache.tagsinuse                510.488308                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  8766017                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                1032279                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   8.491907                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            54591118000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            510.488308                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.997047                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0             8766017                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8766017                       # number of ReadReq hits
-system.cpu.icache.demand_hits::0              8766017                       # number of demand (read+write) hits
+system.cpu.rob.rob_reads                   1166989570                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1746890100                       # The number of ROB writes
+system.cpu.timesIdled                         2859611                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       155597963                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9866635724                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   840653382                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             840653382                       # Number of Instructions Simulated
+system.cpu.cpi                               0.550343                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.550343                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.817047                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.817047                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1406419580                       # number of integer regfile reads
+system.cpu.int_regfile_writes               857121538                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        51                       # number of floating regfile reads
+system.cpu.misc_regfile_reads               282006262                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 409317                       # number of misc regfile writes
+system.cpu.icache.replacements                1024030                       # number of replacements
+system.cpu.icache.tagsinuse                510.509684                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  8586920                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                1024542                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   8.381228                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            56648663000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0            510.509684                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.997089                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::0             8586920                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8586920                       # number of ReadReq hits
+system.cpu.icache.demand_hits::0              8586920                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8766017                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0             8766017                       # number of overall hits
+system.cpu.icache.demand_hits::total          8586920                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::0             8586920                       # number of overall hits
 system.cpu.icache.overall_hits::1                   0                       # number of overall hits
-system.cpu.icache.overall_hits::total         8766017                       # number of overall hits
-system.cpu.icache.ReadReq_misses::0           1100959                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1100959                       # number of ReadReq misses
-system.cpu.icache.demand_misses::0            1100959                       # number of demand (read+write) misses
+system.cpu.icache.overall_hits::total         8586920                       # number of overall hits
+system.cpu.icache.ReadReq_misses::0           1090085                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1090085                       # number of ReadReq misses
+system.cpu.icache.demand_misses::0            1090085                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1100959                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0           1100959                       # number of overall misses
+system.cpu.icache.demand_misses::total        1090085                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::0           1090085                       # number of overall misses
 system.cpu.icache.overall_misses::1                 0                       # number of overall misses
-system.cpu.icache.overall_misses::total       1100959                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency    16475831488                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency     16475831488                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency    16475831488                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0         9866976                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9866976                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0          9866976                       # number of demand (read+write) accesses
+system.cpu.icache.overall_misses::total       1090085                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency    16354144492                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency     16354144492                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency    16354144492                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::0         9677005                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9677005                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::0          9677005                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9866976                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0         9866976                       # number of overall (read+write) accesses
+system.cpu.icache.demand_accesses::total      9677005                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::0         9677005                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9866976                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0       0.111580                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0        0.111580                       # miss rate for demand accesses
+system.cpu.icache.overall_accesses::total      9677005                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::0       0.112647                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::0        0.112647                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0       0.111580                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::0       0.112647                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 14964.981882                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::0 15002.632356                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 14964.981882                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::0 15002.632356                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 14964.981882                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::0 15002.632356                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      2787490                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs      2751493                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               276                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               271                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 10099.601449                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 10153.110701                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                     1565                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits             66134                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits              66134                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits             66134                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses         1034825                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses          1034825                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses         1034825                       # number of overall MSHR misses
+system.cpu.icache.writebacks                     1551                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits             61895                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits              61895                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits             61895                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses         1028190                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses          1028190                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses         1028190                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency  12496503490                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency  12496503490                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency  12496503490                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency  12436535493                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency  12436535493                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency  12436535493                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.104878                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::0     0.106251                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0     0.104878                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::0     0.106251                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0     0.104878                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::0     0.106251                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12075.958244                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12075.958244                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12075.958244                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 12095.561611                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 12095.561611                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 12095.561611                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements         8819                       # number of replacements
-system.cpu.itb_walker_cache.tagsinuse        6.022437                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs          26537                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs         8831                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs         3.004982                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5118899189000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::1     6.022437                       # Average occupied blocks per context
-system.cpu.itb_walker_cache.occ_percent::1     0.376402                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::1        26634                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        26634                       # number of ReadReq hits
+system.cpu.itb_walker_cache.replacements         9946                       # number of replacements
+system.cpu.itb_walker_cache.tagsinuse        6.010746                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.total_refs          24573                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.sampled_refs         9958                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.avg_refs         2.467664                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.warmup_cycle 5129655075000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.occ_blocks::1     6.010746                       # Average occupied blocks per context
+system.cpu.itb_walker_cache.occ_percent::1     0.375672                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.ReadReq_hits::1        24609                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        24609                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::1            3                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            3                       # number of WriteReq hits
 system.cpu.itb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::1        26637                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        26637                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::1        24612                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        24612                       # number of demand (read+write) hits
 system.cpu.itb_walker_cache.overall_hits::0            0                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::1        26637                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        26637                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::1         9699                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         9699                       # number of ReadReq misses
+system.cpu.itb_walker_cache.overall_hits::1        24612                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        24612                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::1        10808                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total        10808                       # number of ReadReq misses
 system.cpu.itb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::1         9699                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total         9699                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::1        10808                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total        10808                       # number of demand (read+write) misses
 system.cpu.itb_walker_cache.overall_misses::0            0                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::1         9699                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total         9699                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency    124296000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency    124296000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency    124296000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::1        36333                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        36333                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.overall_misses::1        10808                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total        10808                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency    135307500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency    135307500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency    135307500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::1        35417                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        35417                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::1            3                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            3                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::1        36336                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        36336                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::1        35420                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        35420                       # number of demand (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::1        36336                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        36336                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::1     0.266947                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.overall_accesses::1        35420                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        35420                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::1     0.305164                       # miss rate for ReadReq accesses
 system.cpu.itb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::1     0.266925                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::1     0.305138                       # miss rate for demand accesses
 system.cpu.itb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
 system.cpu.itb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::1     0.266925                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::1     0.305138                       # miss rate for overall accesses
 system.cpu.itb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12815.341788                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12519.198742                       # average ReadReq miss latency
 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.cpu.itb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12815.341788                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12519.198742                       # average overall miss latency
 system.cpu.itb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu.itb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12815.341788                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12519.198742                       # average overall miss latency
 system.cpu.itb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -685,83 +684,83 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks           1368                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks           1317                       # number of writebacks
 system.cpu.itb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
 system.cpu.itb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
-system.cpu.itb_walker_cache.ReadReq_mshr_misses         9699                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses         9699                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses         9699                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses        10808                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses        10808                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses        10808                       # number of overall MSHR misses
 system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency     94849000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency     94849000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency     94849000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency    102536000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency    102536000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency    102536000                       # number of overall MSHR miss cycles
 system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1     0.266947                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1     0.305164                       # mshr miss rate for ReadReq accesses
 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.itb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::1     0.266925                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::1     0.305138                       # mshr miss rate for demand accesses
 system.cpu.itb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
 system.cpu.itb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::1     0.266925                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::1     0.305138                       # mshr miss rate for overall accesses
 system.cpu.itb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency  9779.255593                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency  9779.255593                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency  9779.255593                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency  9487.046632                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency  9487.046632                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency  9487.046632                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.itb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
 system.cpu.itb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements       145081                       # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse       13.868389                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs         150553                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs       145096                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs         1.037610                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5102657828000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::1    13.868389                       # Average occupied blocks per context
-system.cpu.dtb_walker_cache.occ_percent::1     0.866774                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::1       150554                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       150554                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.replacements       147569                       # number of replacements
+system.cpu.dtb_walker_cache.tagsinuse       13.856334                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.total_refs         141316                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.sampled_refs       147583                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.avg_refs         0.957536                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.warmup_cycle 5108660928000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.occ_blocks::1    13.856334                       # Average occupied blocks per context
+system.cpu.dtb_walker_cache.occ_percent::1     0.866021                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::1       141317                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       141317                       # number of ReadReq hits
 system.cpu.dtb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::1       150554                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       150554                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::1       141317                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       141317                       # number of demand (read+write) hits
 system.cpu.dtb_walker_cache.overall_hits::0            0                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::1       150554                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       150554                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::1       146024                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total       146024                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.overall_hits::1       141317                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       141317                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::1       148425                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total       148425                       # number of ReadReq misses
 system.cpu.dtb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::1       146024                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total       146024                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::1       148425                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total       148425                       # number of demand (read+write) misses
 system.cpu.dtb_walker_cache.overall_misses::0            0                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::1       146024                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total       146024                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency   2047200500                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency   2047200500                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency   2047200500                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::1       296578                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       296578                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.overall_misses::1       148425                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total       148425                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency   2057871000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency   2057871000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency   2057871000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::1       289742                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       289742                       # number of ReadReq accesses(hits+misses)
 system.cpu.dtb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::1       296578                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       296578                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::1       289742                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       289742                       # number of demand (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::1       296578                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       296578                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::1     0.492363                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.overall_accesses::1       289742                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       289742                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::1     0.512266                       # miss rate for ReadReq accesses
 system.cpu.dtb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::1     0.492363                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::1     0.512266                       # miss rate for demand accesses
 system.cpu.dtb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
 system.cpu.dtb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::1     0.492363                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::1     0.512266                       # miss rate for overall accesses
 system.cpu.dtb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 14019.616638                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13864.719555                       # average ReadReq miss latency
 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
 system.cpu.dtb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 14019.616638                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13864.719555                       # average overall miss latency
 system.cpu.dtb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu.dtb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 14019.616638                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13864.719555                       # average overall miss latency
 system.cpu.dtb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -771,136 +770,136 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks          42577                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks          45859                       # number of writebacks
 system.cpu.dtb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
 system.cpu.dtb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses       146024                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses       146024                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses       146024                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses       148425                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses       148425                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses       148425                       # number of overall MSHR misses
 system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency   1605163000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency   1605163000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency   1605163000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency   1608796000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency   1608796000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency   1608796000                       # number of overall MSHR miss cycles
 system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1     0.492363                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1     0.512266                       # mshr miss rate for ReadReq accesses
 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1     0.492363                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1     0.512266                       # mshr miss rate for demand accesses
 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1     0.492363                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1     0.512266                       # mshr miss rate for overall accesses
 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10992.460144                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10992.460144                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10992.460144                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10839.117399                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10839.117399                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10839.117399                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dtb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
 system.cpu.dtb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1663087                       # number of replacements
-system.cpu.dcache.tagsinuse                511.997625                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 17982371                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1663599                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  10.809318                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               13135000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            511.997625                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999995                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0            11413167                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        11413167                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0            6547162                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6547162                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::0             17960329                       # number of demand (read+write) hits
+system.cpu.dcache.replacements                1662019                       # number of replacements
+system.cpu.dcache.tagsinuse                511.997109                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 19289790                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1662531                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  11.602665                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               34336000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0            511.997109                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.999994                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::0            11184512                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        11184512                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::0            8099002                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8099002                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::0             19283514                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         17960329                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0            17960329                       # number of overall hits
+system.cpu.dcache.demand_hits::total         19283514                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::0            19283514                       # number of overall hits
 system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
-system.cpu.dcache.overall_hits::total        17960329                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::0           2492340                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2492340                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0          1875398                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1875398                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::0            4367738                       # number of demand (read+write) misses
+system.cpu.dcache.overall_hits::total        19283514                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::0           2387566                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2387566                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::0           320977                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       320977                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::0            2708543                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4367738                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0           4367738                       # number of overall misses
+system.cpu.dcache.demand_misses::total        2708543                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::0           2708543                       # number of overall misses
 system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4367738                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    37542071500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   63453033216                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency    100995104716                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency   100995104716                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0        13905507                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13905507                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0        8422560                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8422560                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0         22328067                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_misses::total       2708543                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    35727347000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   10720598495                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     46447945495                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    46447945495                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::0        13572078                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13572078                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::0        8419979                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8419979                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::0         21992057                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     22328067                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0        22328067                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21992057                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::0        21992057                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     22328067                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0       0.179234                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0      0.222664                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::0        0.195616                       # miss rate for demand accesses
+system.cpu.dcache.overall_accesses::total     21992057                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0       0.175917                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0      0.038121                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::0        0.123160                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0       0.195616                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::0       0.123160                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15062.981576                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::0 14963.920160                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 33834.435792                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::0 33399.896239                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 23122.976863                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::0 17148.683072                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 23122.976863                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0 17148.683072                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs   1083233153                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      6672000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             73547                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             391                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 14728.447836                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 17063.938619                       # average number of cycles each access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs     28980495                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              5023                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  5769.559028                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1548983                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits           1121085                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1578340                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            2699425                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           2699425                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1371255                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         297058                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1668313                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1668313                       # number of overall MSHR misses
+system.cpu.dcache.writebacks                  1550298                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits           1017351                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits            22830                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits            1040181                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits           1040181                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1370215                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         298147                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          1668362                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         1668362                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  18154950000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   9754920653                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  27909870653                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  27909870653                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency  85210888500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1394917000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency  86605805500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.098612                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency  17997979500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   9490426995                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  27488406495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  27488406495                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency  85207522500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1392017000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency  86599539500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.100958                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.035269                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.035409                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0     0.074718                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::0     0.075862                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0     0.074718                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::0     0.075862                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13239.660019                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32838.437790                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 16729.397093                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 16729.397093                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13135.149958                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31831.368402                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 16476.284221                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 16476.284221                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
index 6570dc3263627f45b9c6f0c3c72b8fb3c3f012f9..6cae7ef0f6fd4a0a78228f0acf848031e2a6e67f 100644 (file)
@@ -39,7 +39,7 @@ ACPI: Core revision 20070126
 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]\r
 ACPI: Unable to load the System Description Tables\r
 Using local APIC timer interrupts.\r
-result 7812497\r
+result 7812498\r
 Detected 7.812 MHz APIC timer.\r
 NET: Registered protocol family 16\r
 PCI: Using configuration type 1\r
index cfda7ba22a999cc6a8192cb6023499eea12378e0..c0a21768c5b960abb48bf1693c883e358dfb69fe 100644 (file)
@@ -80,6 +80,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=true
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -502,9 +503,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
index 426afea0c542f244cab3a2f6a5e7ea1345df961a..7ce56ed7fc3955110df60465ef231a6943996bcb 100755 (executable)
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:45:46
-gem5 executing on zizzer
+gem5 compiled Jan 28 2012 12:11:40
+gem5 started Jan 28 2012 12:12:43
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -23,4 +25,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 70312944500 because target called exit()
+Exiting @ tick 70097938500 because target called exit()
index f9c9708895f4d957a16ff43fcd43ae846a283028..741105f4092ba78e9555500528513155e3a93a2a 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.070313                       # Number of seconds simulated
-sim_ticks                                 70312944500                       # Number of ticks simulated
-final_tick                                70312944500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.070098                       # Number of seconds simulated
+sim_ticks                                 70097938500                       # Number of ticks simulated
+final_tick                                70097938500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 168126                       # Simulator instruction rate (inst/s)
-host_tick_rate                               42493747                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 349904                       # Number of bytes of host memory used
-host_seconds                                  1654.67                       # Real time elapsed on the host
+host_inst_rate                                 110386                       # Simulator instruction rate (inst/s)
+host_tick_rate                               27814669                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 379416                       # Number of bytes of host memory used
+host_seconds                                  2520.18                       # Real time elapsed on the host
 sim_insts                                   278192519                       # Number of instructions simulated
-system.physmem.bytes_read                     4896576                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  65344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                  1867840                       # Number of bytes written to this memory
-system.physmem.num_reads                        76509                       # Number of read requests responded to by this memory
-system.physmem.num_writes                       29185                       # Number of write requests responded to by this memory
+system.physmem.bytes_read                     3896128                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                  65152                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                   892416                       # Number of bytes written to this memory
+system.physmem.num_reads                        60877                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       13944                       # Number of write requests responded to by this memory
 system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       69639752                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    929331                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      26564668                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      96204419                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read                       55581207                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    929442                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      12730988                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                      68312194                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        140625890                       # number of cpu cycles simulated
+system.cpu.numCycles                        140195878                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 37833804                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           37833804                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1322933                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              33591925                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 33081589                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 37928407                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           37928407                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1334678                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              33548417                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 33040245                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           29087381                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      203627812                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    37833804                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33081589                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      63297987                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                10276298                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               38195582                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   21                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles            95                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  28266291                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                204981                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          139497150                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.574262                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.291399                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           29060209                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      203598338                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    37928407                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33040245                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      63274026                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                10249926                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               38189577                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   18                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            77                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  28245503                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                214193                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          139407654                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.577879                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.292775                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 78673130     56.40%     56.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3606277      2.59%     58.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2810090      2.01%     61.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4532102      3.25%     64.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  6824412      4.89%     69.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  5279008      3.78%     72.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  7637539      5.48%     78.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  4315201      3.09%     81.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 25819391     18.51%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 78584615     56.37%     56.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3556242      2.55%     58.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2802198      2.01%     60.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4529245      3.25%     64.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  6913485      4.96%     69.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5169478      3.71%     72.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  7697084      5.52%     78.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4298531      3.08%     81.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 25856776     18.55%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            139497150                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.269039                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.448011                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 41917744                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              28560060                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  52643719                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               7459543                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                8916084                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              354657218                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                8916084                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 48823983                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4469241                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           6888                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  53004642                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              24276312                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              350176569                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    14                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 101342                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              20289844                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           314446851                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             861231533                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        861227904                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              3629                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            139407654                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.270539                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.452242                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 41988791                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              28417024                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  52030953                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               8087139                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                8883747                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              355040007                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                8883747                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 48483810                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4810408                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           9079                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  52929871                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              24290739                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              350051728                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    20                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 103496                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              20366187                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           314282471                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             860902327                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        860897388                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              4939                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             248344192                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 66102659                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                479                       # count of serializing insts renamed
+system.cpu.rename.UndoneMaps                 65938279                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                478                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts            472                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  56104077                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            112666461                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            37647255                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          48253520                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          8188094                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  343455788                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                2295                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 316242386                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             89834                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        65098177                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     92870721                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1849                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     139497150                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.267017                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.750973                       # Number of insts issued each cycle
+system.cpu.rename.skidInsts                  57634584                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            112617334                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            37601195                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          47838969                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          8379867                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  343415839                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                2328                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 316096096                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             78808                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        65029362                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     92942153                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1882                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     139407654                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.267423                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.745481                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            31795649     22.79%     22.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            18418675     13.20%     36.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            25717845     18.44%     54.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            29872112     21.41%     75.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            18507796     13.27%     89.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            10200782      7.31%     96.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             3199934      2.29%     98.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1737869      1.25%     99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8               46488      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            32098361     23.02%     23.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            17868067     12.82%     35.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            24417482     17.52%     53.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            32093883     23.02%     76.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            18421218     13.21%     89.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             9527374      6.83%     96.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             3128162      2.24%     98.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1804154      1.29%     99.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               48953      0.04%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       139497150                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       139407654                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   25785      1.36%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1795857     94.47%     95.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                 79349      4.17%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   25731      1.31%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1863505     95.00%     96.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                 72393      3.69%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             16711      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             180262574     57.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             180196286     57.01%     57.01% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     57.01% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 195      0.00%     57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 342      0.00%     57.01% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     57.01% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     57.01% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     57.01% # Type of FU issued
@@ -178,85 +178,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     57.01% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     57.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     57.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     57.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            101451147     32.08%     89.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            34511759     10.91%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            101438567     32.09%     89.10% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            34444190     10.90%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              316242386                       # Type of FU issued
-system.cpu.iq.rate                           2.248821                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1900991                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006011                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          773971833                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         408587092                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    312537049                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 914                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               2332                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          382                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              318126211                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     455                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         45906656                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              316096096                       # Type of FU issued
+system.cpu.iq.rate                           2.254675                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1961629                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006206                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          773638738                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         408477370                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    312370165                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                1545                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               3169                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          656                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              318040246                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     768                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         52318776                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     21887073                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       122159                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        33758                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6207504                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     21837946                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       139826                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        33737                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6161444                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         2763                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         15488                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3258                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          3821                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                8916084                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  901068                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 88602                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           343458083                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             26305                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             112666461                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             37647255                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                8883747                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  984872                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 88741                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           343418167                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             39651                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             112617334                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             37601195                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                465                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   1597                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 48733                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          33758                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1219939                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       230098                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1450037                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             314144155                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             100864248                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2098231                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                   1341                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 42673                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          33737                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1237180                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       215729                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1452909                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             313907375                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             100815222                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2188721                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    134973322                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31810521                       # Number of branches executed
-system.cpu.iew.exec_stores                   34109074                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.233900                       # Inst execution rate
-system.cpu.iew.wb_sent                      313190495                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     312537431                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 232392592                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 318468890                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    134855811                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31730666                       # Number of branches executed
+system.cpu.iew.exec_stores                   34040589                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.239063                       # Inst execution rate
+system.cpu.iew.wb_sent                      313087219                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     312370821                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 231825034                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 317282535                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.222474                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.729718                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.228103                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.730658                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      278192519                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        65270328                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        65229233                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             446                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1322946                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    130581066                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.130420                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.663472                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1334689                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    130523907                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.131353                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.650695                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     50414718     38.61%     38.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     24339651     18.64%     57.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     16499074     12.64%     69.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     12376450      9.48%     79.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3696747      2.83%     82.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      3466084      2.65%     84.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      2761727      2.11%     86.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1175320      0.90%     87.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     15851295     12.14%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     49374885     37.83%     37.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     24990571     19.15%     56.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     17165469     13.15%     70.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12454302      9.54%     79.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3472302      2.66%     82.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      3453203      2.65%     84.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      2713996      2.08%     87.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1124527      0.86%     87.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     15774652     12.09%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    130581066                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    130523907                       # Number of insts commited each cycle
 system.cpu.commit.count                     278192519                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      122219139                       # Number of memory references committed
@@ -266,49 +266,49 @@ system.cpu.commit.branches                   29309710                       # Nu
 system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 278186227                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              15851295                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              15774652                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    458192618                       # The number of ROB reads
-system.cpu.rob.rob_writes                   695856607                       # The number of ROB writes
-system.cpu.timesIdled                           33615                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         1128740                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    458171007                       # The number of ROB reads
+system.cpu.rob.rob_writes                   695745355                       # The number of ROB writes
+system.cpu.timesIdled                           23904                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          788224                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   278192519                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             278192519                       # Number of Instructions Simulated
-system.cpu.cpi                               0.505498                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.505498                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.978245                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.978245                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                554794614                       # number of integer regfile reads
-system.cpu.int_regfile_writes               279836675                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       437                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      335                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               201195947                       # number of misc regfile reads
-system.cpu.icache.replacements                     68                       # number of replacements
-system.cpu.icache.tagsinuse                824.679926                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 28264985                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   1027                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               27521.893866                       # Average number of references to valid blocks.
+system.cpu.cpi                               0.503953                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.503953                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.984313                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.984313                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                554439426                       # number of integer regfile reads
+system.cpu.int_regfile_writes               279882097                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       791                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      562                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               200975844                       # number of misc regfile reads
+system.cpu.icache.replacements                     62                       # number of replacements
+system.cpu.icache.tagsinuse                823.089414                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 28244206                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   1023                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               27609.194526                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            824.679926                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.402676                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               28264985                       # number of ReadReq hits
-system.cpu.icache.demand_hits                28264985                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               28264985                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1306                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1306                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1306                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       47073500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        47073500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       47073500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           28266291                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            28266291                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           28266291                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0            823.089414                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.401899                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               28244206                       # number of ReadReq hits
+system.cpu.icache.demand_hits                28244206                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               28244206                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 1297                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  1297                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 1297                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       46884000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        46884000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       46884000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           28245503                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            28245503                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           28245503                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate          0.000046                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate           0.000046                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate          0.000046                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36044.027565                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36044.027565                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36044.027565                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 36148.033924                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 36148.033924                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 36148.033924                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -318,166 +318,166 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               278                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                278                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               278                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            1028                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             1028                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            1028                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits               273                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                273                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               273                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            1024                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             1024                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            1024                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     36154500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     36154500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     36154500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     36044000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     36044000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     36044000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000036                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate      0.000036                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate     0.000036                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35169.747082                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35169.747082                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35169.747082                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35199.218750                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35199.218750                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35199.218750                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2073066                       # number of replacements
-system.cpu.dcache.tagsinuse               4076.005888                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 83808707                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2077162                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  40.347699                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            23845092000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4076.005888                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.995119                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               52611944                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              31196754                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                83808698                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               83808698                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              2262875                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              242997                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               2505872                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2505872                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    14629803500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    4394648436                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     19024451936                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    19024451936                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           54874819                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                2072801                       # number of replacements
+system.cpu.dcache.tagsinuse               4073.016957                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 77487718                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2076897                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  37.309370                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            23652058000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4073.016957                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.994389                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               46133976                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              31353733                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                77487709                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               77487709                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              2288597                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses               86018                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               2374615                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              2374615                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    13760644500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency    1501321288                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     15261965788                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    15261965788                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           48422573                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses          31439751                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            86314570                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           86314570                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.041237                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.007729                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.029032                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.029032                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency  6465.139922                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 18085.196262                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency  7591.948805                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency  7591.948805                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       289000                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses            79862324                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           79862324                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.047263                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.002736                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.029734                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.029734                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency  6012.698828                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 17453.571206                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency  6427.132730                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency  6427.132730                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                92                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  3141.304348                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1447147                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            291175                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           137531                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits             428706                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits            428706                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1971700                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         105466                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          2077166                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         2077166                       # number of overall MSHR misses
+system.cpu.dcache.writebacks                  1880524                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            293812                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits             3902                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits             297714                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits            297714                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1994785                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses          82116                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          2076901                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         2076901                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   5609142000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   1870309936                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   7479451936                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   7479451936                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   5560782500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency   1157739288                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   6718521788                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   6718521788                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.035931                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.003355                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.024065                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.024065                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2844.825278                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17733.771414                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  3600.796439                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  3600.796439                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.041195                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.002612                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.026006                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.026006                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2787.660074                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14098.827123                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  3234.878209                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  3234.878209                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                 49057                       # number of replacements
-system.cpu.l2cache.tagsinuse             18859.305089                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3318010                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 77063                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 43.055811                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                 33248                       # number of replacements
+system.cpu.l2cache.tagsinuse             18948.902283                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3764067                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 61254                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 61.450142                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          6747.919367                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         12111.385721                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.205930                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.369610                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               1938157                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             1447147                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               63526                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                2001683                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               2001683                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               34474                       # number of ReadReq misses
+system.cpu.l2cache.occ_blocks::0          6031.150094                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         12917.752189                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.184056                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.394219                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               1964318                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             1880524                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits               52728                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                2017046                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               2017046                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses               31362                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses             42035                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                76509                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               76509                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1179443000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   1438838000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     2618281000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    2618281000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1972631                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         1447147                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_misses             29515                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                60877                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses               60877                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency    1071112000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   1006258500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency     2077370500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency    2077370500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1995680                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         1880524                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          105561                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            2078192                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           2078192                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.017476                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_accesses           82243                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            2077923                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           2077923                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.015715                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.398206                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.036815                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.036815                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34212.536984                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34229.523017                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34221.869323                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34221.869323                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs        37500                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate       0.358876                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.029297                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.029297                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34153.179006                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34093.122141                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34124.061632                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34124.061632                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs               14                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  2678.571429                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   29185                       # number of writebacks
+system.cpu.l2cache.writebacks                   13944                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          34474                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses          31362                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        42035                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           76509                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          76509                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses        29515                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses           60877                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses          60877                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1069429500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency    972890000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1307209000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   2376638500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   2376638500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency    914988000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency   1887878000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency   1887878000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.017476                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.015715                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.398206                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.036815                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.036815                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.334919                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.358876                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.029297                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.029297                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.299662                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31098.108719                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.515403                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.515403                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.779265                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31011.350756                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31011.350756                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 9cc27361f7f4edf02f799f7feedb09df45b821c1..50d3ef0094d6df4caaa1252d7b5de1dc254d3776 100644 (file)
@@ -80,6 +80,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=true
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -502,9 +503,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
index de72d963a42ae6367748f9cdb04fe019f3d31dba..b3bd7cb12ccc6eb1b2dad0f9a289b400c7d3435c 100755 (executable)
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:58:28
-gem5 executing on zizzer
+gem5 compiled Jan 28 2012 12:11:40
+gem5 started Jan 28 2012 12:12:44
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -64,19 +66,9 @@ info: Increasing stack size by one page.
   the man with whom I play tennis is here 
   there is a dog in the park 
   this is not the man we know and love 
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
   we like to eat at restaurants , usually on weekends 
   what did John say he thought you should do 
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 493912286000 because target called exit()
+Exiting @ tick 488997764000 because target called exit()
index 92ece0bed4fca965d22f1339a6b1970d68e7b322..f99849c121efd9e09b02479de59269ce51b240d7 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.493912                       # Number of seconds simulated
-sim_ticks                                493912286000                       # Number of ticks simulated
-final_tick                               493912286000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.488998                       # Number of seconds simulated
+sim_ticks                                488997764000                       # Number of ticks simulated
+final_tick                               488997764000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 145271                       # Simulator instruction rate (inst/s)
-host_tick_rate                               46927205                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 251468                       # Number of bytes of host memory used
-host_seconds                                 10525.07                       # Real time elapsed on the host
+host_inst_rate                                 107684                       # Simulator instruction rate (inst/s)
+host_tick_rate                               34439407                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 280760                       # Number of bytes of host memory used
+host_seconds                                 14198.79                       # Real time elapsed on the host
 sim_insts                                  1528988756                       # Number of instructions simulated
-system.physmem.bytes_read                    37487424                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 347584                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 26320960                       # Number of bytes written to this memory
-system.physmem.num_reads                       585741                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      411265                       # Number of write requests responded to by this memory
+system.physmem.bytes_read                    37533312                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 347328                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 26337408                       # Number of bytes written to this memory
+system.physmem.num_reads                       586458                       # Number of read requests responded to by this memory
+system.physmem.num_writes                      411522                       # Number of write requests responded to by this memory
 system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       75898950                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    703736                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      53290758                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     129189708                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read                       76755590                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    710285                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                      53859976                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                     130615567                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        987824573                       # number of cpu cycles simulated
+system.cpu.numCycles                        977995529                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                245766486                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          245766486                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           16576996                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             236474058                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                218464201                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                244993586                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          244993586                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           16602389                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             235528185                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                217667296                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          205503020                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1343384866                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   245766486                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          218464201                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     436676837                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               119986236                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              218554807                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                32387                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        341323                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 194710374                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               4099618                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          964252463                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.599701                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.317490                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          204934624                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1339258211                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   244993586                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          217667296                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     435322465                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               118846275                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              217468055                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                30116                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        232804                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 194158401                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               4161421                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          959969834                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.603022                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.318234                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                531629837     55.13%     55.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 32377332      3.36%     58.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 38827894      4.03%     62.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 32536894      3.37%     65.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 21844251      2.27%     68.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 36448993      3.78%     71.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 49128972      5.10%     77.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 36937786      3.83%     80.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                184520504     19.14%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                528643490     55.07%     55.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 32333608      3.37%     58.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 38757249      4.04%     62.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 32421466      3.38%     65.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 21788164      2.27%     68.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 36314533      3.78%     71.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 48923013      5.10%     77.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 36860126      3.84%     80.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                183928185     19.16%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            964252463                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.248796                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.359943                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                264509435                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             174554141                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 373011587                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              49033211                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              103144089                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2445932072                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                     1                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              103144089                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                301738657                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                40282868                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          12225                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 383467875                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             135606749                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2393375507                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  2559                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               25131978                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              92224846                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents                8                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          2227188673                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5629907069                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       5629667957                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            239112                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            959969834                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.250506                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.369391                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                264672814                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             172740484                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 371802947                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              48771819                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              101981770                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2436948242                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles              101981770                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                302199214                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                38454889                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          15108                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 381795429                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             135523424                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2384665027                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  2593                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               22692453                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              94335239                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents               23                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          2218279276                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5608704737                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       5608168752                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            535985                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1427299027                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                799889646                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1309                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1288                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 318947403                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            577879232                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           226530900                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         227222440                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         65937432                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2286709085                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               12489                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1922370305                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1306641                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       755226802                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1190125426                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          11936                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     964252463                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.993638                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.811521                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                790980249                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1421                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1399                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 314817660                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            575520947                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           225733737                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         224565693                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         66120103                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2277627469                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               14301                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1920324328                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1300872                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       746152360                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1169098860                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          13748                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     959969834                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.000401                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.810923                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           282911384     29.34%     29.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           160280603     16.62%     45.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           162550496     16.86%     62.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           148847741     15.44%     78.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           109081156     11.31%     89.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            60080329      6.23%     95.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            30822605      3.20%     99.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             8641604      0.90%     99.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1036545      0.11%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           279838383     29.15%     29.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           159390008     16.60%     45.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           161109543     16.78%     62.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           151059392     15.74%     78.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           108561364     11.31%     89.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            60361287      6.29%     95.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            29161241      3.04%     98.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             9391207      0.98%     99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1097409      0.11%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       964252463                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       959969834                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 2246339     14.60%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     14.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               10026447     65.19%     79.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3108042     20.21%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2254063     14.63%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     14.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               10153281     65.89%     80.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3001149     19.48%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2420122      0.13%      0.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1274712167     66.31%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   5      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            463703127     24.12%     90.56% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           181534884      9.44%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2493580      0.13%      0.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1273165358     66.30%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.43% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            463198530     24.12%     90.55% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           181466860      9.45%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1922370305                       # Type of FU issued
-system.cpu.iq.rate                           1.946064                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    15380828                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.008001                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4825675637                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3042139517                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1874661917                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                4905                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              81824                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          136                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1935329448                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                    1563                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        158391521                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1920324328                       # Type of FU issued
+system.cpu.iq.rate                           1.963531                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    15408493                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.008024                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4817321768                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3023912415                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1872800388                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                6087                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             152738                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          154                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1933237228                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    2013                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        171308750                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    193777072                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       372742                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       283642                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     77371112                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    191418787                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       428547                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       281164                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     76573878                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         2379                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            25                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         6486                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             8                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              103144089                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 9045659                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1404502                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2286721574                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           1118432                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             577879232                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            226531297                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               6081                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1006586                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 29974                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         283642                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       15693422                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      2344063                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             18037485                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1889150749                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             454748002                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          33219556                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles              101981770                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 7663639                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1191899                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2277641770                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1232812                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             575520947                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            225734063                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               6109                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 836752                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 17253                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         281164                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       15662112                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      2402353                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             18064465                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1886684972                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             454230068                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          33639356                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    629271939                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                176719729                       # Number of branches executed
-system.cpu.iew.exec_stores                  174523937                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.912435                       # Inst execution rate
-system.cpu.iew.wb_sent                     1882531239                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1874662053                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1440606287                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2134778201                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    628354292                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                176563619                       # Number of branches executed
+system.cpu.iew.exec_stores                  174124224                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.929135                       # Inst execution rate
+system.cpu.iew.wb_sent                     1880378728                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1872800542                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1438142804                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2128029574                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.897768                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.674827                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.914938                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.675810                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts     1528988756                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       757743569                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       748676946                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             553                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          16604349                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    861108374                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.775605                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.288022                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          16628282                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    857988064                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.782063                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.285478                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    338327816     39.29%     39.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    210551706     24.45%     63.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     75360819      8.75%     72.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     92562974     10.75%     83.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     34054041      3.95%     87.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     27955182      3.25%     90.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     16032820      1.86%     92.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     12266632      1.42%     93.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     53996384      6.27%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    333514129     38.87%     38.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    211603589     24.66%     63.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     76333139      8.90%     72.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     92892872     10.83%     83.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     33741100      3.93%     87.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     28402540      3.31%     90.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     15787299      1.84%     92.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     11367789      1.32%     93.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     54345607      6.33%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    861108374                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    857988064                       # Number of insts commited each cycle
 system.cpu.commit.count                    1528988756                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      533262345                       # Number of memory references committed
@@ -268,49 +267,48 @@ system.cpu.commit.branches                  149758588                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1528317614                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              53996384                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              54345607                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3093844315                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4676786954                       # The number of ROB writes
-system.cpu.timesIdled                          606516                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        23572110                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3081308159                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4657476889                       # The number of ROB writes
+system.cpu.timesIdled                          418960                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        18025695                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1528988756                       # Number of Instructions Simulated
 system.cpu.committedInsts_total            1528988756                       # Number of Instructions Simulated
-system.cpu.cpi                               0.646064                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.646064                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.547834                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.547834                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3179044858                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1744829680                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       145                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                        5                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              1039286160                       # number of misc regfile reads
-system.cpu.icache.replacements                  10045                       # number of replacements
-system.cpu.icache.tagsinuse                976.337758                       # Cycle average of tags in use
-system.cpu.icache.total_refs                194480398                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  11548                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               16841.045895                       # Average number of references to valid blocks.
+system.cpu.cpi                               0.639636                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.639636                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.563390                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.563390                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3178059548                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1743141344                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       155                       # number of floating regfile reads
+system.cpu.misc_regfile_reads              1037170422                       # number of misc regfile reads
+system.cpu.icache.replacements                  10067                       # number of replacements
+system.cpu.icache.tagsinuse                971.911936                       # Cycle average of tags in use
+system.cpu.icache.total_refs                193916703                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  11565                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               16767.548898                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            976.337758                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.476727                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              194486608                       # number of ReadReq hits
-system.cpu.icache.demand_hits               194486608                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              194486608                       # number of overall hits
-system.cpu.icache.ReadReq_misses               223766                       # number of ReadReq misses
-system.cpu.icache.demand_misses                223766                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses               223766                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency     1539723000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency      1539723000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency     1539723000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          194710374                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           194710374                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          194710374                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.001149                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.001149                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.001149                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency  6880.951530                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency  6880.951530                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency  6880.951530                       # average overall miss latency
+system.cpu.icache.occ_blocks::0            971.911936                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.474566                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              193923334                       # number of ReadReq hits
+system.cpu.icache.demand_hits               193923334                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              193923334                       # number of overall hits
+system.cpu.icache.ReadReq_misses               235067                       # number of ReadReq misses
+system.cpu.icache.demand_misses                235067                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses               235067                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency     1701123000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency      1701123000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency     1701123000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          194158401                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           194158401                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          194158401                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.001211                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.001211                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.001211                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency  7236.758031                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency  7236.758031                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency  7236.758031                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -319,137 +317,137 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        6                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              2071                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               2071                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              2071                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses          221695                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses           221695                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses          221695                       # number of overall MSHR misses
+system.cpu.icache.writebacks                        8                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits              2036                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               2036                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              2036                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses          233031                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses           233031                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses          233031                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    824417000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    824417000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    824417000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    952412000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    952412000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    952412000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.001139                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.001139                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.001139                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  3718.699114                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  3718.699114                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  3718.699114                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.001200                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.001200                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.001200                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  4087.061378                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  4087.061378                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  4087.061378                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2527930                       # number of replacements
-system.cpu.dcache.tagsinuse               4087.566272                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                440586260                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2532026                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 174.005425                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             2135798000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4087.566272                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.997941                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              291836002                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             147579227                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               439415229                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              439415229                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              3119681                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1580974                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               4700655                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              4700655                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    52079313500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   37355392500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     89434706000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    89434706000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          294955683                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                2529213                       # number of replacements
+system.cpu.dcache.tagsinuse               4087.436678                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                427576950                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2533309                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 168.781996                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             2167021000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           4087.436678                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.997909                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits              278854362                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits             148163093                       # number of WriteReq hits
+system.cpu.dcache.demand_hits               427017455                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits              427017455                       # number of overall hits
+system.cpu.dcache.ReadReq_misses              2666620                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses              997108                       # number of WriteReq misses
+system.cpu.dcache.demand_misses               3663728                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses              3663728                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency    39487606500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency   20600704500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency     60088311000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency    60088311000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses          281520982                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses         149160201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           444115884                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          444115884                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.010577                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.010599                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.010584                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.010584                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 16693.794494                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 23628.087812                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 19026.009354                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 19026.009354                       # average overall miss latency
+system.cpu.dcache.demand_accesses           430681183                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses          430681183                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.009472                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.006685                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.008507                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.008507                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 14808.111579                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 20660.454535                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 16400.865730                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 16400.865730                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        29000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets        14500                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  2229595                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits           1359154                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           607660                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1966814                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1966814                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1760527                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         973314                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          2733841                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         2733841                       # number of overall MSHR misses
+system.cpu.dcache.writebacks                  2229973                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits            903774                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits             5204                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits             908978                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits            908978                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses         1762846                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses         991904                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses          2754750                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses         2754750                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  14908482500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency  17169522000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  32078004500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  32078004500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency  14963544500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency  17553990000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency  32517534500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency  32517534500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.005969                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.006525                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.006156                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.006156                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8468.193047                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17640.270252                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11733.675989                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11733.675989                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.006262                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.006650                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.006396                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.006396                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8488.287973                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17697.267074                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 11804.168981                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 11804.168981                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                574945                       # number of replacements
-system.cpu.l2cache.tagsinuse             21597.257673                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3194359                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                594122                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  5.376604                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          271429089000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          7797.131828                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         13800.125845                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.237950                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.421146                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               1433279                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             2229601                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits               1240                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits              524400                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                1957679                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               1957679                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses              338611                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses           208876                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses            247152                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               585763                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              585763                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   11564612500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency      9756500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   8478074500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency    20042687000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency   20042687000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1771890                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         2229601                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses         210116                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          771552                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            2543442                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           2543442                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.191102                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate      0.994098                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.320331                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.230303                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.230303                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34153.091601                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency    46.709531                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34303.078672                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34216.375906                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34216.375906                       # average overall miss latency
+system.cpu.l2cache.replacements                575697                       # number of replacements
+system.cpu.l2cache.tagsinuse             21610.714484                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3195541                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                594856                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  5.371957                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          269628029000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          7828.943593                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         13781.770891                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.238920                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.420586                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits               1434292                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits             2229981                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits               1300                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits              523974                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                1958266                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits               1958266                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses              339366                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses           220134                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses            247116                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses               586482                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses              586482                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency   11591670000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency      9750500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency   8467686500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency    20059356500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency   20059356500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses           1773658                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses         2229981                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses         221434                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses          771090                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses            2544748                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses           2544748                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.191337                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate      0.994129                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.320476                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.230468                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.230468                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34156.839518                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency    44.293476                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34266.039026                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34202.851068                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34202.851068                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -458,31 +456,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                  411265                       # number of writebacks
+system.cpu.l2cache.writebacks                  411522                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses         338611                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses       208876                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       247152                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          585763                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         585763                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses         339366                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses       220134                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses       247116                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses          586482                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses         586482                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  10503665500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   6475353000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   7666739500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  18170405000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  18170405000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency  10527298500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency   6824577500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency   7661565500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency  18188864000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency  18188864000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.191102                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.994098                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.320331                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.230303                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.230303                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.859071                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.943143                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.341733                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31020.062722                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31020.062722                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.191337                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.994129                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.320476                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.230468                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.230468                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.486731                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31001.923828                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31003.923259                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31013.507661                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31013.507661                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 0cd9938efe5361adb1d0d4d8896295c8580e5df3..b8115d922c972838dbeff03681817f54dc4189fd 100644 (file)
@@ -80,6 +80,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=true
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -502,7 +503,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
index 1f9424384b2ce55403bd477bfe00ff3a49b20aed..3d5ba32f277ca8eb7310ab5834d8894bc628170b 100755 (executable)
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 07:52:38
-gem5 executing on zizzer
+gem5 compiled Jan 28 2012 12:11:40
+gem5 started Jan 28 2012 12:12:43
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
 Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav
 Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2
@@ -24,4 +26,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 96689893000 because target called exit()
+122 123 124 Exiting @ tick 96605044000 because target called exit()
index 71e8505e44bc45385339cb64fc3b56b65e555ea9..5be6519a99e6330003490948c52ccb66db23f8f1 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.096690                       # Number of seconds simulated
-sim_ticks                                 96689893000                       # Number of ticks simulated
-final_tick                                96689893000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.096605                       # Number of seconds simulated
+sim_ticks                                 96605044000                       # Number of ticks simulated
+final_tick                                96605044000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 118200                       # Simulator instruction rate (inst/s)
-host_tick_rate                               51629155                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224032                       # Number of bytes of host memory used
-host_seconds                                  1872.78                       # Real time elapsed on the host
+host_inst_rate                                  67425                       # Simulator instruction rate (inst/s)
+host_tick_rate                               29425038                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253272                       # Number of bytes of host memory used
+host_seconds                                  3283.09                       # Real time elapsed on the host
 sim_insts                                   221363017                       # Number of instructions simulated
-system.physmem.bytes_read                      340224                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 215424                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read                      339456                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 214848                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                         5316                       # Number of read requests responded to by this memory
+system.physmem.num_reads                         5304                       # Number of read requests responded to by this memory
 system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
 system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        3518713                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                   2227989                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                       3518713                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read                        3513854                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   2223983                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       3513854                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        193379787                       # number of cpu cycles simulated
+system.cpu.numCycles                        193210089                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 25818202                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           25818202                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            2898724                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              23602930                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 20841363                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 25792325                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           25792325                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            2895497                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              23600664                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 20878395                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           30995459                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      261573615                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    25818202                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           20841363                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      70808397                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                26924712                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               67767699                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  120                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1017                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  28859729                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                549788                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          193293197                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.259018                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.335260                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           30964428                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      261331282                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    25792325                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           20878395                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      70767464                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                26891019                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               67713706                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  142                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1189                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  28829274                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                550737                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          193129824                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.258996                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.335178                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                124336745     64.33%     64.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4112034      2.13%     66.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  3238737      1.68%     68.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4462671      2.31%     70.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4295145      2.22%     72.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4476640      2.32%     74.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5418723      2.80%     77.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3020771      1.56%     79.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 39931731     20.66%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                124221202     64.32%     64.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4112630      2.13%     66.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  3244602      1.68%     68.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4465272      2.31%     70.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4293373      2.22%     72.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  4464358      2.31%     74.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5413333      2.80%     77.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3013911      1.56%     79.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 39901143     20.66%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            193293197                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.133510                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.352642                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 44764810                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              57827624                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  57161965                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9818293                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               23720505                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              424367292                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               23720505                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 53388300                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                14632169                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          21921                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  57615812                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              43914490                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              411765049                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    18                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               19034939                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              22478875                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           438156432                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1066580371                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1055689317                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          10891054                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            193129824                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.133494                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.352576                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 44734521                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              57786241                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  57127863                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9798304                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               23682895                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              423946385                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               23682895                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 53367953                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                14712731                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          23142                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  57547510                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              43795593                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              411406798                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    10                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               18855699                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              22517657                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           437782007                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1065797846                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1054993887                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          10803959                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             234363409                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                203793023                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1794                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1788                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  94980657                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            104262380                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            37289638                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          67232013                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         21668119                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  396788007                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                2705                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 287703359                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            254770                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       174855842                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    350938331                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1459                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     193293197                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.488430                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.480803                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                203418598                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1777                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1771                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  94869536                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            104184220                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            37252864                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          66898151                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         21504625                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  396406110                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                2683                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 287681996                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            245770                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       174447554                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    349871098                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1437                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     193129824                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.489578                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.482432                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            60724695     31.42%     31.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            54019027     27.95%     59.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            35712551     18.48%     77.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            21012235     10.87%     88.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            13686479      7.08%     95.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             5222239      2.70%     98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2184583      1.13%     99.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              593188      0.31%     99.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              138200      0.07%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            60692059     31.43%     31.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            53894832     27.91%     59.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            35675096     18.47%     77.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            21030275     10.89%     88.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            13671463      7.08%     95.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             5219808      2.70%     98.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2207559      1.14%     99.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              593955      0.31%     99.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              144777      0.07%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       193293197                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       193129824                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  110269      4.01%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2317531     84.31%     88.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                321034     11.68%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  112792      4.13%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2307770     84.43%     88.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                312724     11.44%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           1208234      0.42%      0.42% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             187072997     65.02%     65.44% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     65.44% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.44% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             1650386      0.57%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.02% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             73223880     25.45%     91.47% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            24547862      8.53%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           1204873      0.42%      0.42% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             186986858     65.00%     65.42% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     65.42% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.42% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1646787      0.57%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             73289266     25.48%     91.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            24554212      8.54%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              287703359                       # Type of FU issued
-system.cpu.iq.rate                           1.487763                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2748834                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.009554                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          766190945                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         566572341                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    278374724                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             5512574                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            5407408                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      2648186                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              286471551                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2772408                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         18351013                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              287681996                       # Type of FU issued
+system.cpu.iq.rate                           1.488959                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2733286                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.009501                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          765968498                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         565842765                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    278370688                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             5504374                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            5354879                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      2643921                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              286442288                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2768121                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         18982398                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     47612790                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        32223                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       339608                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     16773922                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     47534630                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        34246                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       347654                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     16737148                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        46155                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads        48277                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               23720505                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  359624                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                213865                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           396790712                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            135718                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             104262380                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             37289638                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1786                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 119790                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 15845                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         339608                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        2505263                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       598160                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              3103423                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             283855997                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              71689961                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3847362                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               23682895                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  506655                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                213138                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           396408793                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            134440                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             104184220                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             37252864                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1768                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 119463                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 15480                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         347654                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        2501516                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       594763                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              3096279                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             283823488                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              71745820                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3858508                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     95739480                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 15662592                       # Number of branches executed
-system.cpu.iew.exec_stores                   24049519                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.467868                       # Inst execution rate
-system.cpu.iew.wb_sent                      282319460                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     281022910                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 227917239                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 378870882                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     95800830                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15659373                       # Number of branches executed
+system.cpu.iew.exec_stores                   24055010                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.468989                       # Inst execution rate
+system.cpu.iew.wb_sent                      282310074                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     281014609                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 227952457                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 378837228                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.453218                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.601570                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.454451                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.601716                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      221363017                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       175435625                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       175071707                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1246                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           2898838                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    169572692                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.305417                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.741291                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           2895631                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    169446929                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.306386                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.743043                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     63662174     37.54%     37.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     62350604     36.77%     74.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15592003      9.19%     83.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     11999288      7.08%     90.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      5440588      3.21%     93.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2982193      1.76%     95.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      2011991      1.19%     96.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1185528      0.70%     97.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      4348323      2.56%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     63655929     37.57%     37.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     62181133     36.70%     74.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15647987      9.23%     83.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     11995121      7.08%     90.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      5411057      3.19%     93.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2989620      1.76%     95.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      2014905      1.19%     96.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1190627      0.70%     97.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4360550      2.57%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    169572692                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    169446929                       # Number of insts commited each cycle
 system.cpu.commit.count                     221363017                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       77165306                       # Number of memory references committed
@@ -265,50 +265,50 @@ system.cpu.commit.branches                   12326943                       # Nu
 system.cpu.commit.fp_insts                    2162459                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 220339606                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               4348323                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               4360550                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    562023011                       # The number of ROB reads
-system.cpu.rob.rob_writes                   817360743                       # The number of ROB writes
-system.cpu.timesIdled                            1880                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           86590                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    561521103                       # The number of ROB reads
+system.cpu.rob.rob_writes                   816599274                       # The number of ROB writes
+system.cpu.timesIdled                            1748                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           80265                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   221363017                       # Number of Instructions Simulated
 system.cpu.committedInsts_total             221363017                       # Number of Instructions Simulated
-system.cpu.cpi                               0.873587                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.873587                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.144706                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.144706                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                530675330                       # number of integer regfile reads
-system.cpu.int_regfile_writes               288962100                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   3614411                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2302807                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               149913222                       # number of misc regfile reads
+system.cpu.cpi                               0.872820                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.872820                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.145711                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.145711                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                530797158                       # number of integer regfile reads
+system.cpu.int_regfile_writes               288957450                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   3607584                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2298041                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               149916629                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    844                       # number of misc regfile writes
-system.cpu.icache.replacements                   4227                       # number of replacements
-system.cpu.icache.tagsinuse               1595.324923                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 28852140                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   6194                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                4658.078786                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                   4194                       # number of replacements
+system.cpu.icache.tagsinuse               1596.157530                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 28821740                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   6159                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                4679.613574                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1595.324923                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.778967                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               28852140                       # number of ReadReq hits
-system.cpu.icache.demand_hits                28852140                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               28852140                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 7589                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  7589                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 7589                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      174464500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       174464500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      174464500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           28859729                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            28859729                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           28859729                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000263                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000263                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000263                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 22989.129003                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 22989.129003                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 22989.129003                       # average overall miss latency
+system.cpu.icache.occ_blocks::0           1596.157530                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.779374                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               28821740                       # number of ReadReq hits
+system.cpu.icache.demand_hits                28821740                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               28821740                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 7534                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  7534                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 7534                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      174012500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       174012500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      174012500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           28829274                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            28829274                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           28829274                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000261                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000261                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000261                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 23096.960446                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 23096.960446                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 23096.960446                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -318,59 +318,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              1125                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               1125                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              1125                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            6464                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             6464                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            6464                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_hits              1131                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits               1131                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits              1131                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            6403                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             6403                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            6403                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    125677000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    125677000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    125677000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency    125261500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    125261500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    125261500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000224                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000224                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000224                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 19442.605198                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 19442.605198                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 19442.605198                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000222                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000222                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000222                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 19562.939247                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 19562.939247                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 19562.939247                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                     59                       # number of replacements
-system.cpu.dcache.tagsinuse               1416.877097                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 73598603                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                   1986                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               37058.712487                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                     57                       # number of replacements
+system.cpu.dcache.tagsinuse               1416.139533                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 73025896                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1980                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               36881.765657                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           1416.877097                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.345917                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               53090649                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              20507453                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                73598102                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               73598102                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  848                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                8277                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                  9125                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 9125                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       26447500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency     228348000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency       254795500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      254795500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           53091497                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::0           1416.139533                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.345737                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               52511655                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              20513921                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                73025576                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               73025576                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  756                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                1809                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                  2565                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 2565                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       24125500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency      68553000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency        92678500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency       92678500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           52512411                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses          20515730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            73607227                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           73607227                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000016                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000403                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.000124                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000124                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 31188.089623                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 27588.256615                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 27922.794521                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 27922.794521                       # average overall miss latency
+system.cpu.dcache.demand_accesses            73028141                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           73028141                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000014                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000088                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.000035                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000035                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 31912.037037                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 37895.522388                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 36131.968811                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 36131.968811                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -380,71 +380,71 @@ system.cpu.dcache.avg_blocked_cycles::no_targets     no_value
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks                       14                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits               424                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits             6443                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits               6867                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits              6867                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             424                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           1834                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             2258                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            2258                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits               336                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits                2                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits                338                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits               338                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             420                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1807                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             2227                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            2227                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     13981500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency     64146500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency     78128000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency     78128000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency     13927500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     63059000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     76986500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     76986500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000008                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000031                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000031                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32975.235849                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34976.281352                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 34600.531444                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 34600.531444                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000088                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000030                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000030                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 33160.714286                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34897.066962                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34569.600359                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 34569.600359                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              2499.166941                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    2858                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                  3763                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.759500                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              2497.262524                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    2830                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3752                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.754264                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          2497.181729                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1             1.985212                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.076208                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.000061                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                  2857                       # number of ReadReq hits
+system.cpu.l2cache.occ_blocks::0          2495.282024                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             1.980500                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.076150                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000060                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                  2828                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits                  14                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits                   8                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                   2865                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                  2865                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                3759                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses              270                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses              1557                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 5316                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                5316                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     128731000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency     53240500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      181971500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     181971500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses              6616                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.demand_hits                   2836                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  2836                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                3749                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses              245                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses              1555                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 5304                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                5304                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     128398000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     53104500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      181502500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     181502500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              6577                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses              14                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses            270                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            1565                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses               8181                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses              8181                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.568168                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_accesses            245                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            1563                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses               8140                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              8140                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.570017                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.994888                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.649798                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.649798                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34246.076084                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34194.283879                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34230.906697                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34230.906697                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate       0.994882                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.651597                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.651597                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34248.599627                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34150.803859                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34219.928356                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34219.928356                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -456,28 +456,28 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           3759                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses          270                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         1557                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            5316                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           5316                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses           3749                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses          245                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1555                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            5304                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           5304                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    116600500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency      8370000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     48374500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    164975000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    164975000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency    116287000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency      7595000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     48232500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    164519500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    164519500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.568168                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.570017                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.994888                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.649798                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.649798                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.021016                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.994882                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.651597                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.651597                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.138170                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.043031                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.671934                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.671934                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31017.684887                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31018.005279                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31018.005279                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
index 8582c91b49f3fd490b2e8706ab45a68399848eac..8f8ece24e409bb3f2741540c66acea1a466d6b77 100644 (file)
@@ -80,6 +80,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=true
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -502,7 +503,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
index 4c371922ed2de914f9a00bf658a02af3ac99a7d9..b49f2b57222c223af3462736949aac38f0eef606 100755 (executable)
@@ -1,12 +1,13 @@
+Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 04:24:37
-gem5 executing on zizzer
+gem5 compiled Jan 28 2012 12:11:40
+gem5 started Jan 28 2012 12:11:57
+gem5 executing on ribera.cs.wisc.edu
 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 11087000 because target called exit()
+Exiting @ tick 11989500 because target called exit()
index e2df7b059d014b858b65c7af7e9c7b6cae9769aa..8477728c88558a11a2efb480ac1fb5c8a63453d1 100644 (file)
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000011                       # Number of seconds simulated
-sim_ticks                                    11087000                       # Number of ticks simulated
-final_tick                                   11087000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000012                       # Number of seconds simulated
+sim_ticks                                    11989500                       # Number of ticks simulated
+final_tick                                   11989500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  31087                       # Simulator instruction rate (inst/s)
-host_tick_rate                               35135175                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 212404                       # Number of bytes of host memory used
-host_seconds                                     0.32                       # Real time elapsed on the host
+host_inst_rate                                   1330                       # Simulator instruction rate (inst/s)
+host_tick_rate                                1625690                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 239860                       # Number of bytes of host memory used
+host_seconds                                     7.38                       # Real time elapsed on the host
 sim_insts                                        9809                       # Number of instructions simulated
 system.physmem.bytes_read                       28288                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  18944                       # Number of instructions bytes read from this memory
@@ -15,247 +15,247 @@ system.physmem.bytes_written                        0                       # Nu
 system.physmem.num_reads                          442                       # Number of read requests responded to by this memory
 system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
 system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     2551456661                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                1708667809                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    2551456661                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read                     2359397806                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                1580049210                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    2359397806                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            22175                       # number of cpu cycles simulated
+system.cpu.numCycles                            23980                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     3056                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               3056                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect                497                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  2731                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      995                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     3019                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               3019                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect                495                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  2695                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      978                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               5895                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          13997                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        3056                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                995                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          3968                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    2221                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   1500                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles               7194                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          13831                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        3019                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                978                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          3921                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    2194                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                   3367                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles             9                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      1891                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   271                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              13088                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.930776                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.218766                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      1866                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   269                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              16182                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.543567                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.980612                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     9227     70.50%     70.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      167      1.28%     71.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      175      1.34%     73.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      239      1.83%     74.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      232      1.77%     76.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      193      1.47%     78.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      279      2.13%     80.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      139      1.06%     81.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2437     18.62%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    12367     76.42%     76.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      166      1.03%     77.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      172      1.06%     78.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      238      1.47%     79.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      224      1.38%     81.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      191      1.18%     82.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      276      1.71%     84.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      137      0.85%     85.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2411     14.90%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                13088                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.137813                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.631206                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     6247                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1453                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      3565                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   111                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1712                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  24090                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1712                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     6535                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     523                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            524                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      3365                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   429                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  22712                       # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total                16182                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.125897                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.576772                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     7550                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  3315                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      3508                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   122                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1687                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  23802                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                   1687                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     7843                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    2077                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            553                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      3329                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   693                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  22457                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                     2                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                     68                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   272                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               21246                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 47645                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            47629                       # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents                   553                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               21026                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 47090                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            47074                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  9368                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    11878                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                    11658                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 33                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             33                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      1613                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2238                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1782                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts                      1820                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2219                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1751                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                13                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                8                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      20539                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      20306                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  37                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     16958                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                63                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           10220                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        12992                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                     16792                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                56                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined           10001                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        12754                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             24                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         13088                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.295691                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.003315                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         16182                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.037696                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.845376                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                8001     61.13%     61.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1108      8.47%     69.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1006      7.69%     77.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 733      5.60%     82.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 670      5.12%     88.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 725      5.54%     93.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 615      4.70%     98.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 196      1.50%     99.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  34      0.26%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10903     67.38%     67.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1372      8.48%     75.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1062      6.56%     82.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 680      4.20%     86.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 659      4.07%     90.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 684      4.23%     94.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 588      3.63%     98.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 200      1.24%     99.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  34      0.21%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           13088                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           16182                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      94     66.67%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     24     17.02%     83.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    23     16.31%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      86     64.66%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     24     18.05%     82.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    23     17.29%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 4      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 13641     80.44%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.46% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1843     10.87%     91.33% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1470      8.67%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 13517     80.50%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.52% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1828     10.89%     91.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1443      8.59%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  16958                       # Type of FU issued
-system.cpu.iq.rate                           0.764735                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         141                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.008315                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              47200                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             30804                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        15755                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  16792                       # Type of FU issued
+system.cpu.iq.rate                           0.700250                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         133                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.007920                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              49947                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             30352                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        15608                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  17091                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  16917                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               80                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads              142                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1182                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1163                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses           12                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           12                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          848                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          817                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1712                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     144                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    16                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               20576                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts                23                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2238                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1782                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                   1687                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    1417                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    38                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               20343                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                26                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2219                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1751                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 33                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      6                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             12                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect             65                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          523                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  588                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 16100                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1742                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               858                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedNotTakenIncorrect          525                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  590                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 15942                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1725                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               850                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3105                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1601                       # Number of branches executed
-system.cpu.iew.exec_stores                       1363                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.726043                       # Inst execution rate
-system.cpu.iew.wb_sent                          15918                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         15759                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                     10538                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     15699                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3065                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1589                       # Number of branches executed
+system.cpu.iew.exec_stores                       1340                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.664804                       # Inst execution rate
+system.cpu.iew.wb_sent                          15766                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         15612                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                     10251                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     15131                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.710665                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.671253                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.651043                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.677483                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           9809                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts           10766                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           10533                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              13                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               497                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        11376                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.862254                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.686850                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               495                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        14495                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.676716                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.510487                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         7944     69.83%     69.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1088      9.56%     79.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          574      5.05%     84.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          883      7.76%     92.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          343      3.02%     95.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          152      1.34%     96.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          139      1.22%     97.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           66      0.58%     98.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          187      1.64%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10831     74.72%     74.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1349      9.31%     84.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          680      4.69%     88.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          780      5.38%     94.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          337      2.32%     96.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          129      0.89%     97.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          140      0.97%     98.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           65      0.45%     98.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          184      1.27%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        11376                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        14495                       # Number of insts commited each cycle
 system.cpu.commit.count                          9809                       # Number of instructions committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                           1990                       # Number of memory references committed
@@ -265,48 +265,48 @@ system.cpu.commit.branches                       1214                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      9714                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                   187                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   184                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        31764                       # The number of ROB reads
-system.cpu.rob.rob_writes                       42896                       # The number of ROB writes
-system.cpu.timesIdled                             182                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                            9087                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        34653                       # The number of ROB reads
+system.cpu.rob.rob_writes                       42403                       # The number of ROB writes
+system.cpu.timesIdled                             150                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                            7798                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        9809                       # Number of Instructions Simulated
 system.cpu.committedInsts_total                  9809                       # Number of Instructions Simulated
-system.cpu.cpi                               2.260679                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.260679                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.442345                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.442345                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    23665                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   14645                       # number of integer regfile writes
+system.cpu.cpi                               2.444694                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.444694                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.409049                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.409049                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    23430                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   14518                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
-system.cpu.misc_regfile_reads                    7211                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                    7136                       # number of misc regfile reads
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                145.144237                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1527                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                140.870525                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1498                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    298                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   5.124161                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   5.026846                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            145.144237                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.070871                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   1527                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    1527                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   1527                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  364                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   364                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  364                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       13314500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        13314500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       13314500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               1891                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                1891                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               1891                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.192491                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.192491                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.192491                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36578.296703                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36578.296703                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36578.296703                       # average overall miss latency
+system.cpu.icache.occ_blocks::0            140.870525                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.068784                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits                   1498                       # number of ReadReq hits
+system.cpu.icache.demand_hits                    1498                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits                   1498                       # number of overall hits
+system.cpu.icache.ReadReq_misses                  368                       # number of ReadReq misses
+system.cpu.icache.demand_misses                   368                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                  368                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency       13394000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency        13394000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency       13394000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses               1866                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses                1866                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses               1866                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.197213                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.197213                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.197213                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 36396.739130                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 36396.739130                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 36396.739130                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -316,59 +316,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets     no_value
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits                66                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                 66                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                66                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits                70                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                 70                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                70                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses             298                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses              298                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses             298                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     10466500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     10466500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     10466500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     10471500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     10471500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     10471500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.157589                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.157589                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.157589                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35122.483221                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35122.483221                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35122.483221                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate     0.159700                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.159700                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.159700                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35139.261745                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35139.261745                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35139.261745                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 85.499149                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2112                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 83.526549                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2275                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    145                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  14.565517                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  15.689655                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             85.499149                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.020874                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1494                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   618                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    2112                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   2112                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  113                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                 316                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   429                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  429                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        3938500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      10708500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency        14647000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       14647000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1607                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::0             83.526549                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.020392                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits                   1417                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits                   858                       # number of WriteReq hits
+system.cpu.dcache.demand_hits                    2275                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits                   2275                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  111                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                  76                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                   187                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                  187                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency        3859500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency       2916500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency         6776000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency        6776000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses               1528                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses               934                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2541                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2541                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.070317                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.338330                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.168831                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.168831                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 34853.982301                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33887.658228                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 34142.191142                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 34142.191142                       # average overall miss latency
+system.cpu.dcache.demand_accesses                2462                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses               2462                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.072644                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.081370                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.075955                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.075955                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 34770.270270                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency        38375                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 36235.294118                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 36235.294118                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -378,63 +378,62 @@ system.cpu.dcache.avg_blocked_cycles::no_targets     no_value
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                44                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits              239                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                283                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               283                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              69                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             77                       # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits                41                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits                 41                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                41                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses              70                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses             76                       # number of WriteReq MSHR misses
 system.cpu.dcache.demand_mshr_misses              146                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses             146                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      2422500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      2761000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      5183500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      5183500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency      2463000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency      2688500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency      5151500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency      5151500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.042937                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.082441                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.057458                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.057458                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35108.695652                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35857.142857                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35503.424658                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35503.424658                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.045812                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.081370                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.059301                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.059301                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35185.714286                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency        35375                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35284.246575                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35284.246575                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               178.614114                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               173.809724                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                   364                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.005495                       # Average number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   365                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.005479                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           178.614114                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.005451                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           173.809724                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.005304                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits                     2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 365                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                77                       # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses                 366                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses                76                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses                  442                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses                 442                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      12494500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      2654000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       15148500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      15148500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               367                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              77                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_miss_latency      12541000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency      2603000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency       15144000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency      15144000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses               368                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses              76                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses                444                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses               444                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.994550                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.994565                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate          0.995495                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate         0.995495                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34231.506849                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34467.532468                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34272.624434                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34272.624434                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34265.027322                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        34250                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34262.443439                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34262.443439                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -446,24 +445,24 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            365                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           77                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses            366                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses           76                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses             442                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses            442                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     11330000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      2409500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     13739500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     13739500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency     11369000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency      2368500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency     13737500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency     13737500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.994550                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.994565                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate     0.995495                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate     0.995495                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31041.095890                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31292.207792                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31084.841629                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31084.841629                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31062.841530                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31164.473684                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31080.316742                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31080.316742                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions