integration/soc: add add_uartbone method (to add a UARTBone aka UART Wishbone bridge).

diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
index e6315016da7e05f30b3cc863407e92e07866bfc9..07fdac3056f0f76bd892bc9e0024f3a2345e6173 100644 (file)
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@@ -239,11 +239,13 @@ class UART(Module, AutoCSR, UARTInterface):
             self.ev.rx.trigger.eq(~rx_fifo.source.valid)
         ]
 
-class UARTWishboneBridge(WishboneStreamingBridge):
+class UARTBone(WishboneStreamingBridge):
     def __init__(self, pads, clk_freq, baudrate=115200):
         self.submodules.phy = RS232PHY(pads, clk_freq, baudrate)
         WishboneStreamingBridge.__init__(self, self.phy, clk_freq)
 
+class UARTWishboneBridge(UARTBone): pass
+
 # UART Multiplexer ---------------------------------------------------------------------------------
 
 class UARTMultiplexer(Module):

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 8d51076259f3347eca5ba4ecb5cb2eec4b3c5ba7..d45b32fddaa769b5b547ede6959864cfe3d7b05e 100644 (file)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -926,13 +926,9 @@ class LiteXSoC(SoC):
             if name == "stub":
                 self.comb += self.uart.sink.ready.eq(1)
 
-        # Bridge
-        elif name in ["bridge"]:
-            self.submodules.uart = uart.UARTWishboneBridge(
-                pads     = self.platform.request("serial"),
-                clk_freq = self.sys_clk_freq,
-                baudrate = baudrate)
-            self.bus.add_master(name="uart_bridge", master=self.uart.wishbone)
+        # UARTBone / Bridge
+        elif name in ["uartbone", "bridge"]:
+            self.add_uartbone(baudrate=baudrate)
 
         # Crossover
         elif name in ["crossover"]:
@@ -986,6 +982,15 @@ class LiteXSoC(SoC):
         else:
             self.add_constant("UART_POLLING")
 
+    # Add UARTbone ---------------------------------------------------------------------------------
+    def add_uartbone(self, name="serial", baudrate=115200):
+        from litex.soc.cores import uart
+        self.submodules.uartbone = uart.UARTBone(
+            pads     = self.platform.request(name),
+            clk_freq = self.sys_clk_freq,
+            baudrate = baudrate)
+        self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)
+
     # Add SDRAM ------------------------------------------------------------------------------------
     def add_sdram(self, name, phy, module, origin, size=None,
         l2_cache_size           = 8192,