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* mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
authorDavid Ung <davidu@mips.com>
Thu, 26 Jan 2006 15:14:57 +0000 (15:14 +0000)
committerDavid Ung <davidu@mips.com>
Thu, 26 Jan 2006 15:14:57 +0000 (15:14 +0000)
ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.

opcodes/ChangeLog patch | blob | history
opcodes/mips-opc.c patch | blob | history

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0566289367cbfa48d4a2bf0366e9b2c0a6cd7e20..27ca4c4e893919b966dfd55fe51e3f94344bdba7 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2006-01-26  David Ung  <davidu@mips.com>
+
+       * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
+       ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
+       floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
+       nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
+       rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
+
 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 
        * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 20512123e2a6c100c6793d6984d8118f9548219a..42da7485c0eca654ffe4a8e59a4f23c1a2910899 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -169,7 +169,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
    instruction name anyhow.  */
 /* name,    args,      match,      mask,       pinfo,                  pinfo2,         membership */
 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                  0,              I4|I32|G3       },
-{"prefx",   "h,t(b)",  0x4c00000f, 0xfc0007ff, RD_b|RD_t,              0,              I4      },
+{"prefx",   "h,t(b)",  0x4c00000f, 0xfc0007ff, RD_b|RD_t,              0,              I4|I33  },
 {"nop",     "",         0x00000000, 0xffffffff, 0,                     INSN2_ALIAS,    I1      }, /* sll */
 {"ssnop",   "",         0x00000040, 0xffffffff, 0,                     INSN2_ALIAS,    I32|N55 }, /* sll */
 {"ehb",     "",         0x000000c0, 0xffffffff, 0,                     INSN2_ALIAS,    I33     }, /* sll */
@@ -460,9 +460,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cabs.un.ps", "M,S,T",        0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
 {"cabs.un.s",  "M,S,T",        0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
 {"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,                  0,              I3|I32|T3},
-{"ceil.l.d", "D,S",    0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3      },
-{"ceil.l.s", "D,S",    0x4600000a, 0xffff003f, WR_D|RD_S|FP_S,         0,              I3      },
-{"ceil.w.d", "D,S",    0x4620000e, 0xffff003f, WR_D|RD_S|FP_D,         0,              I2      },
+{"ceil.l.d", "D,S",    0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
+{"ceil.l.s", "D,S",    0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
+{"ceil.w.d", "D,S",    0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
 {"ceil.w.s", "D,S",    0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
 {"cfc0",    "t,G",     0x40400000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
 {"cfc1",    "t,G",     0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
@@ -482,20 +482,20 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cttc1",   "t,g",     0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
 {"cttc1",   "t,S",     0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
 {"cttc2",   "t,g",     0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,    0,              MT32    },
-{"cvt.d.l", "D,S",     0x46a00021, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3      },
-{"cvt.d.s", "D,S",     0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S,    0,              I1      },
-{"cvt.d.w", "D,S",     0x46800021, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
-{"cvt.l.d", "D,S",     0x46200025, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3      },
-{"cvt.l.s", "D,S",     0x46000025, 0xffff003f, WR_D|RD_S|FP_S,         0,              I3      },
-{"cvt.s.l", "D,S",     0x46a00020, 0xffff003f, WR_D|RD_S|FP_S,         0,              I3      },
+{"cvt.d.l", "D,S",     0x46a00021, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
+{"cvt.d.s", "D,S",     0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
+{"cvt.d.w", "D,S",     0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
+{"cvt.l.d", "D,S",     0x46200025, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
+{"cvt.l.s", "D,S",     0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_S,    0,              I3|I33  },
+{"cvt.s.l", "D,S",     0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_S,    0,              I3|I33  },
 {"cvt.s.d", "D,S",     0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
 {"cvt.s.w", "D,S",     0x46800020, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
 {"cvt.s.pl","D,S",     0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5      },
 {"cvt.s.pu","D,S",     0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5      },
-{"cvt.w.d", "D,S",     0x46200024, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
+{"cvt.w.d", "D,S",     0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
 {"cvt.w.s", "D,S",     0x46000024, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
 {"cvt.ps.pw", "D,S",   0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
-{"cvt.ps.s","D,V,T",   0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5      },
+{"cvt.ps.s","D,V,T",   0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0,            I5      },
 {"cvt.pw.ps", "D,S",   0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
 {"dabs",    "d,v",     0,    (int) M_DABS,     INSN_MACRO,             0,              I3      },
 {"dadd",    "d,v,t",   0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
@@ -567,10 +567,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dmtc0",   "t,G",     0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I3      },
 {"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I64     },
 {"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I64     },
-{"dmfc1",   "t,S",     0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I3      },
-{"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,             I3      },
-{"dmtc1",   "t,S",     0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I3      },
-{"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,             I3      },
+{"dmfc1",   "t,S",     0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3      },
+{"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,             I3      },
+{"dmtc1",   "t,S",     0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3      },
+{"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,             I3      },
 /* dmfc2 is at the bottom of the table.  */
 /* dmtc2 is at the bottom of the table.  */
 {"dmfc3",   "t,G",      0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,        0,              I3      },
@@ -638,9 +638,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"evpe",    "",                0x41600021, 0xffffffff, TRAP,                   0,              MT32    },
 {"evpe",    "t",       0x41600021, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
 {"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,                    0,              I33     },
-{"floor.l.d", "D,S",   0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3      },
-{"floor.l.s", "D,S",   0x4600000b, 0xffff003f, WR_D|RD_S|FP_S,         0,              I3      },
-{"floor.w.d", "D,S",   0x4620000f, 0xffff003f, WR_D|RD_S|FP_D,         0,              I2      },
+{"floor.l.d", "D,S",   0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
+{"floor.l.s", "D,S",   0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_S,    0,              I3|I33  },
+{"floor.w.d", "D,S",   0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
 {"floor.w.s", "D,S",   0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
 {"flushi",  "",                0xbc010000, 0xffffffff, 0,                      0,              L1      },
 {"flushd",  "",                0xbc020000, 0xffffffff, 0,                      0,              L1      },
@@ -695,7 +695,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ldl",            "t,A(b)",   0,    (int) M_LDL_AB,   INSN_MACRO,             0,              I3      },
 {"ldr",            "t,o(b)",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
 {"ldr",     "t,A(b)",  0,    (int) M_LDR_AB,   INSN_MACRO,             0,              I3      },
-{"ldxc1",   "D,t(b)",  0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,     0,              I4      },
+{"ldxc1",   "D,t(b)",  0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4|I33  },
 {"lh",      "t,o(b)",  0x84000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
 {"lh",      "t,A(b)",  0,    (int) M_LH_AB,    INSN_MACRO,             0,              I1      },
 {"lhu",     "t,o(b)",  0x94000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
@@ -736,7 +736,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"fork",    "d,s,t",   0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t,    0,              MT32    },
 {"lwu",     "t,o(b)",  0x9c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3      },
 {"lwu",     "t,A(b)",  0,    (int) M_LWU_AB,   INSN_MACRO,             0,              I3      },
-{"lwxc1",   "D,t(b)",  0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,     0,              I4      },
+{"lwxc1",   "D,t(b)",  0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4|I33  },
 {"macc",    "d,s,t",   0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
 {"macc",    "d,s,t",   0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
 {"maccs",   "d,s,t",   0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
@@ -751,8 +751,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"maccus",  "d,s,t",   0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
 {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,             P3      },
 {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,             P3      },
-{"madd.d",  "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I4      },
-{"madd.s",  "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,         I4      },
+{"madd.d",  "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I4|I33  },
+{"madd.s",  "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,         I4|I33  },
 {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I5      },
 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,                L1 },
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,                I32|N55},
@@ -793,8 +793,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I32     },
 {"mfc1",    "t,S",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
 {"mfc1",    "t,G",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
-{"mfhc1",   "t,S",     0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I33     },
-{"mfhc1",   "t,G",     0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I33     },
+{"mfhc1",   "t,S",     0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
+{"mfhc1",   "t,G",     0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
 /* mfc2 is at the bottom of the table.  */
 /* mfhc2 is at the bottom of the table.  */
 {"mfc3",    "t,G",     0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1      },
@@ -812,7 +812,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mov.d",   "D,S",     0x46200006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
 {"mov.s",   "D,S",     0x46000006, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
 {"mov.ps",  "D,S",     0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5      },
-{"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, 0,          I4|I32},
+{"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,          I4|I32  },
 {"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             I4|I32  },
 {"movf.l",  "D,S,N",   0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
 {"movf.l",  "X,Y,N",   0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
@@ -825,7 +825,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"movn.l",  "X,Y,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             MX|SB1  },
 {"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,             I4|I32  },
 {"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             I5      },
-{"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC,        0,             I4|I32  },
+{"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,          I4|I32  },
 {"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             I4|I32  },
 {"movt.l",  "D,S,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             MX|SB1  },
 {"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             MX|SB1  },
@@ -844,8 +844,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msachiu", "d,s,t",   0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
 /* move is at the top of the table.  */
 {"msgn.qh", "X,Y,Q",   0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
-{"msub.d",  "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4      },
-{"msub.s",  "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4      },
+{"msub.d",  "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
+{"msub.s",  "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
 {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5      },
 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,     0,              L1      },
 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,             I32|N55 },
@@ -858,8 +858,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I32     },
 {"mtc1",    "t,S",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
 {"mtc1",    "t,G",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
-{"mthc1",   "t,S",     0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I33     },
-{"mthc1",   "t,G",     0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I33     },
+{"mthc1",   "t,S",     0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
+{"mthc1",   "t,G",     0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
 /* mtc2 is at the bottom of the table.  */
 /* mthc2 is at the bottom of the table.  */
 {"mtc3",    "t,G",     0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I1      },
@@ -940,11 +940,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"neg.d",   "D,V",     0x46200007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
 {"neg.s",   "D,V",     0x46000007, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
 {"neg.ps",  "D,V",     0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5      },
-{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4      },
-{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4      },
+{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
+{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
 {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5      },
-{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4      },
-{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4      },
+{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
+{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
 {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5      },
 /* nop is at the start of the table.  */
 {"nor",     "d,v,t",   0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
@@ -990,9 +990,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"racm.ob", "X",       0x7900003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
 {"racm.ob", "D",       0x4900003f, 0xfffff83f, WR_D,                   0,              N54     },
 {"racm.qh", "X",       0x7920003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
-{"recip.d", "D,S",     0x46200015, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4      },
+{"recip.d", "D,S",     0x46200015, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4|I33  },
 {"recip.ps","D,S",     0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
-{"recip.s", "D,S",     0x46000015, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4      },
+{"recip.s", "D,S",     0x46000015, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4|I33  },
 {"recip1.d",  "D,S",   0x4620001d, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
 {"recip1.ps", "D,S",   0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
 {"recip1.s",  "D,S",   0x4600001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
@@ -1025,13 +1025,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"rotr",    "d,v,t",   0,    (int) M_ROR,      INSN_MACRO,             0,              I33     },
 {"rotr",    "d,v,I",   0,    (int) M_ROR_I,    INSN_MACRO,             0,              I33     },
 {"rotrv",   "d,t,s",   0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              I33     },
-{"round.l.d", "D,S",   0x46200008, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3      },
-{"round.l.s", "D,S",   0x46000008, 0xffff003f, WR_D|RD_S|FP_S,         0,              I3      },
-{"round.w.d", "D,S",   0x4620000c, 0xffff003f, WR_D|RD_S|FP_D,         0,              I2      },
+{"round.l.d", "D,S",   0x46200008, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
+{"round.l.s", "D,S",   0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3      },
+{"round.w.d", "D,S",   0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
 {"round.w.s", "D,S",   0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
-{"rsqrt.d", "D,S",     0x46200016, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4      },
+{"rsqrt.d", "D,S",     0x46200016, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4|I33  },
 {"rsqrt.ps","D,S",     0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
-{"rsqrt.s", "D,S",     0x46000016, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4      },
+{"rsqrt.s", "D,S",     0x46000016, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4|I33  },
 {"rsqrt1.d",  "D,S",   0x4620001e, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
 {"rsqrt1.ps", "D,S",   0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
 {"rsqrt1.s",  "D,S",   0x4600001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
@@ -1071,7 +1071,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sdl",     "t,A(b)",  0,    (int) M_SDL_AB,   INSN_MACRO,             0,              I3      },
 {"sdr",     "t,o(b)",  0xb4000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
 {"sdr",     "t,A(b)",  0,    (int) M_SDR_AB,   INSN_MACRO,             0,              I3      },
-{"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b,     0,              I4      },
+{"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D,        0,              I4|I33  },
 {"seb",     "d,w",     0x7c000420, 0xffe007ff, WR_d|RD_t,              0,              I33     },
 {"seh",     "d,w",     0x7c000620, 0xffe007ff, WR_d|RD_t,              0,              I33     },
 {"selsl",   "d,v,t",   0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              L1      },
@@ -1177,7 +1177,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"swr",     "t,A(b)",  0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I1      },
 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000,        RD_t|RD_b,              0,              I2      }, /* same */
 {"invalidate", "t,A(b)",0,    (int) M_SWR_AB,  INSN_MACRO,             0,              I2      }, /* as swr */
-{"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b,     0,              I4      },
+{"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S,        0,              I4|I33  },
 {"sync",    "",                0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2|G1   },
 {"sync.p",  "",                0x0000040f, 0xffffffff, INSN_SYNC,              0,              I2      },
 {"sync.l",  "",                0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2      },
@@ -1218,10 +1218,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"tne",     "s,t,q",   0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
 {"tne",     "s,j",     0x040e0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tnei */
 {"tne",     "s,I",     0,    (int) M_TNE_I,    INSN_MACRO,             0,              I2      },
-{"trunc.l.d", "D,S",   0x46200009, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3      },
-{"trunc.l.s", "D,S",   0x46000009, 0xffff003f, WR_D|RD_S|FP_S,         0,              I3      },
-{"trunc.w.d", "D,S",   0x4620000d, 0xffff003f, WR_D|RD_S|FP_D,         0,              I2      },
-{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D,         0,              I2      },
+{"trunc.l.d", "D,S",   0x46200009, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
+{"trunc.l.s", "D,S",   0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
+{"trunc.w.d", "D,S",   0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
+{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
 {"trunc.w.d", "D,S,t", 0,    (int) M_TRUNCWD,  INSN_MACRO,             0,              I1      },
 {"trunc.w.s", "D,S",   0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },