hyp = 1;
tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
return;
+ case MISCREG_TLBIIPAS2L:
+ case MISCREG_TLBIIPAS2LIS:
+ // mcr tlbiipas2l(is) is invalidating all matching entries
+ // regardless of the level of lookup, since in gem5 we cache
+ // in the tlb the last level of lookup only.
+ case MISCREG_TLBIIPAS2:
+ case MISCREG_TLBIIPAS2IS:
+ assert32(tc);
+ target_el = 1; // EL 0 and 1 are handled together
+ scr = readMiscReg(MISCREG_SCR, tc);
+ secure_lookup = haveSecurity && !scr.ns;
+ tlbiIPA(tc, newVal, secure_lookup, target_el);
+ return;
// TLBI by address and asid, EL0&1, instruction side only
case MISCREG_ITLBIMVA:
assert32(tc);
target_el = 1; // EL 0 and 1 are handled together
scr = readMiscReg(MISCREG_SCR, tc);
secure_lookup = haveSecurity && !scr.ns;
- sys = tc->getSystemPtr();
- for (x = 0; x < sys->numContexts(); x++) {
- oc = sys->getThreadContext(x);
- Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12;
- getITBPtr(oc)->flushIpaVmid(ipa,
- secure_lookup, false, target_el);
- getDTBPtr(oc)->flushIpaVmid(ipa,
- secure_lookup, false, target_el);
-
- CheckerCPU *checker = oc->getCheckerCpuPtr();
- if (checker) {
- getITBPtr(checker)->flushIpaVmid(ipa,
- secure_lookup, false, target_el);
- getDTBPtr(checker)->flushIpaVmid(ipa,
- secure_lookup, false, target_el);
- }
- }
+ tlbiIPA(tc, newVal, secure_lookup, target_el);
return;
case MISCREG_ACTLR:
warn("Not doing anything for write of miscreg ACTLR\n");
}
}
+void
+ISA::tlbiIPA(ThreadContext *tc, MiscReg newVal, bool secure_lookup,
+ uint8_t target_el)
+{
+ System *sys = tc->getSystemPtr();
+ for (auto x = 0; x < sys->numContexts(); x++) {
+ tc = sys->getThreadContext(x);
+ Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12;
+ getITBPtr(tc)->flushIpaVmid(ipa,
+ secure_lookup, false, target_el);
+ getDTBPtr(tc)->flushIpaVmid(ipa,
+ secure_lookup, false, target_el);
+
+ CheckerCPU *checker = tc->getCheckerCpuPtr();
+ if (checker) {
+ getITBPtr(checker)->flushIpaVmid(ipa,
+ secure_lookup, false, target_el);
+ getDTBPtr(checker)->flushIpaVmid(ipa,
+ secure_lookup, false, target_el);
+ }
+ }
+}
+
BaseISADevice &
ISA::getGenericTimer(ThreadContext *tc)
{
break;
}
} else if (opc1 == 4) {
- if (crm == 3) {
+ if (crm == 0) {
+ switch (opc2) {
+ case 1:
+ return MISCREG_TLBIIPAS2IS;
+ case 5:
+ return MISCREG_TLBIIPAS2LIS;
+ }
+ } else if (crm == 3) {
switch (opc2) {
case 0:
return MISCREG_TLBIALLHIS;
case 5:
return MISCREG_TLBIMVALHIS;
}
+ } else if (crm == 4) {
+ switch (opc2) {
+ case 1:
+ return MISCREG_TLBIIPAS2;
+ case 5:
+ return MISCREG_TLBIIPAS2L;
+ }
} else if (crm == 7) {
switch (opc2) {
case 0:
InitReg(MISCREG_TLBIMVAAL)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBIIPAS2IS)
- .unimplemented()
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBIIPAS2LIS)
- .unimplemented()
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBIALLHIS)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBIMVALHIS)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBIIPAS2)
- .unimplemented()
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBIIPAS2L)
- .unimplemented()
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBIALLH)
.monNonSecureWrite().hypWrite();