--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
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+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
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+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
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+machine_type=VExpress_EMM64
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+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
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+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+reset_addr_64=0
+symbolfile=
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+
+[system.bridge]
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+master=system.iobus.slave[0]
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+
+[system.cf0]
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+
+[system.cf0.image]
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+
+[system.cf0.image.child]
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+
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+
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+
+[system.cpu0.dcache]
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+
+[system.cpu0.dcache.tags]
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+[system.cpu0.dstage2_mmu.stage2_tlb]
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+
+[system.cpu0.dstage2_mmu.stage2_tlb.walker]
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+[system.cpu0.icache]
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+
+[system.cpu0.icache.tags]
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+
+[system.cpu0.interrupts]
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+[system.cpu0.isa]
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+[system.cpu0.istage2_mmu]
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+[system.cpu0.istage2_mmu.stage2_tlb]
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+[system.cpu0.istage2_mmu.stage2_tlb.walker]
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+[system.cpu0.l2cache]
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+
+[system.cpu0.l2cache.prefetcher]
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+
+[system.cpu0.l2cache.tags]
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+[system.cpu0.toL2Bus]
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+
+[system.cpu0.tracer]
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+
+[system.cpu1]
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+
+[system.cpu1.dcache]
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+
+[system.cpu1.dcache.tags]
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+[system.cpu1.dstage2_mmu]
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+[system.cpu1.dstage2_mmu.stage2_tlb]
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+[system.cpu1.dstage2_mmu.stage2_tlb.walker]
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+[system.cpu1.dtb]
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+[system.cpu1.dtb.walker]
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+[system.cpu1.icache]
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+[system.cpu1.icache.tags]
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+[system.cpu1.interrupts]
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+[system.cpu1.isa]
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+[system.cpu1.istage2_mmu]
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+[system.cpu1.istage2_mmu.stage2_tlb]
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+
+[system.cpu1.istage2_mmu.stage2_tlb.walker]
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+[system.cpu1.itb]
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+[system.cpu1.itb.walker]
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+
+[system.cpu1.l2cache]
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+
+[system.cpu1.l2cache.prefetcher]
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+[system.cpu1.l2cache.tags]
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+[system.cpu1.toL2Bus]
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+master=system.cpu1.l2cache.cpu_side
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
+
+[system.cpu1.tracer]
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+[system.cpu_clk_domain]
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+
+[system.dvfs_handler]
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+
+[system.intrctrl]
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+
+[system.iobus]
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+width=16
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.l2c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.l2c.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+response_latency=2
+snoop_filter=Null
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2415919103
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.l2c.cpu_side
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:01:47
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu0.isa: ISA system set to: 0x52fab00 0x52fab00
+ 0: system.cpu1.isa: ISA system set to: 0x52fab00 0x52fab00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 47256535568000 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 47.216814 # Number of seconds simulated
+sim_ticks 47216814145000 # Number of ticks simulated
+final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1225013 # Simulator instruction rate (inst/s)
+host_op_rate 1441119 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 59296512316 # Simulator tick rate (ticks/s)
+host_mem_usage 723320 # Number of bytes of host memory used
+host_seconds 796.28 # Real time elapsed on the host
+sim_insts 975457230 # Number of instructions simulated
+sim_ops 1147538415 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu0.dtb.walker 154048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 128704 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 3911220 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 35234584 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 222912 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 221184 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2638152 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 38475968 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 412928 # Number of bytes read from this memory
+system.physmem.bytes_read::total 81399700 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 3911220 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 2638152 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 6549372 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 100563072 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
+system.physmem.bytes_written::total 100583888 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 2407 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2011 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 101520 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 550562 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 3483 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 3456 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 41328 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 601205 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6452 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1312424 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1571298 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1573901 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 3263 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 2726 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 82835 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 746230 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 4721 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 4684 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 55873 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 814879 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8745 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1723956 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 82835 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 55873 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 138708 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2129815 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 441 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2130256 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2129815 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 3263 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 82835 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 746670 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 4721 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 4684 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 55873 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 814879 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8745 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3854211 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.walks 125229 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 92662773 # DTB read hits
+system.cpu0.dtb.read_misses 88786 # DTB read misses
+system.cpu0.dtb.write_hits 85694958 # DTB write hits
+system.cpu0.dtb.write_misses 36443 # DTB write misses
+system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 92751559 # DTB read accesses
+system.cpu0.dtb.write_accesses 85731401 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 178357731 # DTB hits
+system.cpu0.dtb.misses 125229 # DTB misses
+system.cpu0.dtb.accesses 178482960 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.walks 61377 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 497696393 # ITB inst hits
+system.cpu0.itb.inst_misses 61377 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 497757770 # ITB inst accesses
+system.cpu0.itb.hits 497696393 # DTB hits
+system.cpu0.itb.misses 61377 # DTB misses
+system.cpu0.itb.accesses 497757770 # DTB accesses
+system.cpu0.numCycles 94433641544 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.committedInsts 497466384 # Number of instructions committed
+system.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses
+system.cpu0.num_func_calls 28869117 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 536103359 # number of integer instructions
+system.cpu0.num_fp_insts 526132 # number of float instructions
+system.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written
+system.cpu0.num_mem_refs 178459396 # number of memory refs
+system.cpu0.num_load_insts 92737001 # Number of load instructions
+system.cpu0.num_store_insts 85722395 # Number of store instructions
+system.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles
+system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles
+system.cpu0.Branches 111287587 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
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+system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction
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+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction
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+system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction
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+system.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction
+system.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu0.op_class::total 585300003 # Class of executed instruction
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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+system.cpu0.l2cache.UpgradeReq_misses::total 128143 # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158369 # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total 158369 # number of SCUpgradeReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709409 # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total 709409 # number of ReadExReq misses
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+system.cpu0.l2cache.demand_misses::cpu0.data 1966666 # number of demand (read+write) misses
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+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11316 # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8593 # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst 568201 # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data 1966666 # number of overall misses
+system.cpu0.l2cache.overall_misses::total 2554776 # number of overall misses
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 280666 # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 150346 # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5539598 # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4201332 # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total 10171942 # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks 4469723 # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total 4469723 # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 831335 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.WriteInvalidateReq_accesses::total 831335 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131664 # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total 131664 # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158369 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total 158369 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344223 # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total 1344223 # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 280666 # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 150346 # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data 5545555 # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total 11516165 # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 280666 # number of overall (read+write) accesses
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+system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data 5545555 # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total 11516165 # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057155 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102571 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.299252 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total 0.181417 # miss rate for ReadReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.732073 # miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.732073 # miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973258 # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973258 # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527747 # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527747 # miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.057155 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102571 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354638 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total 0.221843 # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.057155 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102571 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354638 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total 0.221843 # miss rate for overall accesses
+system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu0.l2cache.writebacks::writebacks 1573452 # number of writebacks
+system.cpu0.l2cache.writebacks::total 1573452 # number of writebacks
+system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.toL2Bus.trans_dist::ReadReq 10363949 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 10363949 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 32448 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 32448 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 4469723 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 831335 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 831335 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 131664 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158369 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 290033 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1344223 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1344223 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11165446 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17933523 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 30193699 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 694376897 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 1053462589 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 3346385 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 20385280 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 3.155096 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.361996 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 17223609 84.49% 84.49% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 3161671 15.51% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 20385280 # Request fanout histogram
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.walks 144041 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 90153061 # DTB read hits
+system.cpu1.dtb.read_misses 111753 # DTB read misses
+system.cpu1.dtb.write_hits 81132787 # DTB write hits
+system.cpu1.dtb.write_misses 32288 # DTB write misses
+system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 90264814 # DTB read accesses
+system.cpu1.dtb.write_accesses 81165075 # DTB write accesses
+system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dtb.hits 171285848 # DTB hits
+system.cpu1.dtb.misses 144041 # DTB misses
+system.cpu1.dtb.accesses 171429889 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.walks 60885 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 478248118 # ITB inst hits
+system.cpu1.itb.inst_misses 60885 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.write_hits 0 # DTB write hits
+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 478309003 # ITB inst accesses
+system.cpu1.itb.hits 478248118 # DTB hits
+system.cpu1.itb.misses 60885 # DTB misses
+system.cpu1.itb.accesses 478309003 # DTB accesses
+system.cpu1.numCycles 94433634550 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.committedInsts 477990846 # Number of instructions committed
+system.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses
+system.cpu1.num_func_calls 28237407 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 516282159 # number of integer instructions
+system.cpu1.num_fp_insts 374678 # number of float instructions
+system.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written
+system.cpu1.num_mem_refs 171406825 # number of memory refs
+system.cpu1.num_load_insts 90251973 # Number of load instructions
+system.cpu1.num_store_insts 81154852 # Number of store instructions
+system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles
+system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles
+system.cpu1.Branches 106497601 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction
+system.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction
+system.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
+system.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction
+system.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::total 562879339 # Class of executed instruction
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed
+system.cpu1.dcache.tags.replacements 5945049 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use
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+system.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor
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+system.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits
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+system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits
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+system.cpu1.dcache.WriteInvalidateReq_hits::total 63447 # number of WriteInvalidateReq hits
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+system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits
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+system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 427052 # number of WriteInvalidateReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::total 427052 # number of WriteInvalidateReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158842 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 158842 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 4811362 # number of demand (read+write) misses
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+system.cpu1.dcache.overall_misses::total 5603713 # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses)
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+system.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 490499 # number of WriteInvalidateReq accesses(hits+misses)
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+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses)
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+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses
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+system.cpu1.dcache.WriteReq_miss_rate::total 0.018525 # miss rate for WriteReq accesses
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+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.870648 # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.870648 # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071947 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071947 # miss rate for StoreCondReq accesses
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+system.cpu1.dcache.overall_miss_rate::total 0.033660 # miss rate for overall accesses
+system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes 0 # number of fast writes performed
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+system.cpu1.dcache.writebacks::writebacks 4030826 # number of writebacks
+system.cpu1.dcache.writebacks::total 4030826 # number of writebacks
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.icache.tags.replacements 4741297 # number of replacements
+system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks.
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+system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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+system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
+system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
+system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
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+system.cpu1.l2cache.tags.sampled_refs 2294953 # Sample count of references to valid blocks.
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+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 68.434503 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 91.707533 # Average occupied blocks per requestor
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+system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5282.581627 # Average occupied blocks per requestor
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+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id
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+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1583 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5963 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4534 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3771 # Occupied blocks per task id
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+system.cpu1.l2cache.ReadReq_hits::total 7741332 # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks 4030826 # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total 4030826 # number of Writeback hits
+system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 161366 # number of WriteInvalidateReq hits
+system.cpu1.l2cache.WriteInvalidateReq_hits::total 161366 # number of WriteInvalidateReq hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3865 # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total 3865 # number of UpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614191 # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total 614191 # number of ReadExReq hits
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+system.cpu1.l2cache.overall_hits::cpu1.inst 4217165 # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data 3672082 # number of overall hits
+system.cpu1.l2cache.overall_hits::total 8355523 # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12489 # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9780 # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.inst 524644 # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.data 1239502 # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total 1786415 # number of ReadReq misses
+system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 265480 # number of WriteInvalidateReq misses
+system.cpu1.l2cache.WriteInvalidateReq_misses::total 265480 # number of WriteInvalidateReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133591 # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total 133591 # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158842 # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total 158842 # number of SCUpgradeReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data 701699 # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total 701699 # number of ReadExReq misses
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+system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9780 # number of demand (read+write) misses
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+system.cpu1.l2cache.demand_misses::cpu1.data 1941201 # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total 2488114 # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12489 # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9780 # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst 524644 # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data 1941201 # number of overall misses
+system.cpu1.l2cache.overall_misses::total 2488114 # number of overall misses
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 337607 # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 150938 # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4741809 # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4297393 # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total 9527747 # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks 4030826 # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total 4030826 # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 426846 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.WriteInvalidateReq_accesses::total 426846 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137456 # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total 137456 # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158842 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total 158842 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 337607 # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 150938 # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total 10843637 # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 337607 # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150938 # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total 10843637 # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.064795 # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.110642 # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288431 # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total 0.187496 # miss rate for ReadReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.621957 # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.621957 # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.971882 # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.971882 # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533250 # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533250 # miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064795 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110642 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345823 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total 0.229454 # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064795 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110642 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345823 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total 0.229454 # miss rate for overall accesses
+system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu1.l2cache.writebacks::writebacks 1183487 # number of writebacks
+system.cpu1.l2cache.writebacks::total 1183487 # number of writebacks
+system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.toL2Bus.trans_dist::ReadReq 9645413 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 4030826 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 426846 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 426846 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 137456 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158842 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 296298 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9483878 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16729164 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 27412486 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 644579516 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 952853588 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 3730448 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 19274314 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 3.184989 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.388288 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 15708784 81.50% 81.50% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 3565530 18.50% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 19274314 # Request fanout histogram
+system.iobus.trans_dist::ReadReq 40295 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40295 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136634 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29906 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.replacements 115585 # number of replacements
+system.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1040793 # Number of tag accesses
+system.iocache.tags.data_accesses 1040793 # Number of data accesses
+system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses
+system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8916 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
+system.iocache.overall_misses::realview.ide 8876 # number of overall misses
+system.iocache.overall_misses::total 8916 # number of overall misses
+system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.writebacks::writebacks 106694 # number of writebacks
+system.iocache.writebacks::total 106694 # number of writebacks
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.tags.replacements 1759966 # number of replacements
+system.l2c.tags.tagsinuse 62842.185631 # Cycle average of tags in use
+system.l2c.tags.total_refs 3707512 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 1818705 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 2.038545 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 482634500 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 35219.340736 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 46.907098 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 57.886687 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 3338.956610 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 6965.181537 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 309.496433 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker 430.211698 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 2959.236338 # Average occupied blocks per requestor
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+system.realview.ethernet.totBytes 966 # Total Bytes
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+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq 3713925 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 3713925 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38831 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38831 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 2756939 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 859574 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 859574 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 330257 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 317211 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 647468 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 1357089 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 1357089 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8689428 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7301285 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 15990713 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301218837 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249930820 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 551149657 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 117306 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 9368496 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.012344 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.110415 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 9252852 98.77% 98.77% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 115644 1.23% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 9368496 # Request fanout histogram
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[ 0.000000] Initializing cgroup subsys cpu\r
+[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
+[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
+[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
+[ 0.000000] Memory limited to 256MB\r
+[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
+[ 0.000000] On node 0 totalpages: 65536\r
+[ 0.000000] DMA zone: 896 pages used for memmap\r
+[ 0.000000] DMA zone: 0 pages reserved\r
+[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
+[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
+[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
+[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
+[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
+[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
+[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
+[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
+[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
+[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
+[ 0.000000] Virtual kernel memory layout:\r
+[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
+[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
+[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
+[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
+[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
+[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
+[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
+[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
+[ 0.000000] Preemptible hierarchical RCU implementation.\r
+[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
+[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
+[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
+[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
+[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
+[ 0.000013] Console: colour dummy device 80x25\r
+[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000015] pid_max: default: 32768 minimum: 301\r
+[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000066] hw perfevents: no hardware support available\r
+[ 0.060015] CPU1: Booted secondary processor\r
+[ 1.080050] CPU2: failed to come online\r
+[ 2.100100] CPU3: failed to come online\r
+[ 2.100101] Brought up 2 CPUs\r
+[ 2.100102] SMP: Total of 2 processors activated.\r
+[ 2.100134] devtmpfs: initialized\r
+[ 2.100536] atomic64_test: passed\r
+[ 2.100559] regulator-dummy: no parameters\r
+[ 2.100800] NET: Registered protocol family 16\r
+[ 2.100894] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 2.100898] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 2.100937] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 2.100938] Serial: AMBA PL011 UART driver\r
+[ 2.101059] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 2.101082] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 2.101116] console [ttyAMA0] enabled\r
+[ 2.101154] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 2.101168] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 2.101183] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 2.101195] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 2.140179] 3V3: 3300 mV \r
+[ 2.140202] vgaarb: loaded\r
+[ 2.140232] SCSI subsystem initialized\r
+[ 2.140246] libata version 3.00 loaded.\r
+[ 2.140272] usbcore: registered new interface driver usbfs\r
+[ 2.140279] usbcore: registered new interface driver hub\r
+[ 2.140288] usbcore: registered new device driver usb\r
+[ 2.140300] pps_core: LinuxPPS API ver. 1 registered\r
+[ 2.140301] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 2.140304] PTP clock support registered\r
+[ 2.140381] Switched to clocksource arch_sys_counter\r
+[ 2.141215] NET: Registered protocol family 2\r
+[ 2.141272] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 2.141277] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 2.141282] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 2.141285] TCP: reno registered\r
+[ 2.141286] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.141288] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.141303] NET: Registered protocol family 1\r
+[ 2.141330] RPC: Registered named UNIX socket transport module.\r
+[ 2.141331] RPC: Registered udp transport module.\r
+[ 2.141331] RPC: Registered tcp transport module.\r
+[ 2.141332] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 2.141334] PCI: CLS 0 bytes, default 64\r
+[ 2.141433] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 2.141477] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 2.143024] fuse init (API version 7.23)\r
+[ 2.143091] msgmni has been set to 469\r
+[ 2.143142] io scheduler noop registered\r
+[ 2.143175] io scheduler cfq registered (default)\r
+[ 2.143447] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 2.143448] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 2.143450] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 2.143451] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 2.143453] pci_bus 0000:00: scanning bus\r
+[ 2.143455] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 2.143457] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 2.143460] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.143476] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 2.143477] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 2.143479] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 2.143481] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 2.143482] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 2.143484] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 2.143486] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.143503] pci_bus 0000:00: fixups for bus\r
+[ 2.143505] pci_bus 0000:00: bus scan returning with max=00\r
+[ 2.143506] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 2.143511] pci 0000:00:00.0: fixup irq: got 33\r
+[ 2.143512] pci 0000:00:00.0: assigning IRQ 33\r
+[ 2.143515] pci 0000:00:01.0: fixup irq: got 34\r
+[ 2.143516] pci 0000:00:01.0: assigning IRQ 34\r
+[ 2.143519] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 2.143520] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 2.143522] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 2.143524] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 2.143525] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 2.143527] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 2.143529] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 2.143531] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 2.143891] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 2.144060] ata_piix 0000:00:01.0: version 2.13\r
+[ 2.144062] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 2.144068] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 2.144250] scsi0 : ata_piix\r
+[ 2.144297] scsi1 : ata_piix\r
+[ 2.144314] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 2.144315] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 2.144376] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 2.144377] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 2.144381] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 2.144382] e1000 0000:00:00.0: enabling bus mastering\r
+[ 2.290388] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 2.290389] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 2.290395] ata1.00: configured for UDMA/33\r
+[ 2.290412] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 2.290466] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 2.290469] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 2.290484] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 2.290486] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 2.290493] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 2.290548] sda: sda1\r
+[ 2.290610] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 2.410644] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 2.410646] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 2.410652] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 2.410653] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 2.410661] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 2.410662] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 2.410706] usbcore: registered new interface driver usb-storage\r
+[ 2.410735] mousedev: PS/2 mouse device common for all mice\r
+[ 2.410834] usbcore: registered new interface driver usbhid\r
+[ 2.410835] usbhid: USB HID core driver\r
+[ 2.410850] TCP: cubic registered\r
+[ 2.410852] NET: Registered protocol family 17\r
+\0[ 2.411039] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 2.411050] devtmpfs: mounted\r
+[ 2.411057] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+\0\0\rINIT: \0version 2.88 booting\0\r\r
+\0Starting udev\r
+[ 2.446370] udevd[609]: starting version 182\r
+Starting Bootlog daemon: bootlogd.\r\r
+[ 2.512067] random: dd urandom read with 17 bits of entropy available\r
+Populating dev cache\r\r
+net.ipv4.conf.default.rp_filter = 1\r\r
+net.ipv4.conf.all.rp_filter = 1\r\r
+hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
+Mon Jan 27 08:00:00 UTC 2014\r\r
+hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
+\rINIT: Entering runlevel: 5\r\r\r
+Configuring network interfaces... udhcpc (v1.21.1) started\r\r
+[ 2.610614] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+Sending discover...\r\r
+Sending discover...\r\r
+Sending discover...\r\r
+No lease, forking to background\r\r
+done.\r\r
+Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
+rpcbind: cannot create socket for tcp6\r\r\r
+rpcbind: cannot get uid of '': Success\r\r\r
+done.\r\r
+creating NFS state directory: done\r\r
+starting statd: done\r\r
+Starting auto-serial-console:
\ No newline at end of file
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+eventq_index=0
+flags_addr=469827632
+gic_cpu_addr=738205696
+have_generic_timer=false
+have_large_asid_64=false
+have_lpae=false
+have_security=false
+have_virtualization=false
+highest_el_is_64=false
+init_param=0
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=atomic
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
+clk_domain=system.clk_domain
+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+eventq_index=0
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+eventq_index=0
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
+dtb=system.cpu.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[3]
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=1
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=1
+frontend_latency=2
+response_latency=2
+use_default_range=true
+width=16
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+response_latency=2
+snoop_filter=Null
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2415919103
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:00:57
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-atomic
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu.isa: ISA system set to: 0x54cdb00 0x54cdb00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 51111167186000 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 51.111153 # Number of seconds simulated
+sim_ticks 51111152682000 # Number of ticks simulated
+final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1276359 # Simulator instruction rate (inst/s)
+host_op_rate 1499931 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 66258489115 # Simulator tick rate (ticks/s)
+host_mem_usage 712024 # Number of bytes of host memory used
+host_seconds 771.39 # Real time elapsed on the host
+sim_insts 984570519 # Number of instructions simulated
+sim_ops 1157031967 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 376512 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 5562740 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 74833672 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory
+system.physmem.bytes_read::total 81627068 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 5562740 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 103042944 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
+system.physmem.bytes_written::total 103063524 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 5883 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 127325 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1169289 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1315843 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1610046 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1612619 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 7367 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 108836 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1464136 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1597050 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 108836 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2016056 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2016459 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2016056 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 7367 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 108836 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1464539 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3613509 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.walks 265715 # Table walker walks requested
+system.cpu.dtb.walker.walksLong 265715 # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walkWaitTime::samples 265715 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 265715 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K 204282 89.47% 89.47% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M 24037 10.53% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 228319 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265715 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265715 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228319 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228319 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 494034 # Table walker requests started/completed, data/inst
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 184014035 # DTB read hits
+system.cpu.dtb.read_misses 194198 # DTB read misses
+system.cpu.dtb.write_hits 168232768 # DTB write hits
+system.cpu.dtb.write_misses 71517 # DTB write misses
+system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 82353 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 9303 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 184208233 # DTB read accesses
+system.cpu.dtb.write_accesses 168304285 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 352246803 # DTB hits
+system.cpu.dtb.misses 265715 # DTB misses
+system.cpu.dtb.accesses 352512518 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.walks 126837 # Table walker walks requested
+system.cpu.itb.walker.walksLong 126837 # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walkWaitTime::samples 126837 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0 126837 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 126837 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K 113576 99.02% 99.02% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M 1123 0.98% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 114699 # Table walker page sizes translated
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126837 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 126837 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114699 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 114699 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 241536 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 985047321 # ITB inst hits
+system.cpu.itb.inst_misses 126837 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 58174 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 985174158 # ITB inst accesses
+system.cpu.itb.hits 985047321 # DTB hits
+system.cpu.itb.misses 126837 # DTB misses
+system.cpu.itb.accesses 985174158 # DTB accesses
+system.cpu.numCycles 102222322140 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 984570519 # Number of instructions committed
+system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 880805 # Number of float alu accesses
+system.cpu.num_func_calls 57056367 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 151940834 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1060455466 # number of integer instructions
+system.cpu.num_fp_insts 880805 # number of float instructions
+system.cpu.num_int_register_reads 1564002170 # number of times the integer registers were read
+system.cpu.num_int_register_writes 842444791 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 747920 # number of times the floating registers were written
+system.cpu.num_cc_register_reads 264407058 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 263829403 # number of times the CC registers were written
+system.cpu.num_mem_refs 352465606 # number of memory refs
+system.cpu.num_load_insts 184180431 # Number of load instructions
+system.cpu.num_store_insts 168285175 # Number of store instructions
+system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles
+system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles
+system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.988675 # Percentage of idle cycles
+system.cpu.Branches 220088562 # Number of branches fetched
+system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 802636616 69.33% 69.33% # Class of executed instruction
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+system.cpu.op_class::IntDiv 101759 0.01% 69.54% # Class of executed instruction
+system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
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+system.cpu.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
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+system.cpu.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
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+system.cpu.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
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+system.cpu.op_class::SimdFloatCvt 21 0.00% 69.54% # Class of executed instruction
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+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
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+system.cpu.op_class::MemRead 184180431 15.91% 85.46% # Class of executed instruction
+system.cpu.op_class::MemWrite 168285175 14.54% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 1157666593 # Class of executed instruction
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed
+system.cpu.dcache.tags.replacements 11612141 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 29.345233 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
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+system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
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+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 1421167352 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1421167352 # Number of data accesses
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+system.cpu.dcache.SoftPFReq_hits::total 424020 # number of SoftPFReq hits
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+system.cpu.dcache.LoadLockedReq_misses::total 253721 # number of LoadLockedReq misses
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+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033845 # miss rate for ReadReq accesses
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+system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786673 # miss rate for WriteInvalidateReq accesses
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+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055589 # miss rate for LoadLockedReq accesses
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+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.dcache.writebacks::total 8921315 # number of writebacks
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements 14295641 # number of replacements
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+system.cpu.icache.tags.total_refs 970865862 # Total number of references to valid blocks.
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+system.cpu.l2cache.tags.total_refs 29983424 # Total number of references to valid blocks.
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+system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
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+system.cpu.l2cache.Writeback_hits::writebacks 8921315 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 8921315 # number of Writeback hits
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+system.cpu.l2cache.UpgradeReq_hits::total 11223 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 1692610 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 1692610 # number of ReadExReq hits
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+system.cpu.l2cache.ReadReq_misses::cpu.data 343966 # number of ReadReq misses
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+system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 551016 # number of WriteInvalidateReq misses
+system.cpu.l2cache.WriteInvalidateReq_misses::total 551016 # number of WriteInvalidateReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 39917 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 39917 # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 826507 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 826507 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 6443 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker 5883 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst 84237 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 1170473 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 1267036 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 6443 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker 5883 # number of overall misses
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+system.cpu.l2cache.overall_misses::cpu.data 1170473 # number of overall misses
+system.cpu.l2cache.overall_misses::total 1267036 # number of overall misses
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 513055 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261506 # number of ReadReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_accesses::cpu.data 7848198 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 22918917 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 8921315 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 8921315 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1245349 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.l2cache.WriteInvalidateReq_accesses::total 1245349 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51140 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 51140 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 2519117 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 513055 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 261506 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 14296158 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 10367315 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 25438034 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 513055 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 261506 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 14296158 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 10367315 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 25438034 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012558 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022497 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005892 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043827 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.019221 # miss rate for ReadReq accesses
+system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.442459 # miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.442459 # miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328094 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022497 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005892 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.112900 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.049809 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022497 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005892 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.112900 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.049809 # miss rate for overall accesses
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks 1503415 # number of writebacks
+system.cpu.l2cache.writebacks::total 1503415 # number of writebacks
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 23372119 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28678566 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32383245 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 63363979 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 116338 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 36147883 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.003196 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.056441 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 36032362 99.68% 99.68% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram
+system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29851 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.replacements 115463 # number of replacements
+system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1039686 # Number of tag accesses
+system.iocache.tags.data_accesses 1039686 # Number of data accesses
+system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses
+system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8857 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
+system.iocache.overall_misses::realview.ide 8817 # number of overall misses
+system.iocache.overall_misses::total 8857 # number of overall misses
+system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.writebacks::writebacks 106631 # number of writebacks
+system.iocache.writebacks::total 106631 # number of writebacks
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 526062 # Transaction distribution
+system.membus.trans_dist::ReadResp 526062 # Transaction distribution
+system.membus.trans_dist::WriteReq 33606 # Transaction distribution
+system.membus.trans_dist::WriteResp 33606 # Transaction distribution
+system.membus.trans_dist::Writeback 1610046 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 657675 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 657675 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution
+system.membus.trans_dist::ReadExReq 825948 # Transaction distribution
+system.membus.trans_dist::ReadExResp 825948 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5310733 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5439925 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5777598 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212730912 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212899962 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 3583537 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3583537 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 3583537 # Request fanout histogram
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[ 0.000000] Initializing cgroup subsys cpu\r
+[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
+[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
+[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
+[ 0.000000] Memory limited to 256MB\r
+[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
+[ 0.000000] On node 0 totalpages: 65536\r
+[ 0.000000] DMA zone: 896 pages used for memmap\r
+[ 0.000000] DMA zone: 0 pages reserved\r
+[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
+[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
+[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
+[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
+[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
+[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
+[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
+[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
+[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
+[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
+[ 0.000000] Virtual kernel memory layout:\r
+[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
+[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
+[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
+[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
+[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
+[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
+[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
+[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
+[ 0.000000] Preemptible hierarchical RCU implementation.\r
+[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
+[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
+[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
+[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
+[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
+[ 0.000013] Console: colour dummy device 80x25\r
+[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000015] pid_max: default: 32768 minimum: 301\r
+[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000066] hw perfevents: no hardware support available\r
+[ 1.060049] CPU1: failed to come online\r
+[ 2.080098] CPU2: failed to come online\r
+[ 3.100148] CPU3: failed to come online\r
+[ 3.100150] Brought up 1 CPUs\r
+[ 3.100151] SMP: Total of 1 processors activated.\r
+[ 3.100177] devtmpfs: initialized\r
+[ 3.100579] atomic64_test: passed\r
+[ 3.100603] regulator-dummy: no parameters\r
+[ 3.100844] NET: Registered protocol family 16\r
+[ 3.100938] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 3.100941] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 3.100980] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 3.100981] Serial: AMBA PL011 UART driver\r
+[ 3.101103] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 3.101125] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 3.101160] console [ttyAMA0] enabled\r
+[ 3.101194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 3.101208] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 3.101222] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 3.101235] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 3.130356] 3V3: 3300 mV \r
+[ 3.130377] vgaarb: loaded\r
+[ 3.130406] SCSI subsystem initialized\r
+[ 3.130425] libata version 3.00 loaded.\r
+[ 3.130450] usbcore: registered new interface driver usbfs\r
+[ 3.130457] usbcore: registered new interface driver hub\r
+[ 3.130471] usbcore: registered new device driver usb\r
+[ 3.130482] pps_core: LinuxPPS API ver. 1 registered\r
+[ 3.130483] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 3.130487] PTP clock support registered\r
+[ 3.130559] Switched to clocksource arch_sys_counter\r
+[ 3.131204] NET: Registered protocol family 2\r
+[ 3.131250] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 3.131255] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 3.131259] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 3.131263] TCP: reno registered\r
+[ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.131281] NET: Registered protocol family 1\r
+[ 3.131310] RPC: Registered named UNIX socket transport module.\r
+[ 3.131311] RPC: Registered udp transport module.\r
+[ 3.131312] RPC: Registered tcp transport module.\r
+[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 3.131315] PCI: CLS 0 bytes, default 64\r
+[ 3.131413] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 3.131456] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 3.132687] fuse init (API version 7.23)\r
+[ 3.132738] msgmni has been set to 469\r
+[ 3.133992] io scheduler noop registered\r
+[ 3.134024] io scheduler cfq registered (default)\r
+[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 3.134301] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 3.134302] pci_bus 0000:00: scanning bus\r
+[ 3.134304] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 3.134306] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 3.134329] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 3.134336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.134354] pci_bus 0000:00: fixups for bus\r
+[ 3.134355] pci_bus 0000:00: bus scan returning with max=00\r
+[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 3.134361] pci 0000:00:00.0: fixup irq: got 33\r
+[ 3.134363] pci 0000:00:00.0: assigning IRQ 33\r
+[ 3.134365] pci 0000:00:01.0: fixup irq: got 34\r
+[ 3.134367] pci 0000:00:01.0: assigning IRQ 34\r
+[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 3.134372] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 3.134377] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.134813] ata_piix 0000:00:01.0: version 2.13\r
+[ 3.134815] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 3.134820] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 3.135009] scsi0 : ata_piix\r
+[ 3.135063] scsi1 : ata_piix\r
+[ 3.135081] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 3.135082] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.135143] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.135144] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.135148] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.135150] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.290565] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 3.290566] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 3.290572] ata1.00: configured for UDMA/33\r
+[ 3.290589] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 3.290650] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 3.290658] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 3.290672] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 3.290673] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 3.290680] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 3.290733] sda: sda1\r
+[ 3.290795] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 3.410824] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 3.410825] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 3.410832] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 3.410833] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 3.410841] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 3.410842] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 3.410886] usbcore: registered new interface driver usb-storage\r
+[ 3.410912] mousedev: PS/2 mouse device common for all mice\r
+[ 3.411009] usbcore: registered new interface driver usbhid\r
+[ 3.411010] usbhid: USB HID core driver\r
+[ 3.411025] TCP: cubic registered\r
+[ 3.411026] NET: Registered protocol family 17\r
+\0[ 3.411204] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 3.411214] devtmpfs: mounted\r
+[ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+\0\0\rINIT: \0version 2.88 booting\0\r\r
+\0Starting udev\r
+[ 3.446950] udevd[607]: starting version 182\r
+Starting Bootlog daemon: bootlogd.\r\r
+[ 3.532262] random: dd urandom read with 19 bits of entropy available\r
+Populating dev cache\r\r
+net.ipv4.conf.default.rp_filter = 1\r\r
+net.ipv4.conf.all.rp_filter = 1\r\r
+hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
+Mon Jan 27 08:00:00 UTC 2014\r\r
+hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
+\rINIT: Entering runlevel: 5\r\r\r
+Configuring network interfaces... udhcpc (v1.21.1) started\r\r
+[ 3.640780] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+Sending discover...\r\r
+Sending discover...\r\r
+Sending discover...\r\r
+No lease, forking to background\r\r
+done.\r\r
+Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
+rpcbind: cannot create socket for tcp6\r\r\r
+done.\r\r
+rpcbind: cannot get uid of '': Success\r\r\r
+creating NFS state directory: done\r\r
+starting statd: done\r\r
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+eventq_index=0
+flags_addr=469827632
+gic_cpu_addr=738205696
+have_generic_timer=false
+have_large_asid_64=false
+have_lpae=false
+have_security=false
+have_virtualization=false
+highest_el_is_64=false
+init_param=0
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=timing
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
+clk_domain=system.clk_domain
+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+eventq_index=0
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+eventq_index=0
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu0]
+type=TimingSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu0.dstage2_mmu
+dtb=system.cpu0.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+istage2_mmu=system.cpu0.istage2_mmu
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=6
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.dcache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=16
+cpu_side=system.cpu0.dcache_port
+mem_side=system.cpu0.toL2Bus.slave[1]
+
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu0.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu0.dtb
+
+[system.cpu0.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu0.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu0.toL2Bus.slave[3]
+
+[system.cpu0.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=1
+is_top_level=true
+max_miss_count=0
+mshrs=2
+prefetch_on_access=false
+prefetcher=Null
+response_latency=1
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.icache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.cpu0.toL2Bus.slave[0]
+
+[system.cpu0.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=1
+sequential_access=false
+size=32768
+
+[system.cpu0.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu0.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu0.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu0.itb
+
+[system.cpu0.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu0.istage2_mmu.stage2_tlb.walker
+
+[system.cpu0.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu0.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu0.toL2Bus.slave[2]
+
+[system.cpu0.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu0.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu0.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.l2cache.prefetcher]
+type=StridePrefetcher
+cache_snoop=false
+clk_domain=system.cpu_clk_domain
+degree=8
+eventq_index=0
+latency=1
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
+sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
+use_master_id=true
+
+[system.cpu0.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu0.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu0.l2cache.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+
+[system.cpu0.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=1
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu1.dstage2_mmu
+dtb=system.cpu1.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
+istage2_mmu=system.cpu1.istage2_mmu
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu1.tracer
+workload=
+dcache_port=system.cpu1.dcache.cpu_side
+icache_port=system.cpu1.icache.cpu_side
+
+[system.cpu1.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=6
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu1.dcache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=16
+cpu_side=system.cpu1.dcache_port
+mem_side=system.cpu1.toL2Bus.slave[1]
+
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu1.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu1.dtb
+
+[system.cpu1.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu1.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu1.toL2Bus.slave[3]
+
+[system.cpu1.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=1
+is_top_level=true
+max_miss_count=0
+mshrs=2
+prefetch_on_access=false
+prefetcher=Null
+response_latency=1
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu1.icache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.icache_port
+mem_side=system.cpu1.toL2Bus.slave[0]
+
+[system.cpu1.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=1
+sequential_access=false
+size=32768
+
+[system.cpu1.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu1.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu1.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu1.itb
+
+[system.cpu1.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.istage2_mmu.stage2_tlb.walker
+
+[system.cpu1.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu1.toL2Bus.slave[2]
+
+[system.cpu1.l2cache]
+type=BaseCache
+children=prefetcher tags
+addr_ranges=0:18446744073709551615
+assoc=16
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=12
+is_top_level=false
+max_miss_count=0
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu1.l2cache.prefetcher
+response_latency=12
+sequential_access=false
+size=1048576
+system=system
+tags=system.cpu1.l2cache.tags
+tgts_per_mshr=8
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.toL2Bus.master[0]
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l2cache.prefetcher]
+type=StridePrefetcher
+cache_snoop=false
+clk_domain=system.cpu_clk_domain
+degree=8
+eventq_index=0
+latency=1
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
+sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
+use_master_id=true
+
+[system.cpu1.l2cache.tags]
+type=RandomRepl
+assoc=16
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=12
+sequential_access=false
+size=1048576
+
+[system.cpu1.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu1.l2cache.cpu_side
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
+
+[system.cpu1.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=1
+frontend_latency=2
+response_latency=2
+use_default_range=true
+width=16
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.l2c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.l2c.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+response_latency=2
+snoop_filter=Null
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaCoCh
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=2147483648:2415919103
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.l2c.cpu_side
+slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:01:57
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu0.isa: ISA system set to: 0x5b5eb00 0x5b5eb00
+ 0: system.cpu1.isa: ISA system set to: 0x5b5eb00 0x5b5eb00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 47438274662000 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 47.367818 # Number of seconds simulated
+sim_ticks 47367817574000 # Number of ticks simulated
+final_tick 47367817574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 678056 # Simulator instruction rate (inst/s)
+host_op_rate 798173 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 38043399524 # Simulator tick rate (ticks/s)
+host_mem_usage 751768 # Number of bytes of host memory used
+host_seconds 1245.10 # Real time elapsed on the host
+sim_insts 844246943 # Number of instructions simulated
+sim_ops 993804803 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu0.dtb.walker 36928 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 40576 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 2794548 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 9993048 # Number of bytes read from this memory
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+system.physmem.bytes_read::cpu1.itb.walker 86016 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2509048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 8105888 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 7582272 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 437184 # Number of bytes read from this memory
+system.physmem.bytes_read::total 41225828 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 2794548 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 2509048 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5303596 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 61292480 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
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+system.physmem.num_reads::cpu0.itb.walker 634 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 84072 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 156163 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 149501 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 1129 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 1344 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 39292 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 126669 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 118473 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6831 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 684685 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 957695 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 960298 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 780 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 857 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 58997 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 210967 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 201995 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 1525 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 1816 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 52969 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 171126 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 160072 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 9230 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 870334 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 58997 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 52969 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 111966 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1293969 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1294408 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1293969 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 780 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 857 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 58997 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 211406 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 201995 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 1525 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 1816 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 52969 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 171127 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 160072 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 9230 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2164742 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 684685 # Number of read requests accepted
+system.physmem.writeReqs 1596629 # Number of write requests accepted
+system.physmem.readBursts 684685 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1596629 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 43802304 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 17536 # Total number of bytes read from write queue
+system.physmem.bytesWritten 99044160 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 41225828 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 102038480 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 274 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 49035 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 111704 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 42136 # Per bank write bursts
+system.physmem.perBankRdBursts::1 44080 # Per bank write bursts
+system.physmem.perBankRdBursts::2 34958 # Per bank write bursts
+system.physmem.perBankRdBursts::3 41288 # Per bank write bursts
+system.physmem.perBankRdBursts::4 39326 # Per bank write bursts
+system.physmem.perBankRdBursts::5 49165 # Per bank write bursts
+system.physmem.perBankRdBursts::6 40428 # Per bank write bursts
+system.physmem.perBankRdBursts::7 47118 # Per bank write bursts
+system.physmem.perBankRdBursts::8 36254 # Per bank write bursts
+system.physmem.perBankRdBursts::9 81044 # Per bank write bursts
+system.physmem.perBankRdBursts::10 36070 # Per bank write bursts
+system.physmem.perBankRdBursts::11 40557 # Per bank write bursts
+system.physmem.perBankRdBursts::12 34453 # Per bank write bursts
+system.physmem.perBankRdBursts::13 38158 # Per bank write bursts
+system.physmem.perBankRdBursts::14 37145 # Per bank write bursts
+system.physmem.perBankRdBursts::15 42231 # Per bank write bursts
+system.physmem.perBankWrBursts::0 97165 # Per bank write bursts
+system.physmem.perBankWrBursts::1 99476 # Per bank write bursts
+system.physmem.perBankWrBursts::2 95543 # Per bank write bursts
+system.physmem.perBankWrBursts::3 98326 # Per bank write bursts
+system.physmem.perBankWrBursts::4 92692 # Per bank write bursts
+system.physmem.perBankWrBursts::5 102230 # Per bank write bursts
+system.physmem.perBankWrBursts::6 96747 # Per bank write bursts
+system.physmem.perBankWrBursts::7 98806 # Per bank write bursts
+system.physmem.perBankWrBursts::8 93672 # Per bank write bursts
+system.physmem.perBankWrBursts::9 100275 # Per bank write bursts
+system.physmem.perBankWrBursts::10 92352 # Per bank write bursts
+system.physmem.perBankWrBursts::11 96579 # Per bank write bursts
+system.physmem.perBankWrBursts::12 94667 # Per bank write bursts
+system.physmem.perBankWrBursts::13 97213 # Per bank write bursts
+system.physmem.perBankWrBursts::14 92658 # Per bank write bursts
+system.physmem.perBankWrBursts::15 99164 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 352 # Number of times write queue was full causing retry
+system.physmem.totGap 47367814519500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 43195 # Read request sizes (log2)
+system.physmem.readPktSize::3 37 # Read request sizes (log2)
+system.physmem.readPktSize::4 5 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 641448 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 2 # Write request sizes (log2)
+system.physmem.writePktSize::3 2601 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 1594026 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 510577 # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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+system.physmem.wrQLenPdf::59 504 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::61 424 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 339 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 1324 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 813055 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 175.690629 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 106.318755 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 249.924527 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 526198 64.72% 64.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 156067 19.20% 83.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 35208 4.33% 88.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 17256 2.12% 90.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 12096 1.49% 91.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 8107 1.00% 92.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 6222 0.77% 93.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 5625 0.69% 94.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 46276 5.69% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 813055 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 73772 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 9.277314 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 118.735455 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 73768 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 73772 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 73772 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 20.977674 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 19.369218 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 19.656514 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 71961 97.55% 97.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47 712 0.97% 98.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63 29 0.04% 98.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79 36 0.05% 98.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95 132 0.18% 98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 174 0.24% 99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127 342 0.46% 99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143 135 0.18% 99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159 19 0.03% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 12 0.02% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 64 0.09% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 33 0.04% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 12 0.02% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 4 0.01% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255 4 0.01% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 7 0.01% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 6 0.01% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 10 0.01% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 9 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 6 0.01% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 10 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 15 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399 2 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::432-447 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 6 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-511 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 7 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 1 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::560-575 3 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::576-591 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::592-607 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::640-655 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::688-703 2 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::720-735 2 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 73772 # Writes before turning the bus around for reads
+system.physmem.totQLat 20326500723 # Total ticks spent queuing
+system.physmem.totMemAccLat 33159206973 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 3422055000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 29699.26 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 48449.26 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 0.92 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.09 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 0.87 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.15 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.02 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing
+system.physmem.readRowHits 509481 # Number of row buffer hits during reads
+system.physmem.writeRowHits 909439 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 74.44 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes
+system.physmem.avgGap 20763390.98 # Average gap between requests
+system.physmem.pageHitRate 63.57 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 3169991160 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1729657875 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 2640253200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 5060782800 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1178038765890 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 27387322041000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 31671796931685 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.635370 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 45560807372172 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1581715460000 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 225294290828 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem_1.actEnergy 2976704640 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1624194000 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 2698113600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 4967438400 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1169320459140 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 27394969678500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 31670392028040 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.605711 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 45573545582628 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1581715460000 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 212554603622 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.walks 95467 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 95467 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8616 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72889 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 95458 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 0.225230 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 69.587670 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-2047 95457 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::20480-22527 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 95458 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 81514 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 17324.683490 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 15769.335506 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 10694.107977 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 81100 99.49% 99.49% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 359 0.44% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 15 0.02% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 81514 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 1873275212 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 1.115454 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 -216276296 -11.55% -11.55% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 2089551508 111.55% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 1873275212 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 72890 89.43% 89.43% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 8616 10.57% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 81506 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 95467 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 95467 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81506 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81506 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 176973 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 81219280 # DTB read hits
+system.cpu0.dtb.read_misses 71070 # DTB read misses
+system.cpu0.dtb.write_hits 73504932 # DTB write hits
+system.cpu0.dtb.write_misses 24397 # DTB write misses
+system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 38298 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 4007 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 10240 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 81290350 # DTB read accesses
+system.cpu0.dtb.write_accesses 73529329 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 154724212 # DTB hits
+system.cpu0.dtb.misses 95467 # DTB misses
+system.cpu0.dtb.accesses 154819679 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.walks 56383 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 56383 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 751 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 50468 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 56383 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 56383 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 56383 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 51219 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 19351.129327 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 17618.924664 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 12629.312385 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767 47792 93.31% 93.31% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535 2988 5.83% 99.14% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303 157 0.31% 99.45% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071 221 0.43% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.03% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607 4 0.01% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.03% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 51219 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples -241360296 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 -241360296 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total -241360296 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 50468 98.53% 98.53% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 751 1.47% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 51219 # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56383 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 56383 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51219 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51219 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 107602 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 434853798 # ITB inst hits
+system.cpu0.itb.inst_misses 56383 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 26912 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 434910181 # ITB inst accesses
+system.cpu0.itb.hits 434853798 # DTB hits
+system.cpu0.itb.misses 56383 # DTB misses
+system.cpu0.itb.accesses 434910181 # DTB accesses
+system.cpu0.numCycles 94735635148 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.committedInsts 434594659 # Number of instructions committed
+system.cpu0.committedOps 509819268 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 468245604 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 368958 # Number of float alu accesses
+system.cpu0.num_func_calls 25685063 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 65742912 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 468245604 # number of integer instructions
+system.cpu0.num_fp_insts 368958 # number of float instructions
+system.cpu0.num_int_register_reads 681605000 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 371986080 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 629019 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 237888 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 113785122 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 113402508 # number of times the CC registers were written
+system.cpu0.num_mem_refs 154715442 # number of memory refs
+system.cpu0.num_load_insts 81215665 # Number of load instructions
+system.cpu0.num_store_insts 73499777 # Number of store instructions
+system.cpu0.num_idle_cycles 93677942540.842026 # Number of idle cycles
+system.cpu0.num_busy_cycles 1057692607.157978 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.011165 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.988835 # Percentage of idle cycles
+system.cpu0.Branches 96525602 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 354149041 69.42% 69.42% # Class of executed instruction
+system.cpu0.op_class::IntMult 1173113 0.23% 69.65% # Class of executed instruction
+system.cpu0.op_class::IntDiv 59997 0.01% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 23937 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::MemRead 81215665 15.92% 85.59% # Class of executed instruction
+system.cpu0.op_class::MemWrite 73499777 14.41% 100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu0.op_class::total 510121531 # Class of executed instruction
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 13974 # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements 5284481 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 474.292500 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 149186915 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 5284993 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 28.228404 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 4077089500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 474.292500 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.926353 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.926353 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses 314708854 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 314708854 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 75740068 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 75740068 # number of ReadReq hits
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+system.cpu0.dcache.WriteInvalidateReq_hits::total 143100 # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1662300 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 1662300 # number of LoadLockedReq hits
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+system.cpu0.dcache.StoreCondReq_hits::total 1634095 # number of StoreCondReq hits
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+system.cpu0.dcache.SoftPFReq_misses::total 635767 # number of SoftPFReq misses
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+system.cpu0.dcache.demand_misses::cpu0.data 4140939 # number of demand (read+write) misses
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+system.cpu0.dcache.overall_misses::total 4776706 # number of overall misses
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+system.cpu0.dcache.overall_accesses::total 150138618 # number of overall (read+write) accesses
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+system.cpu0.dcache.ReadReq_miss_rate::total 0.035901 # miss rate for ReadReq accesses
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+system.cpu0.dcache.WriteReq_miss_rate::total 0.018661 # miss rate for WriteReq accesses
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+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781789 # miss rate for SoftPFReq accesses
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+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839055 # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085831 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085831 # miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100684 # miss rate for StoreCondReq accesses
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+system.cpu0.dcache.demand_miss_rate::total 0.027731 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031815 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.031815 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14027.073411 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14027.073411 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18430.730664 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 18430.730664 # average WriteReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41477.242118 # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41477.242118 # average WriteInvalidateReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13759.923324 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13759.923324 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21654.913478 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21654.913478 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15431.397107 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 15431.397107 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13377.518755 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13377.518755 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes 0 # number of fast writes performed
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks 3634622 # number of writebacks
+system.cpu0.dcache.writebacks::total 3634622 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28612 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 28612 # number of ReadReq MSHR hits
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+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 38145 # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.demand_mshr_hits::total 49969 # number of demand (read+write) MSHR hits
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+system.cpu0.dcache.overall_mshr_hits::total 49969 # number of overall MSHR hits
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+system.cpu0.dcache.ReadReq_mshr_misses::total 2791784 # number of ReadReq MSHR misses
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+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12432309289 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29820271426 # number of WriteInvalidateReq MSHR miss cycles
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1422971246 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1422971246 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3676791544 # number of StoreCondReq MSHR miss cycles
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+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1208000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1208000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 56092609905 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 56092609905 # number of demand (read+write) MSHR miss cycles
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+system.cpu0.dcache.overall_mshr_miss_latency::total 68524919194 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4525228998 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4525228998 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4129291250 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4129291250 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8654520248 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8654520248 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035537 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035537 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018359 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018359 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.774878 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.774878 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.839055 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.839055 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064853 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064853 # mshr miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12066.543251 # average LoadLockedReq mshr miss latency
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+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20873.741897 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15129.520789 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15129.520789 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 335166.666667 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 335166.666667 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38586.013882 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38586.013882 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25928.818372 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28813.655266 # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.toL2Bus.trans_dist::ReadReq 10272423 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 8656546 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 26078 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 26078 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 3634622 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 896357 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1072966 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 744713 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 432357 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330872 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 471310 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1218200 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1108311 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9087184 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15490281 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 297199 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 469779 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 25344443 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 288202388 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 584369767 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1031640 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1541304 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 875145099 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 3727007 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 17787477 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 3.192426 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.394206 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 14364709 80.76% 80.76% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 3422768 19.24% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 17787477 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 11622970748 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 201159488 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer0.occupancy 6810939722 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer1.occupancy 7629819592 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer2.occupancy 168326514 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer3.occupancy 277196500 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.walks 92509 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 92509 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6608 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 71644 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 92500 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 0.081081 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 24.659848 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-511 92499 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::7168-7679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 92500 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 78261 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 18926.409693 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 17150.140934 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 13619.258696 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 77412 98.92% 98.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 724 0.93% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.04% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 50 0.06% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 78261 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 2425306712 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.143168 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 2078081352 85.68% 85.68% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1 347225360 14.32% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 2425306712 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 71644 91.56% 91.56% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 6608 8.44% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 78252 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92509 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92509 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 78252 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 78252 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 170761 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 78277454 # DTB read hits
+system.cpu1.dtb.read_misses 68245 # DTB read misses
+system.cpu1.dtb.write_hits 71517077 # DTB write hits
+system.cpu1.dtb.write_misses 24264 # DTB write misses
+system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 32777 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 3876 # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 8314 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 78345699 # DTB read accesses
+system.cpu1.dtb.write_accesses 71541341 # DTB write accesses
+system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dtb.hits 149794531 # DTB hits
+system.cpu1.dtb.misses 92509 # DTB misses
+system.cpu1.dtb.accesses 149887040 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.walks 60524 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 60524 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 415 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54985 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 60524 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 60524 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 60524 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 55400 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 21598.519856 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 19393.747052 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 17485.706336 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767 51757 93.42% 93.42% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535 2619 4.73% 98.15% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303 338 0.61% 98.76% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071 537 0.97% 99.73% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.77% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375 37 0.07% 99.86% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911 28 0.05% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::491520-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 55400 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 2054805852 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 2054805852 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 2054805852 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 54985 99.25% 99.25% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 415 0.75% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 55400 # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60524 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60524 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55400 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55400 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 115924 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 409921957 # ITB inst hits
+system.cpu1.itb.inst_misses 60524 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.write_hits 0 # DTB write hits
+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 23091 # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 409982481 # ITB inst accesses
+system.cpu1.itb.hits 409921957 # DTB hits
+system.cpu1.itb.misses 60524 # DTB misses
+system.cpu1.itb.accesses 409982481 # DTB accesses
+system.cpu1.numCycles 94735635148 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.committedInsts 409652284 # Number of instructions committed
+system.cpu1.committedOps 483985535 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 446181756 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 565626 # Number of float alu accesses
+system.cpu1.num_func_calls 25682090 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 61510479 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 446181756 # number of integer instructions
+system.cpu1.num_fp_insts 565626 # number of float instructions
+system.cpu1.num_int_register_reads 638057436 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 352717621 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 886208 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 535956 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 102771786 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 102542500 # number of times the CC registers were written
+system.cpu1.num_mem_refs 149782083 # number of memory refs
+system.cpu1.num_load_insts 78271508 # Number of load instructions
+system.cpu1.num_store_insts 71510575 # Number of store instructions
+system.cpu1.num_idle_cycles 93767065494.048019 # Number of idle cycles
+system.cpu1.num_busy_cycles 968569653.951980 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.010224 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.989776 # Percentage of idle cycles
+system.cpu1.Branches 91673037 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 333338821 68.84% 68.84% # Class of executed instruction
+system.cpu1.op_class::IntMult 986884 0.20% 69.04% # Class of executed instruction
+system.cpu1.op_class::IntDiv 58271 0.01% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 89216 0.02% 69.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.07% # Class of executed instruction
+system.cpu1.op_class::MemRead 78271508 16.16% 85.23% # Class of executed instruction
+system.cpu1.op_class::MemWrite 71510575 14.77% 100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::total 484255317 # Class of executed instruction
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 5204 # number of quiesce instructions executed
+system.cpu1.dcache.tags.replacements 4752540 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 455.880794 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 144856637 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 4753051 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 30.476559 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 8382286333500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.880794 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890392 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.890392 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 304369060 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 304369060 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 73044937 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 73044937 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 67886662 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 67886662 # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data 184038 # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total 184038 # number of SoftPFReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 188938 # number of WriteInvalidateReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::total 188938 # number of WriteInvalidateReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1611925 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 1611925 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1592857 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 1592857 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 140931599 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 140931599 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 141115637 # number of overall hits
+system.cpu1.dcache.overall_hits::total 141115637 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 2767627 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 2767627 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 1154762 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 1154762 # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data 498783 # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total 498783 # number of SoftPFReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 496292 # number of WriteInvalidateReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::total 496292 # number of WriteInvalidateReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158321 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 158321 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 176268 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 176268 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 3922389 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 3922389 # number of demand (read+write) misses
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+system.cpu1.dcache.overall_misses::total 4421172 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 37645623046 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 37645623046 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19534966036 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 19534966036 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11881656902 # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11881656902 # number of WriteInvalidateReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2306877268 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 2306877268 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3770896575 # number of StoreCondReq miss cycles
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+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1887000 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1887000 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 57180589082 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 57180589082 # number of demand (read+write) miss cycles
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+system.cpu1.dcache.overall_miss_latency::total 57180589082 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 75812564 # number of ReadReq accesses(hits+misses)
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+system.cpu1.dcache.WriteReq_accesses::cpu1.data 69041424 # number of WriteReq accesses(hits+misses)
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+system.cpu1.dcache.SoftPFReq_accesses::total 682821 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 685230 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::total 685230 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1770246 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 1770246 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1769125 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 1769125 # number of StoreCondReq accesses(hits+misses)
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+system.cpu1.dcache.overall_accesses::total 145536809 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036506 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.036506 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016726 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.016726 # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.730474 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.730474 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.724271 # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.724271 # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089434 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089434 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099636 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099636 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027078 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.027078 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030378 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.030378 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13602.130289 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13602.130289 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16916.876409 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 16916.876409 # average WriteReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 23940.859216 # average WriteInvalidateReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 23940.859216 # average WriteInvalidateReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14570.886162 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14570.886162 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21392.973058 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21392.973058 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14578.000571 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14578.000571 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12933.355473 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 12933.355473 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes 0 # number of fast writes performed
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.writebacks::writebacks 3063492 # number of writebacks
+system.cpu1.dcache.writebacks::total 3063492 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11545 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 11545 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 352 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 352 # number of WriteReq MSHR hits
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+system.cpu1.dcache.demand_mshr_hits::cpu1.data 11897 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 11897 # number of demand (read+write) MSHR hits
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+system.cpu1.dcache.overall_mshr_hits::total 11897 # number of overall MSHR hits
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+system.cpu1.dcache.WriteReq_mshr_misses::total 1154410 # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 498783 # number of SoftPFReq MSHR misses
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+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 111639 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 111639 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 176268 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 176268 # number of StoreCondReq MSHR misses
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+system.cpu1.dcache.overall_mshr_misses::total 4409275 # number of overall MSHR misses
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+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 17743172214 # number of WriteReq MSHR miss cycles
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+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9770846491 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 9770846491 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11134079098 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11134079098 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1396307998 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1396307998 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3498646925 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3498646925 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1819500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1819500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 50602962592 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 50602962592 # number of demand (read+write) MSHR miss cycles
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+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19589.373517 # average SoftPFReq mshr miss latency
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+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22434.532690 # average WriteInvalidateReq mshr miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12507.349564 # average LoadLockedReq mshr miss latency
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+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191832 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24122.647893 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23948.829754 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33772.870485 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32243.321967 # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32243.321967 # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19748.308136 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19748.308136 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14712.282892 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14712.282892 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296199.600000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296199.600000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31396.349903 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31396.349903 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25010.215568 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27352.810917 # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.toL2Bus.trans_dist::ReadReq 11346555 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 9442060 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 12895 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 12895 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 3063492 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 747367 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1164315 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 494732 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 387368 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 328581 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 412328 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1123330 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 992188 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11047474 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13661084 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 335346 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 476365 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 25520269 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353512568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 512414548 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1234496 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1647784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 868809396 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 4168573 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 18149089 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 3.215812 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.411385 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 14232289 78.42% 78.42% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 3916800 21.58% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 18149089 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 10693279996 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 176128990 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer0.occupancy 8292291078 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer1.occupancy 7012668647 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer2.occupancy 181227501 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer3.occupancy 270567252 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 40336 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40336 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136623 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29895 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122628 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155735 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7496677 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36212000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 607542087 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 92736000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 148516061 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.replacements 115606 # number of replacements
+system.iocache.tags.tagsinuse 11.280528 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115622 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 9179145722000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 7.421794 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 3.858734 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.463862 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.241171 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.705033 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1040802 # Number of tag accesses
+system.iocache.tags.data_accesses 1040802 # Number of data accesses
+system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses
+system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8917 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
+system.iocache.overall_misses::realview.ide 8877 # number of overall misses
+system.iocache.overall_misses::total 8917 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 1629440754 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 1634636254 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19888935272 # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total 19888935272 # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide 1629440754 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 1635005254 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide 1629440754 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 1635005254 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
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+system.membus.snoops 581158 # Total snoops (count)
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+system.membus.snoop_fanout::mean 1 # Request fanout histogram
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+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
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+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
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+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
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+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
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+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq 3783137 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 3775909 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38973 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38973 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 2047649 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 890925 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 784014 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 429633 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 300246 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 729879 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 258637 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 258637 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 6917142 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4903000 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 11820142 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 229102843 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 151634764 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 380737607 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1518303 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 7628101 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.015184 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.122286 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 7512273 98.48% 98.48% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 115828 1.52% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 7628101 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 6924291534 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 2530500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 3796276244 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 3095093071 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[ 0.000000] Initializing cgroup subsys cpu\r
+[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
+[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
+[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
+[ 0.000000] Memory limited to 256MB\r
+[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
+[ 0.000000] On node 0 totalpages: 65536\r
+[ 0.000000] DMA zone: 896 pages used for memmap\r
+[ 0.000000] DMA zone: 0 pages reserved\r
+[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
+[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
+[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
+[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
+[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
+[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
+[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
+[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
+[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
+[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
+[ 0.000000] Virtual kernel memory layout:\r
+[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
+[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
+[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
+[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
+[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
+[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
+[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
+[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
+[ 0.000000] Preemptible hierarchical RCU implementation.\r
+[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
+[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
+[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
+[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
+[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
+[ 0.000024] Console: colour dummy device 80x25\r
+[ 0.000026] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000028] pid_max: default: 32768 minimum: 301\r
+[ 0.000041] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000043] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000177] hw perfevents: no hardware support available\r
+[ 0.060047] CPU1: Booted secondary processor\r
+[ 1.080090] CPU2: failed to come online\r
+[ 2.100176] CPU3: failed to come online\r
+[ 2.100179] Brought up 2 CPUs\r
+[ 2.100180] SMP: Total of 2 processors activated.\r
+[ 2.100246] devtmpfs: initialized\r
+[ 2.101156] atomic64_test: passed\r
+[ 2.101216] regulator-dummy: no parameters\r
+[ 2.101757] NET: Registered protocol family 16\r
+[ 2.101938] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 2.101944] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 2.102749] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 2.102752] Serial: AMBA PL011 UART driver\r
+[ 2.102985] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 2.103030] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 2.103571] console [ttyAMA0] enabled\r
+[ 2.103651] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 2.103687] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 2.103724] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 2.103758] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 2.130471] 3V3: 3300 mV \r
+[ 2.130527] vgaarb: loaded\r
+[ 2.130588] SCSI subsystem initialized\r
+[ 2.130625] libata version 3.00 loaded.\r
+[ 2.130697] usbcore: registered new interface driver usbfs\r
+[ 2.130719] usbcore: registered new interface driver hub\r
+[ 2.130747] usbcore: registered new device driver usb\r
+[ 2.130780] pps_core: LinuxPPS API ver. 1 registered\r
+[ 2.130789] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 2.130808] PTP clock support registered\r
+[ 2.130983] Switched to clocksource arch_sys_counter\r
+[ 2.132484] NET: Registered protocol family 2\r
+[ 2.132575] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 2.132593] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 2.132613] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 2.132639] TCP: reno registered\r
+[ 2.132646] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.132659] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.132700] NET: Registered protocol family 1\r
+[ 2.132760] RPC: Registered named UNIX socket transport module.\r
+[ 2.132769] RPC: Registered udp transport module.\r
+[ 2.132777] RPC: Registered tcp transport module.\r
+[ 2.132785] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 2.132797] PCI: CLS 0 bytes, default 64\r
+[ 2.133009] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 2.133115] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 2.136052] fuse init (API version 7.23)\r
+[ 2.136196] msgmni has been set to 469\r
+[ 2.136706] io scheduler noop registered\r
+[ 2.136791] io scheduler cfq registered (default)\r
+[ 2.137366] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 2.137378] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 2.137389] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 2.137401] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 2.137411] pci_bus 0000:00: scanning bus\r
+[ 2.137421] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 2.137433] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 2.137448] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.137496] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 2.137508] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 2.137518] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 2.137529] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 2.137540] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 2.137551] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 2.137562] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.137612] pci_bus 0000:00: fixups for bus\r
+[ 2.137620] pci_bus 0000:00: bus scan returning with max=00\r
+[ 2.137631] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 2.137651] pci 0000:00:00.0: fixup irq: got 33\r
+[ 2.137660] pci 0000:00:00.0: assigning IRQ 33\r
+[ 2.137670] pci 0000:00:01.0: fixup irq: got 34\r
+[ 2.137679] pci 0000:00:01.0: assigning IRQ 34\r
+[ 2.137690] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 2.137702] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 2.137715] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 2.137727] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 2.137739] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 2.137750] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 2.137761] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 2.137773] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 2.138657] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 2.139057] ata_piix 0000:00:01.0: version 2.13\r
+[ 2.139067] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 2.139093] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 2.139456] scsi0 : ata_piix\r
+[ 2.139567] scsi1 : ata_piix\r
+[ 2.139611] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 2.139623] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 2.139769] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 2.139781] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 2.139797] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 2.139808] e1000 0000:00:00.0: enabling bus mastering\r
+[ 2.291018] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 2.291027] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 2.291054] ata1.00: configured for UDMA/33\r
+[ 2.291104] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 2.291261] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 2.291294] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 2.291338] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 2.291347] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 2.291369] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 2.291545] sda: sda1\r
+[ 2.291741] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 2.411341] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 2.411354] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 2.411387] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 2.411399] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 2.411432] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 2.411446] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 2.411610] usbcore: registered new interface driver usb-storage\r
+[ 2.411699] mousedev: PS/2 mouse device common for all mice\r
+[ 2.412097] usbcore: registered new interface driver usbhid\r
+[ 2.412108] usbhid: USB HID core driver\r
+[ 2.412141] TCP: cubic registered\r
+[ 2.412149] NET: Registered protocol family 17\r
+\0[ 2.412566] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 2.412601] devtmpfs: mounted\r
+[ 2.412656] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+\0\0\rINIT: \0version 2.88 booting\0\r\r
+\0Starting udev\r
+[ 2.452574] udevd[608]: starting version 182\r
+Starting Bootlog daemon: bootlogd.\r\r
+[ 2.544108] random: dd urandom read with 18 bits of entropy available\r
+Populating dev cache\r\r
+net.ipv4.conf.default.rp_filter = 1\r\r
+net.ipv4.conf.all.rp_filter = 1\r\r
+hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
+Mon Jan 27 08:00:00 UTC 2014\r\r
+hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
+\rINIT: Entering runlevel: 5\r\r\r
+Configuring network interfaces... udhcpc (v1.21.1) started\r\r
+[ 2.681213] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+Sending discover...\r\r
+Sending discover...\r\r
+Sending discover...\r\r
+No lease, forking to background\r\r
+done.\r\r
+Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
+rpcbind: cannot create socket for tcp6\r\r\r
+rpcbind: cannot get uid of '': Success\r\r\r
+done.\r\r
+creating NFS state directory: done\r\r
+starting statd: done\r\r
+Starting auto-serial-console:
\ No newline at end of file
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+eventq_index=0
+flags_addr=469827632
+gic_cpu_addr=738205696
+have_generic_timer=false
+have_large_asid_64=false
+have_lpae=false
+have_security=false
+have_virtualization=false
+highest_el_is_64=false
+init_param=0
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=timing
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
+clk_domain=system.clk_domain
+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+eventq_index=0
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+eventq_index=0
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
+dtb=system.cpu.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[3]
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=1
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=1
+frontend_latency=2
+response_latency=2
+use_default_range=true
+width=16
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+response_latency=2
+snoop_filter=Null
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaCoCh
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+page_policy=open_adaptive
+range=2147483648:2415919103
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:01:52
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+ 0: system.cpu.isa: ISA system set to: 0x500ab00 0x500ab00
+info: Using bootloader at address 0x10
+info: Using kernel entry physical address at 0x80080000
+info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 51781056074000 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 51.824462 # Number of seconds simulated
+sim_ticks 51824462100500 # Number of ticks simulated
+final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 723017 # Simulator instruction rate (inst/s)
+host_op_rate 849578 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 41937024652 # Simulator tick rate (ticks/s)
+host_mem_usage 712044 # Number of bytes of host memory used
+host_seconds 1235.77 # Real time elapsed on the host
+sim_insts 893481288 # Number of instructions simulated
+sim_ops 1049881338 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.dtb.walker 266048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 259456 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 5261620 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 50351624 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 398272 # Number of bytes read from this memory
+system.physmem.bytes_read::total 56537020 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 5261620 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5261620 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 77705792 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
+system.physmem.bytes_written::total 77726372 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 4157 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 4054 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 122620 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 786757 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6223 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 923811 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1214153 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1216726 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 5134 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 5006 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 101528 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 971580 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 7685 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1090933 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 101528 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 101528 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1499404 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1499801 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1499404 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 5134 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 5006 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 101528 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 971977 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 7685 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2590734 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 923811 # Number of read requests accepted
+system.physmem.writeReqs 1833124 # Number of write requests accepted
+system.physmem.readBursts 923811 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1833124 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 59092736 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 31168 # Total number of bytes read from write queue
+system.physmem.bytesWritten 114062016 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 56537020 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 117175844 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 487 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 50880 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 36215 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 57129 # Per bank write bursts
+system.physmem.perBankRdBursts::1 60965 # Per bank write bursts
+system.physmem.perBankRdBursts::2 52485 # Per bank write bursts
+system.physmem.perBankRdBursts::3 50413 # Per bank write bursts
+system.physmem.perBankRdBursts::4 54002 # Per bank write bursts
+system.physmem.perBankRdBursts::5 59718 # Per bank write bursts
+system.physmem.perBankRdBursts::6 51713 # Per bank write bursts
+system.physmem.perBankRdBursts::7 51669 # Per bank write bursts
+system.physmem.perBankRdBursts::8 50247 # Per bank write bursts
+system.physmem.perBankRdBursts::9 101235 # Per bank write bursts
+system.physmem.perBankRdBursts::10 59848 # Per bank write bursts
+system.physmem.perBankRdBursts::11 58323 # Per bank write bursts
+system.physmem.perBankRdBursts::12 55369 # Per bank write bursts
+system.physmem.perBankRdBursts::13 55988 # Per bank write bursts
+system.physmem.perBankRdBursts::14 51743 # Per bank write bursts
+system.physmem.perBankRdBursts::15 52477 # Per bank write bursts
+system.physmem.perBankWrBursts::0 110630 # Per bank write bursts
+system.physmem.perBankWrBursts::1 112240 # Per bank write bursts
+system.physmem.perBankWrBursts::2 108805 # Per bank write bursts
+system.physmem.perBankWrBursts::3 108103 # Per bank write bursts
+system.physmem.perBankWrBursts::4 111102 # Per bank write bursts
+system.physmem.perBankWrBursts::5 113339 # Per bank write bursts
+system.physmem.perBankWrBursts::6 105567 # Per bank write bursts
+system.physmem.perBankWrBursts::7 107723 # Per bank write bursts
+system.physmem.perBankWrBursts::8 108849 # Per bank write bursts
+system.physmem.perBankWrBursts::9 115780 # Per bank write bursts
+system.physmem.perBankWrBursts::10 115663 # Per bank write bursts
+system.physmem.perBankWrBursts::11 113049 # Per bank write bursts
+system.physmem.perBankWrBursts::12 112494 # Per bank write bursts
+system.physmem.perBankWrBursts::13 116984 # Per bank write bursts
+system.physmem.perBankWrBursts::14 111502 # Per bank write bursts
+system.physmem.perBankWrBursts::15 110389 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 145 # Number of times write queue was full causing retry
+system.physmem.totGap 51824459475500 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 43101 # Read request sizes (log2)
+system.physmem.readPktSize::3 13 # Read request sizes (log2)
+system.physmem.readPktSize::4 2 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 880695 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 1 # Write request sizes (log2)
+system.physmem.writePktSize::3 2572 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 1830551 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 889155 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 28186 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 284 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 462 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 528 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 455 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 746 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 480 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1765 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 111 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 102 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 57524 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 60978 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 91825 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 117209 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 106855 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 97040 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 98714 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::23 94185 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::26 98737 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::28 94916 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 105152 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 97025 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 94048 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 92817 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 5441 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 5084 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 5738 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 7709 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 7730 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 6924 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 6738 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 7452 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 5737 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 5138 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 4676 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 5004 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 4547 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 3838 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 3903 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 3022 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 2209 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 1452 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 1128 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 643 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 513 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 524 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 509 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 510 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 478 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 419 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 286 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 162 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 329 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 603787 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 286.780656 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 164.845955 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 326.273004 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 251324 41.62% 41.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 149673 24.79% 66.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 51779 8.58% 74.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 28017 4.64% 79.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 19714 3.27% 82.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 13055 2.16% 85.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 9885 1.64% 86.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 8959 1.48% 88.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 71381 11.82% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 603787 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 89136 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 10.358104 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 107.922360 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 89134 100.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 89136 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 89136 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.994379 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.728374 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 17.051434 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 87330 97.97% 97.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47 694 0.78% 98.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63 23 0.03% 98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79 47 0.05% 98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95 149 0.17% 99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 187 0.21% 99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127 322 0.36% 99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143 118 0.13% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159 42 0.05% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 62 0.07% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 32 0.04% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 11 0.01% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 9 0.01% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255 3 0.00% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 1 0.00% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 2 0.00% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 6 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 10 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 26 0.03% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 5 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::400-415 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::416-431 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::432-447 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::464-479 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 5 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-511 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 3 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 89136 # Writes before turning the bus around for reads
+system.physmem.totQLat 12043609520 # Total ticks spent queuing
+system.physmem.totMemAccLat 29355934520 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4616620000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 13043.75 # Average queueing delay per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 31793.75 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.20 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.26 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing
+system.physmem.readRowHits 694872 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1406883 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes
+system.physmem.avgGap 18797853.22 # Average gap between requests
+system.physmem.pageHitRate 77.68 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 2251693080 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1228602375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 3417133200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 5686258320 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1307306510865 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 29947912845000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 34652724495480 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.655841 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 49820369752426 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1730532440000 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 273552725074 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.physmem_1.actEnergy 2312936640 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1262019000 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3784755000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 5862520800 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1309001038785 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 29946426417000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 34653571139865 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.672178 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 49817859630672 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1730532440000 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 276069619328 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
+system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.walks 211321 # Table walker walks requested
+system.cpu.dtb.walker.walksLong 211321 # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15784 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3 163511 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples 211307 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean 0.170368 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 58.877055 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-2047 211305 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 211307 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 179309 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 23338.389317 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 19372.996771 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 15325.519359 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535 177365 98.92% 98.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071 1663 0.93% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607 114 0.06% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143 88 0.05% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679 58 0.03% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 179309 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples -200578036 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean -2.729096 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0 -747974796 372.91% 372.91% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::1 547396760 -272.91% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total -200578036 # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K 163512 91.20% 91.20% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M 15784 8.80% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 179296 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 211321 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 211321 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 179296 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 179296 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 390617 # Table walker requests started/completed, data/inst
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 167775531 # DTB read hits
+system.cpu.dtb.read_misses 155743 # DTB read misses
+system.cpu.dtb.write_hits 152648275 # DTB write hits
+system.cpu.dtb.write_misses 55578 # DTB write misses
+system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 75520 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 8371 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 19881 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 167931274 # DTB read accesses
+system.cpu.dtb.write_accesses 152703853 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 320423806 # DTB hits
+system.cpu.dtb.misses 211321 # DTB misses
+system.cpu.dtb.accesses 320635127 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.walks 122916 # Table walker walks requested
+system.cpu.itb.walker.walksLong 122916 # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3 110644 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples 122916 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0 122916 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 122916 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 111766 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 26583.507059 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 22687.613632 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 18325.329143 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-32767 56090 50.19% 50.19% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-65535 53429 47.80% 97.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-98303 753 0.67% 98.66% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::98304-131071 1184 1.06% 99.72% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-163839 19 0.02% 99.74% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::163840-196607 105 0.09% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::229376-262143 54 0.05% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-294911 30 0.03% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::294912-327679 11 0.01% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-360447 20 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::360448-393215 11 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-425983 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::491520-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total 111766 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples -853761296 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 -853761296 100.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total -853761296 # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K 110644 99.00% 99.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M 1122 1.00% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 111766 # Table walker page sizes translated
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122916 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 122916 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111766 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 111766 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 234682 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 894030670 # ITB inst hits
+system.cpu.itb.inst_misses 122916 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 53866 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 894153586 # ITB inst accesses
+system.cpu.itb.hits 894030670 # DTB hits
+system.cpu.itb.misses 122916 # DTB misses
+system.cpu.itb.accesses 894153586 # DTB accesses
+system.cpu.numCycles 103648924201 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 893481288 # Number of instructions committed
+system.cpu.committedOps 1049881338 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 963989017 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 895873 # Number of float alu accesses
+system.cpu.num_func_calls 52999943 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 136446519 # number of instructions that are conditional controls
+system.cpu.num_int_insts 963989017 # number of integer instructions
+system.cpu.num_fp_insts 895873 # number of float instructions
+system.cpu.num_int_register_reads 1405913792 # number of times the integer registers were read
+system.cpu.num_int_register_writes 764688301 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 1443674 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 760516 # number of times the floating registers were written
+system.cpu.num_cc_register_reads 234750393 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 234155899 # number of times the CC registers were written
+system.cpu.num_mem_refs 320407593 # number of memory refs
+system.cpu.num_load_insts 167768846 # Number of load instructions
+system.cpu.num_store_insts 152638747 # Number of store instructions
+system.cpu.num_idle_cycles 100474792122.552063 # Number of idle cycles
+system.cpu.num_busy_cycles 3174132078.447939 # Number of busy cycles
+system.cpu.not_idle_fraction 0.030624 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.969376 # Percentage of idle cycles
+system.cpu.Branches 199584978 # Number of branches fetched
+system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 727639004 69.27% 69.27% # Class of executed instruction
+system.cpu.op_class::IntMult 2217476 0.21% 69.48% # Class of executed instruction
+system.cpu.op_class::IntDiv 99175 0.01% 69.49% # Class of executed instruction
+system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 8 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 110553 0.01% 69.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction
+system.cpu.op_class::MemRead 167768846 15.97% 85.47% # Class of executed instruction
+system.cpu.op_class::MemWrite 152638747 14.53% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 1050473844 # Class of executed instruction
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 16327 # number of quiesce instructions executed
+system.cpu.dcache.tags.replacements 10213653 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.965664 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 310015199 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 10214165 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 30.351497 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 3500615250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.965664 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999933 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 1291569953 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1291569953 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 156758765 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 156758765 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 144836105 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 144836105 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 393576 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 393576 # number of SoftPFReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 334400 # number of WriteInvalidateReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::total 334400 # number of WriteInvalidateReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 3672090 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 3672090 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 3974747 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 3974747 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 301594870 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 301594870 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 301988446 # number of overall hits
+system.cpu.dcache.overall_hits::total 301988446 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 5315823 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 5315823 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2219045 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2219045 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 1297249 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 1297249 # number of SoftPFReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1232796 # number of WriteInvalidateReq misses
+system.cpu.dcache.WriteInvalidateReq_misses::total 1232796 # number of WriteInvalidateReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 304342 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 304342 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 7534868 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 7534868 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 8832117 # number of overall misses
+system.cpu.dcache.overall_misses::total 8832117 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 84066704475 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 84066704475 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 66382286210 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 66382286210 # number of WriteReq miss cycles
+system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 32849513005 # number of WriteInvalidateReq miss cycles
+system.cpu.dcache.WriteInvalidateReq_miss_latency::total 32849513005 # number of WriteInvalidateReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4463810234 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 4463810234 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 150448990685 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 150448990685 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 150448990685 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 150448990685 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 162074588 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 162074588 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 147055150 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 147055150 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 1690825 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 1690825 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1567196 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::total 1567196 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3976432 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 3976432 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 3974749 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 3974749 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 309129738 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 309129738 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 310820563 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 310820563 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032799 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.032799 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015090 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.015090 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767228 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.767228 # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786625 # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786625 # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076536 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076536 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.024374 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.024374 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.028415 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.028415 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15814.428824 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15814.428824 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29914.799479 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29914.799479 # average WriteReq miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 26646.349441 # average WriteInvalidateReq miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 26646.349441 # average WriteInvalidateReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14667.085825 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14667.085825 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19967.037337 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19967.037337 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17034.306802 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 17034.306802 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 7878976 # number of writebacks
+system.cpu.dcache.writebacks::total 7878976 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 16016 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 16016 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21118 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 21118 # number of WriteReq MSHR hits
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+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 7878976 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339565 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232795 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 45517 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 45519 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 2152414 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 2152414 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27593630 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28534080 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 622119 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 992785 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 57742614 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 880408660 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1158207750 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2038152 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 470306 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 32992382 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.003506 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.059104 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 32876724 99.65% 99.65% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 115658 0.35% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 32992382 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 20698021683 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 14320653166 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 367823750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy 617486750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 40333 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40333 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29907 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231024 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231024 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353808 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7492448 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 606968921 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 148463571 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks)
+system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.replacements 115493 # number of replacements
+system.iocache.tags.tagsinuse 10.456626 # Cycle average of tags in use
+system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 115509 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 13157260299000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.510556 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.946069 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.219410 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.434129 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.653539 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 1039965 # Number of tag accesses
+system.iocache.tags.data_accesses 1039965 # Number of data accesses
+system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8848 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8885 # number of ReadReq misses
+system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
+system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
+system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8848 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8888 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
+system.iocache.overall_misses::realview.ide 8848 # number of overall misses
+system.iocache.overall_misses::total 8888 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 1591055254 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 1596127254 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19834612096 # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total 19834612096 # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide 1591055254 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 1596479754 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide 1591055254 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 1596479754 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8848 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8885 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8848 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8888 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8848 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8888 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
+system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 179820.892179 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 179642.909848 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185954.137253 # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 185954.137253 # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 179621.934518 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 179621.934518 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 109316 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 16121 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 6.780969 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 0 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.writebacks::writebacks 106630 # number of writebacks
+system.iocache.writebacks::total 106630 # number of writebacks
+system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide 8848 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 8885 # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 8848 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 8888 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 8848 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 8888 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 1129796362 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 1132938362 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14288050130 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14288050130 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 1129796362 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 1133131862 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 1129796362 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 1133131862 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127689.462251 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 127511.351941 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133953.818814 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133953.818814 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 448489 # Transaction distribution
+system.membus.trans_dist::ReadResp 448489 # Transaction distribution
+system.membus.trans_dist::WriteReq 33710 # Transaction distribution
+system.membus.trans_dist::WriteResp 33710 # Transaction distribution
+system.membus.trans_dist::Writeback 1214153 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 616398 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 616398 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 36221 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 36223 # Transaction distribution
+system.membus.trans_dist::ReadExReq 512353 # Transaction distribution
+system.membus.trans_dist::ReadExResp 512353 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4040402 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4170106 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4505175 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 159663776 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 159833626 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 3324 # Total snoops (count)
+system.membus.snoop_fanout::samples 2750930 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2750930 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 2750930 # Request fanout histogram
+system.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 5171500 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 10418059043 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 5433894864 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer3.occupancy 151694929 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[ 0.000000] Initializing cgroup subsys cpu\r
+[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
+[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
+[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
+[ 0.000000] Memory limited to 256MB\r
+[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
+[ 0.000000] On node 0 totalpages: 65536\r
+[ 0.000000] DMA zone: 896 pages used for memmap\r
+[ 0.000000] DMA zone: 0 pages reserved\r
+[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
+[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
+[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
+[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
+[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
+[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
+[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
+[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
+[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
+[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
+[ 0.000000] Virtual kernel memory layout:\r
+[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
+[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
+[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
+[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
+[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
+[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
+[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
+[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
+[ 0.000000] Preemptible hierarchical RCU implementation.\r
+[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
+[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
+[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
+[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
+[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
+[ 0.000039] Console: colour dummy device 80x25\r
+[ 0.000042] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000045] pid_max: default: 32768 minimum: 301\r
+[ 0.000065] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000068] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000254] hw perfevents: no hardware support available\r
+[ 1.060134] CPU1: failed to come online\r
+[ 2.080264] CPU2: failed to come online\r
+[ 3.100395] CPU3: failed to come online\r
+[ 3.100400] Brought up 1 CPUs\r
+[ 3.100402] SMP: Total of 1 processors activated.\r
+[ 3.100500] devtmpfs: initialized\r
+[ 3.101762] atomic64_test: passed\r
+[ 3.101843] regulator-dummy: no parameters\r
+[ 3.102644] NET: Registered protocol family 16\r
+[ 3.102917] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 3.102927] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 3.103581] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 3.103585] Serial: AMBA PL011 UART driver\r
+[ 3.103931] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 3.103997] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 3.104547] console [ttyAMA0] enabled\r
+[ 3.104647] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 3.104695] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 3.104744] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 3.104789] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 3.130966] 3V3: 3300 mV \r
+[ 3.131042] vgaarb: loaded\r
+[ 3.131134] SCSI subsystem initialized\r
+[ 3.131205] libata version 3.00 loaded.\r
+[ 3.131293] usbcore: registered new interface driver usbfs\r
+[ 3.131321] usbcore: registered new interface driver hub\r
+[ 3.131375] usbcore: registered new device driver usb\r
+[ 3.131420] pps_core: LinuxPPS API ver. 1 registered\r
+[ 3.131429] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 3.131451] PTP clock support registered\r
+[ 3.131688] Switched to clocksource arch_sys_counter\r
+[ 3.133862] NET: Registered protocol family 2\r
+[ 3.134013] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 3.134040] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 3.134072] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 3.134099] TCP: reno registered\r
+[ 3.134107] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.134124] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.134187] NET: Registered protocol family 1\r
+[ 3.134256] RPC: Registered named UNIX socket transport module.\r
+[ 3.134266] RPC: Registered udp transport module.\r
+[ 3.134274] RPC: Registered tcp transport module.\r
+[ 3.134283] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 3.134296] PCI: CLS 0 bytes, default 64\r
+[ 3.134626] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 3.134832] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 3.138917] fuse init (API version 7.23)\r
+[ 3.139097] msgmni has been set to 469\r
+[ 3.143447] io scheduler noop registered\r
+[ 3.143560] io scheduler cfq registered (default)\r
+[ 3.144375] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.144389] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 3.144401] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 3.144415] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 3.144425] pci_bus 0000:00: scanning bus\r
+[ 3.144438] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 3.144452] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 3.144469] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.144534] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 3.144547] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 3.144560] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 3.144572] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 3.144584] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 3.144596] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 3.144609] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.144672] pci_bus 0000:00: fixups for bus\r
+[ 3.144681] pci_bus 0000:00: bus scan returning with max=00\r
+[ 3.144694] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 3.144718] pci 0000:00:00.0: fixup irq: got 33\r
+[ 3.144728] pci 0000:00:00.0: assigning IRQ 33\r
+[ 3.144741] pci 0000:00:01.0: fixup irq: got 34\r
+[ 3.144750] pci 0000:00:01.0: assigning IRQ 34\r
+[ 3.144764] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 3.144778] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 3.144792] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 3.144806] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.144818] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 3.144831] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 3.144844] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 3.144856] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 3.145803] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.146345] ata_piix 0000:00:01.0: version 2.13\r
+[ 3.146356] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 3.146386] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 3.146981] scsi0 : ata_piix\r
+[ 3.147177] scsi1 : ata_piix\r
+[ 3.147237] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 3.147249] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.147450] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.147462] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.147484] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.147496] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.301720] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 3.301730] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 3.301764] ata1.00: configured for UDMA/33\r
+[ 3.301835] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 3.302052] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 3.302087] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 3.302146] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 3.302156] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 3.302186] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 3.302399] sda: sda1\r
+[ 3.302620] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 3.422060] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 3.422074] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 3.422105] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 3.422115] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 3.422148] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 3.422160] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 3.422304] usbcore: registered new interface driver usb-storage\r
+[ 3.422400] mousedev: PS/2 mouse device common for all mice\r
+[ 3.422718] usbcore: registered new interface driver usbhid\r
+[ 3.422728] usbhid: USB HID core driver\r
+[ 3.422776] TCP: cubic registered\r
+[ 3.422785] NET: Registered protocol family 17\r
+\0[ 3.423371] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 3.423415] devtmpfs: mounted\r
+[ 3.423469] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+\0\0\rINIT: \0version 2.88 booting\0\r\r
+\0Starting udev\r
+[ 3.470498] udevd[607]: starting version 182\r
+Starting Bootlog daemon: bootlogd.\r\r
+[ 3.596627] random: dd urandom read with 22 bits of entropy available\r
+Populating dev cache\r\r
+net.ipv4.conf.default.rp_filter = 1\r\r
+net.ipv4.conf.all.rp_filter = 1\r\r
+hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
+Mon Jan 27 08:00:00 UTC 2014\r\r
+hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
+\rINIT: Entering runlevel: 5\r\r\r
+Configuring network interfaces... udhcpc (v1.21.1) started\r\r
+[ 3.801922] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+Sending discover...\r\r
+Sending discover...\r\r
+Sending discover...\r\r
+No lease, forking to background\r\r
+done.\r\r
+Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
+rpcbind: cannot create socket for tcp6\r\r\r
+done.\r\r
+rpcbind: cannot get uid of '': Success\r\r\r
+creating NFS state directory: done\r\r
+starting statd: done\r\r
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=true
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxArmSystem
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
+atags_addr=134217728
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+boot_release_addr=65528
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+early_kernel_symbols=false
+enable_context_switch_stats_dump=false
+eventq_index=0
+flags_addr=469827632
+gic_cpu_addr=738205696
+have_generic_timer=false
+have_large_asid_64=false
+have_lpae=false
+have_security=false
+have_virtualization=false
+highest_el_is_64=false
+init_param=0
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel_addr_check=true
+load_addr_mask=268435455
+load_offset=2147483648
+machine_type=VExpress_EMM64
+mem_mode=atomic
+mem_ranges=2147483648:2415919103
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
+multi_proc=true
+num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
+phys_addr_range_64=40
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+reset_addr_64=0
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.bridge]
+type=Bridge
+clk_domain=system.clk_domain
+delay=50000
+eventq_index=0
+ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
+req_size=16
+resp_size=16
+master=system.iobus.slave[0]
+slave=system.membus.master[0]
+
+[system.cf0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+eventq_index=0
+image=system.cf0.image
+
+[system.cf0.image]
+type=CowDiskImage
+children=child
+child=system.cf0.image.child
+eventq_index=0
+image_file=
+read_only=false
+table_size=65536
+
+[system.cf0.image.child]
+type=RawDiskImage
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+read_only=true
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu0.dstage2_mmu
+dtb=system.cpu0.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+istage2_mmu=system.cpu0.istage2_mmu
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+width=1
+workload=
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu0.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu0.dtb
+
+[system.cpu0.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu0.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu0.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[3]
+
+[system.cpu0.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=1
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu0.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu0.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu0.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu0.itb
+
+[system.cpu0.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu0.istage2_mmu.stage2_tlb.walker
+
+[system.cpu0.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu0.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.toL2Bus.slave[2]
+
+[system.cpu0.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu1]
+type=AtomicSimpleCPU
+children=dstage2_mmu dtb isa istage2_mmu itb tracer
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu1.dstage2_mmu
+dtb=system.cpu1.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=Null
+isa=system.cpu1.isa
+istage2_mmu=system.cpu1.istage2_mmu
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=true
+system=system
+tracer=system.cpu1.tracer
+width=1
+workload=
+
+[system.cpu1.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu1.dtb
+
+[system.cpu1.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu1.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+pmu=Null
+system=system
+
+[system.cpu1.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
+tlb=system.cpu1.itb
+
+[system.cpu1.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu1.istage2_mmu.stage2_tlb.walker
+
+[system.cpu1.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+
+[system.cpu1.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.intrctrl]
+type=IntrControl
+eventq_index=0
+sys=system
+
+[system.iobus]
+type=NoncoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=1
+frontend_latency=2
+response_latency=2
+use_default_range=true
+width=16
+default=system.realview.pciconfig.pio
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
+
+[system.iocache]
+type=BaseCache
+children=tags
+addr_ranges=2147483648:2415919103
+assoc=8
+clk_domain=system.clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=false
+hit_latency=50
+is_top_level=true
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=50
+sequential_access=false
+size=1024
+system=system
+tags=system.iocache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.master[27]
+mem_side=system.membus.slave[3]
+
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+hit_latency=50
+sequential_access=false
+size=1024
+
+[system.l2c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=4194304
+system=system
+tags=system.l2c.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[2]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=4194304
+
+[system.membus]
+type=CoherentXBar
+children=badaddr_responder
+clk_domain=system.clk_domain
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+response_latency=2
+snoop_filter=Null
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+default=system.membus.badaddr_responder.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
+slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
+
+[system.membus.badaddr_responder]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=0
+pio_latency=100000
+pio_size=8
+ret_bad_addr=true
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=warn
+pio=system.membus.default
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=2147483648:2415919103
+port=system.membus.master[5]
+
+[system.realview]
+type=RealView
+children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+eventq_index=0
+intrctrl=system.intrctrl
+pci_cfg_base=805306368
+pci_cfg_gen_offsets=true
+pci_io_base=788529152
+system=system
+
+[system.realview.aaci_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470024192
+pio_latency=100000
+system=system
+pio=system.iobus.master[18]
+
+[system.realview.cf_ctrl]
+type=IdeController
+BAR0=471465984
+BAR0LegacyIO=true
+BAR0Size=256
+BAR1=471466240
+BAR1LegacyIO=true
+BAR1Size=4096
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=1
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=31
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=2
+disks=
+eventq_index=0
+io_shift=2
+pci_bus=2
+pci_dev=0
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[9]
+dma=system.iobus.slave[2]
+pio=system.iobus.master[8]
+
+[system.realview.clcd]
+type=Pl111
+amba_id=1315089
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=46
+pio_addr=471793664
+pio_latency=10000
+pixel_clock=41667
+system=system
+vnc=system.vncserver
+dma=system.iobus.slave[1]
+pio=system.iobus.master[4]
+
+[system.realview.energy_ctrl]
+type=EnergyCtrl
+clk_domain=system.clk_domain
+dvfs_handler=system.dvfs_handler
+eventq_index=0
+pio_addr=470286336
+pio_latency=100000
+system=system
+pio=system.iobus.master[22]
+
+[system.realview.ethernet]
+type=IGbE
+BAR0=0
+BAR0LegacyIO=false
+BAR0Size=131072
+BAR1=0
+BAR1LegacyIO=false
+BAR1Size=0
+BAR2=0
+BAR2LegacyIO=false
+BAR2Size=0
+BAR3=0
+BAR3LegacyIO=false
+BAR3Size=0
+BAR4=0
+BAR4LegacyIO=false
+BAR4Size=0
+BAR5=0
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=2
+Command=0
+DeviceID=4213
+ExpansionROM=0
+HeaderType=0
+InterruptLine=1
+InterruptPin=1
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=255
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=0
+Revision=0
+Status=0
+SubClassCode=0
+SubsystemID=4104
+SubsystemVendorID=32902
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+eventq_index=0
+fetch_comp_delay=10000
+fetch_delay=10000
+hardware_address=00:90:00:00:00:01
+pci_bus=0
+pci_dev=0
+pci_func=0
+phy_epid=896
+phy_pid=680
+pio_latency=30000
+platform=system.realview
+rx_desc_cache_size=64
+rx_fifo_size=393216
+rx_write_delay=0
+system=system
+tx_desc_cache_size=64
+tx_fifo_size=393216
+tx_read_delay=0
+wb_comp_delay=10000
+wb_delay=10000
+config=system.iobus.master[26]
+dma=system.iobus.slave[4]
+pio=system.iobus.master[25]
+
+[system.realview.generic_timer]
+type=GenericTimer
+eventq_index=0
+gic=system.realview.gic
+int_num=29
+system=system
+
+[system.realview.gic]
+type=Pl390
+clk_domain=system.clk_domain
+cpu_addr=738205696
+cpu_pio_delay=10000
+dist_addr=738201600
+dist_pio_delay=10000
+eventq_index=0
+int_latency=10000
+it_lines=128
+msix_addr=0
+platform=system.realview
+system=system
+pio=system.membus.master[2]
+
+[system.realview.hdlcd]
+type=HDLcd
+amba_id=1314816
+clk_domain=system.clk_domain
+enable_capture=true
+eventq_index=0
+gic=system.realview.gic
+int_num=117
+pio_addr=721420288
+pio_latency=10000
+pixel_clock=7299
+system=system
+vnc=system.vncserver
+dma=system.membus.slave[0]
+pio=system.iobus.master[5]
+
+[system.realview.ide]
+type=IdeController
+BAR0=1
+BAR0LegacyIO=false
+BAR0Size=8
+BAR1=1
+BAR1LegacyIO=false
+BAR1Size=4
+BAR2=1
+BAR2LegacyIO=false
+BAR2Size=8
+BAR3=1
+BAR3LegacyIO=false
+BAR3Size=4
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CapabilityPtr=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=2
+InterruptPin=2
+LatencyTimer=0
+LegacyIOBase=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
+MaximumLatency=0
+MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
+ProgIF=133
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.cf0
+eventq_index=0
+io_shift=0
+pci_bus=0
+pci_dev=1
+pci_func=0
+pio_latency=30000
+platform=system.realview
+system=system
+config=system.iobus.master[24]
+dma=system.iobus.slave[3]
+pio=system.iobus.master[23]
+
+[system.realview.kmi0]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=44
+is_mouse=false
+pio_addr=470155264
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[6]
+
+[system.realview.kmi1]
+type=Pl050
+amba_id=1314896
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=1000000
+int_num=45
+is_mouse=true
+pio_addr=470220800
+pio_latency=100000
+system=system
+vnc=system.vncserver
+pio=system.iobus.master[7]
+
+[system.realview.l2x0_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=739246080
+pio_latency=100000
+pio_size=4095
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[12]
+
+[system.realview.lan_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=436207616
+pio_latency=100000
+pio_size=65535
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[19]
+
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=738721792
+pio_latency=100000
+system=system
+pio=system.membus.master[3]
+
+[system.realview.mmc_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470089728
+pio_latency=100000
+system=system
+pio=system.iobus.master[21]
+
+[system.realview.nvmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:67108863
+port=system.membus.master[1]
+
+[system.realview.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+eventq_index=0
+pio_addr=0
+pio_latency=30000
+platform=system.realview
+size=268435456
+system=system
+pio=system.iobus.default
+
+[system.realview.realview_io]
+type=RealViewCtrl
+clk_domain=system.clk_domain
+eventq_index=0
+idreg=35979264
+pio_addr=469827584
+pio_latency=100000
+proc_id0=335544320
+proc_id1=335544320
+system=system
+pio=system.iobus.master[1]
+
+[system.realview.rtc]
+type=PL031
+amba_id=3412017
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=36
+pio_addr=471269376
+pio_latency=100000
+system=system
+time=Thu Jan 1 00:00:00 2009
+pio=system.iobus.master[10]
+
+[system.realview.sp810_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=true
+pio_addr=469893120
+pio_latency=100000
+system=system
+pio=system.iobus.master[16]
+
+[system.realview.timer0]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=34
+int_num1=34
+pio_addr=470876160
+pio_latency=100000
+system=system
+pio=system.iobus.master[2]
+
+[system.realview.timer1]
+type=Sp804
+amba_id=1316868
+clk_domain=system.clk_domain
+clock0=1000000
+clock1=1000000
+eventq_index=0
+gic=system.realview.gic
+int_num0=35
+int_num1=35
+pio_addr=470941696
+pio_latency=100000
+system=system
+pio=system.iobus.master[3]
+
+[system.realview.uart]
+type=Pl011
+clk_domain=system.clk_domain
+end_on_eot=false
+eventq_index=0
+gic=system.realview.gic
+int_delay=100000
+int_num=37
+pio_addr=470351872
+pio_latency=100000
+platform=system.realview
+system=system
+terminal=system.terminal
+pio=system.iobus.master[0]
+
+[system.realview.uart1_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470417408
+pio_latency=100000
+system=system
+pio=system.iobus.master[13]
+
+[system.realview.uart2_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470482944
+pio_latency=100000
+system=system
+pio=system.iobus.master[14]
+
+[system.realview.uart3_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470548480
+pio_latency=100000
+system=system
+pio=system.iobus.master[15]
+
+[system.realview.usb_fake]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=452984832
+pio_latency=100000
+pio_size=131071
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[20]
+
+[system.realview.vgic]
+type=VGic
+clk_domain=system.clk_domain
+eventq_index=0
+gic=system.realview.gic
+hv_addr=738213888
+pio_delay=10000
+platform=system.realview
+ppint=25
+system=system
+vcpu_addr=738222080
+pio=system.membus.master[4]
+
+[system.realview.vram]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=false
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=402653184:436207615
+port=system.iobus.master[11]
+
+[system.realview.watchdog_fake]
+type=AmbaFake
+amba_id=0
+clk_domain=system.clk_domain
+eventq_index=0
+ignore_access=false
+pio_addr=470745088
+pio_latency=100000
+system=system
+pio=system.iobus.master[17]
+
+[system.terminal]
+type=Terminal
+eventq_index=0
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+response_latency=1
+snoop_filter=Null
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.l2c.cpu_side
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+
+[system.vncserver]
+type=VncServer
+eventq_index=0
+frame_capture=false
+number=0
+port=5900
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
+warn: Sockets disabled, not accepting vnc client connections
+warn: Sockets disabled, not accepting terminal connections
+warn: Sockets disabled, not accepting gdb connections
+warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
+warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
+warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 29 2014 15:46:15
+gem5 started Oct 29 2014 16:13:02
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic
+Selected 64-bit ARM architecture, updating default disk image...
+Global frequency set at 1000000000000 ticks per second
+ 0: system.cpu0.isa: ISA system set to: 0x5318b00 0x5318b00
+ 0: system.cpu1.isa: ISA system set to: 0x5318b00 0x5318b00
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 51.111153 # Number of seconds simulated
+sim_ticks 51111152682000 # Number of ticks simulated
+final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1095499 # Simulator instruction rate (inst/s)
+host_op_rate 1287391 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 56869697369 # Simulator tick rate (ticks/s)
+host_mem_usage 728040 # Number of bytes of host memory used
+host_seconds 898.74 # Real time elapsed on the host
+sim_insts 984570519 # Number of instructions simulated
+sim_ops 1157031967 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu0.dtb.walker 203392 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 187968 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 3328564 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 37865864 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 208384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 188288 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2234176 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 36967936 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory
+system.physmem.bytes_read::total 81626364 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 3328564 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 2234176 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 103043072 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
+system.physmem.bytes_written::total 103063652 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 3178 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2937 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 92416 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 591667 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 3256 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 2942 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 34909 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 577624 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1315832 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1610048 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1612621 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 3979 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 3678 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 65124 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 740853 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 4077 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 3684 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 43712 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 723285 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1597036 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 65124 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 43712 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2016058 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2016461 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2016058 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 3979 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 65124 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 741256 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 4077 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 3684 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 43712 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 723285 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3613497 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
+system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.dtb.walker.walks 144734 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 144734 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples 144734 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 144734 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 144734 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 107995 85.62% 85.62% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 18140 14.38% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 126135 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144734 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144734 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126135 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126135 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 270869 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.inst_hits 0 # ITB inst hits
+system.cpu0.dtb.inst_misses 0 # ITB inst misses
+system.cpu0.dtb.read_hits 91873100 # DTB read hits
+system.cpu0.dtb.read_misses 107254 # DTB read misses
+system.cpu0.dtb.write_hits 84300346 # DTB write hits
+system.cpu0.dtb.write_misses 37480 # DTB write misses
+system.cpu0.dtb.flush_tlb 51121 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 56998 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 5021 # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults 11101 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 91980354 # DTB read accesses
+system.cpu0.dtb.write_accesses 84337826 # DTB write accesses
+system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu0.dtb.hits 176173446 # DTB hits
+system.cpu0.dtb.misses 144734 # DTB misses
+system.cpu0.dtb.accesses 176318180 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu0.itb.walker.walks 70623 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 70623 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples 70623 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 70623 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 70623 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 62003 96.05% 96.05% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 2552 3.95% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 64555 # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70623 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70623 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64555 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64555 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 135178 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 493558289 # ITB inst hits
+system.cpu0.itb.inst_misses 70623 # ITB inst misses
+system.cpu0.itb.read_hits 0 # DTB read hits
+system.cpu0.itb.read_misses 0 # DTB read misses
+system.cpu0.itb.write_hits 0 # DTB write hits
+system.cpu0.itb.write_misses 0 # DTB write misses
+system.cpu0.itb.flush_tlb 51121 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 40618 # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses 0 # DTB read accesses
+system.cpu0.itb.write_accesses 0 # DTB write accesses
+system.cpu0.itb.inst_accesses 493628912 # ITB inst accesses
+system.cpu0.itb.hits 493558289 # DTB hits
+system.cpu0.itb.misses 70623 # DTB misses
+system.cpu0.itb.accesses 493628912 # DTB accesses
+system.cpu0.numCycles 98036732821 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.committedInsts 493343054 # Number of instructions committed
+system.cpu0.committedOps 579320783 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 530703417 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 453665 # Number of float alu accesses
+system.cpu0.num_func_calls 28504103 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 76145406 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 530703417 # number of integer instructions
+system.cpu0.num_fp_insts 453665 # number of float instructions
+system.cpu0.num_int_register_reads 784985742 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 421507499 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 741739 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 362084 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 133043946 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 132723498 # number of times the CC registers were written
+system.cpu0.num_mem_refs 176296730 # number of memory refs
+system.cpu0.num_load_insts 91967123 # Number of load instructions
+system.cpu0.num_store_insts 84329607 # Number of store instructions
+system.cpu0.num_idle_cycles 96926191341.047134 # Number of idle cycles
+system.cpu0.num_busy_cycles 1110541479.952863 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.011328 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.988672 # Percentage of idle cycles
+system.cpu0.Branches 110281342 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 402074699 69.37% 69.37% # Class of executed instruction
+system.cpu0.op_class::IntMult 1168928 0.20% 69.57% # Class of executed instruction
+system.cpu0.op_class::IntDiv 50558 0.01% 69.58% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 52783 0.01% 69.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction
+system.cpu0.op_class::MemRead 91967123 15.87% 85.45% # Class of executed instruction
+system.cpu0.op_class::MemWrite 84329607 14.55% 100.00% # Class of executed instruction
+system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu0.op_class::total 579643698 # Class of executed instruction
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 16775 # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements 11612141 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 340775537 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 29.345192 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 264.268132 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 247.731587 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.516149 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data 0.483851 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses 1421165468 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 1421165468 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 85681160 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data 85885886 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 171567046 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 79835128 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data 79687740 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 159522868 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 208530 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data 215328 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 423858 # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 146037 # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 191672 # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total 337709 # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2127418 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2183031 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 4310449 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2250403 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2312061 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 165516288 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data 165573626 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 331089914 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 165724818 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data 165788954 # number of overall hits
+system.cpu0.dcache.overall_hits::total 331513772 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 3015225 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data 2995068 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 6010293 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1305618 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data 1264641 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 2570259 # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 792908 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data 791180 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 1584088 # number of SoftPFReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 765143 # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 480206 # number of WriteInvalidateReq misses
+system.cpu0.dcache.WriteInvalidateReq_misses::total 1245349 # number of WriteInvalidateReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 123898 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 129919 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 253817 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 4320843 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data 4259709 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 8580552 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 5113751 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data 5050889 # number of overall misses
+system.cpu0.dcache.overall_misses::total 10164640 # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 88696385 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data 88880954 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 81140746 # number of WriteReq accesses(hits+misses)
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+system.cpu0.dcache.WriteInvalidateReq_accesses::total 1583058 # number of WriteInvalidateReq accesses(hits+misses)
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+system.cpu0.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses)
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+system.cpu0.dcache.ReadReq_miss_rate::total 0.033846 # miss rate for ReadReq accesses
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+system.cpu0.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.791769 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.786064 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788910 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839728 # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.714722 # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses
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+system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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+system.cpu0.dcache.writebacks::total 8921315 # number of writebacks
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 970865862 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 268.250565 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 243.734034 # Average occupied blocks per requestor
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+system.cpu0.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
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+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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+system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.dtb.walker.walks 143589 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 143589 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walkWaitTime::samples 143589 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 143589 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 143589 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walksPending::samples 1000001000 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 1000001000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 1000001000 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 106707 85.51% 85.51% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 18085 14.49% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 124792 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143589 # Table walker requests started/completed, data/inst
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+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143589 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124792 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124792 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 268381 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.inst_hits 0 # ITB inst hits
+system.cpu1.dtb.inst_misses 0 # ITB inst misses
+system.cpu1.dtb.read_hits 92120843 # DTB read hits
+system.cpu1.dtb.read_misses 106565 # DTB read misses
+system.cpu1.dtb.write_hits 83929435 # DTB write hits
+system.cpu1.dtb.write_misses 37024 # DTB write misses
+system.cpu1.dtb.flush_tlb 51112 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 56458 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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+system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults 10550 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 92227408 # DTB read accesses
+system.cpu1.dtb.write_accesses 83966459 # DTB write accesses
+system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
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+system.cpu1.dtb.misses 143589 # DTB misses
+system.cpu1.dtb.accesses 176193867 # DTB accesses
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+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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+system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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+system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu1.itb.walker.walks 69863 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 69863 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walkWaitTime::samples 69863 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 69863 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 69863 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 61226 95.98% 95.98% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 2567 4.02% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 63793 # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69863 # Table walker requests started/completed, data/inst
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+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63793 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63793 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 133656 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 491475383 # ITB inst hits
+system.cpu1.itb.inst_misses 69863 # ITB inst misses
+system.cpu1.itb.read_hits 0 # DTB read hits
+system.cpu1.itb.read_misses 0 # DTB read misses
+system.cpu1.itb.write_hits 0 # DTB write hits
+system.cpu1.itb.write_misses 0 # DTB write misses
+system.cpu1.itb.flush_tlb 51112 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 40934 # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses 0 # DTB read accesses
+system.cpu1.itb.write_accesses 0 # DTB write accesses
+system.cpu1.itb.inst_accesses 491545246 # ITB inst accesses
+system.cpu1.itb.hits 491475383 # DTB hits
+system.cpu1.itb.misses 69863 # DTB misses
+system.cpu1.itb.accesses 491545246 # DTB accesses
+system.cpu1.numCycles 97463064529 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.committedInsts 491227465 # Number of instructions committed
+system.cpu1.committedOps 577711184 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 529752049 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 427140 # Number of float alu accesses
+system.cpu1.num_func_calls 28552264 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 75795428 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 529752049 # number of integer instructions
+system.cpu1.num_fp_insts 427140 # number of float instructions
+system.cpu1.num_int_register_reads 779016428 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 420937292 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 677260 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 385836 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 131363112 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 131105905 # number of times the CC registers were written
+system.cpu1.num_mem_refs 176168876 # number of memory refs
+system.cpu1.num_load_insts 92213308 # Number of load instructions
+system.cpu1.num_store_insts 83955568 # Number of store instructions
+system.cpu1.num_idle_cycles 96357044010.669601 # Number of idle cycles
+system.cpu1.num_busy_cycles 1106020518.330400 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.011348 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.988652 # Percentage of idle cycles
+system.cpu1.Branches 109807220 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 400561917 69.30% 69.30% # Class of executed instruction
+system.cpu1.op_class::IntMult 1185819 0.21% 69.50% # Class of executed instruction
+system.cpu1.op_class::IntDiv 51201 0.01% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction
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+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 55039 0.01% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::MemRead 92213308 15.95% 85.48% # Class of executed instruction
+system.cpu1.op_class::MemWrite 83955568 14.52% 100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::total 578022895 # Class of executed instruction
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29851 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
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+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes)
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+system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use
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+system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
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+system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor
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+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.l2c.Writeback_hits::writebacks 8921315 # number of Writeback hits
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+system.l2c.WriteInvalidateReq_misses::total 551017 # number of WriteInvalidateReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 19994 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 19925 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 39919 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 415064 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 411444 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 826508 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker 3178 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker 2937 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 49315 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 592123 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker 3256 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker 2942 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 34922 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 578352 # number of demand (read+write) misses
+system.l2c.demand_misses::total 1267025 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker 3178 # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker 2937 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 49315 # number of overall misses
+system.l2c.overall_misses::cpu0.data 592123 # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker 3256 # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker 2942 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 34922 # number of overall misses
+system.l2c.overall_misses::cpu1.data 578352 # number of overall misses
+system.l2c.overall_misses::total 1267025 # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 282613 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 148194 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 7156510 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 3932031 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 280110 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 145702 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 7139648 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 3916167 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 23000975 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 8921315 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 8921315 # number of Writeback accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::cpu0.data 765143 # number of WriteInvalidateReq accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::cpu1.data 480206 # number of WriteInvalidateReq accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::total 1245349 # number of WriteInvalidateReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 25681 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 25461 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 51142 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 1279937 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 1239180 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 282613 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 148194 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 7156510 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 5211968 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 280110 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 145702 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 7139648 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 5155347 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 25520092 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 282613 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 148194 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 7156510 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 5211968 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 280110 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 145702 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 7139648 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 5155347 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 25520092 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019819 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.006891 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.045030 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.020192 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.004891 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.042620 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.548943 # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.272793 # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::total 0.442460 # miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.778552 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782569 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.780552 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.324285 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.332029 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.019819 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.006891 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.113608 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker 0.020192 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.004891 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.112185 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.049648 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.019819 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.006891 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.113608 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker 0.020192 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.004891 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.112185 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.049648 # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.writebacks::writebacks 1503417 # number of writebacks
+system.l2c.writebacks::total 1503417 # number of writebacks
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 526050 # Transaction distribution
+system.membus.trans_dist::ReadResp 526050 # Transaction distribution
+system.membus.trans_dist::WriteReq 33606 # Transaction distribution
+system.membus.trans_dist::WriteResp 33606 # Transaction distribution
+system.membus.trans_dist::Writeback 1610048 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 657676 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 657676 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution
+system.membus.trans_dist::ReadExReq 825949 # Transaction distribution
+system.membus.trans_dist::ReadExResp 825949 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5310719 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 5439911 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5777584 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 212730400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 212899450 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 227116986 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 3583531 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3583531 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 3583531 # Request fanout histogram
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq 23464706 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 23464706 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 51142 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 51143 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28678566 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32383249 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832126 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655216 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 63549157 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3328504 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 2239440306 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 116338 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 36240472 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 3.003188 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.056369 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 36124951 99.68% 99.68% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 36240472 # Request fanout histogram
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[ 0.000000] Initializing cgroup subsys cpu\r
+[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
+[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
+[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
+[ 0.000000] Memory limited to 256MB\r
+[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
+[ 0.000000] On node 0 totalpages: 65536\r
+[ 0.000000] DMA zone: 896 pages used for memmap\r
+[ 0.000000] DMA zone: 0 pages reserved\r
+[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
+[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
+[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
+[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
+[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
+[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
+[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
+[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
+[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
+[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
+[ 0.000000] Virtual kernel memory layout:\r
+[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
+[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
+[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
+[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
+[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
+[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
+[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
+[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
+[ 0.000000] Preemptible hierarchical RCU implementation.\r
+[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
+[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
+[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
+[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
+[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
+[ 0.000013] Console: colour dummy device 80x25\r
+[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000015] pid_max: default: 32768 minimum: 301\r
+[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000066] hw perfevents: no hardware support available\r
+[ 1.060049] CPU1: failed to come online\r
+[ 2.080098] CPU2: failed to come online\r
+[ 3.100148] CPU3: failed to come online\r
+[ 3.100150] Brought up 1 CPUs\r
+[ 3.100151] SMP: Total of 1 processors activated.\r
+[ 3.100177] devtmpfs: initialized\r
+[ 3.100579] atomic64_test: passed\r
+[ 3.100603] regulator-dummy: no parameters\r
+[ 3.100844] NET: Registered protocol family 16\r
+[ 3.100938] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 3.100941] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 3.100980] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 3.100981] Serial: AMBA PL011 UART driver\r
+[ 3.101103] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 3.101125] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 3.101160] console [ttyAMA0] enabled\r
+[ 3.101194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 3.101208] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 3.101222] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 3.101235] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 3.130356] 3V3: 3300 mV \r
+[ 3.130377] vgaarb: loaded\r
+[ 3.130406] SCSI subsystem initialized\r
+[ 3.130425] libata version 3.00 loaded.\r
+[ 3.130450] usbcore: registered new interface driver usbfs\r
+[ 3.130457] usbcore: registered new interface driver hub\r
+[ 3.130471] usbcore: registered new device driver usb\r
+[ 3.130482] pps_core: LinuxPPS API ver. 1 registered\r
+[ 3.130483] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 3.130487] PTP clock support registered\r
+[ 3.130559] Switched to clocksource arch_sys_counter\r
+[ 3.131204] NET: Registered protocol family 2\r
+[ 3.131250] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 3.131255] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 3.131259] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 3.131263] TCP: reno registered\r
+[ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.131281] NET: Registered protocol family 1\r
+[ 3.131310] RPC: Registered named UNIX socket transport module.\r
+[ 3.131311] RPC: Registered udp transport module.\r
+[ 3.131312] RPC: Registered tcp transport module.\r
+[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 3.131315] PCI: CLS 0 bytes, default 64\r
+[ 3.131413] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 3.131456] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 3.132687] fuse init (API version 7.23)\r
+[ 3.132738] msgmni has been set to 469\r
+[ 3.133992] io scheduler noop registered\r
+[ 3.134024] io scheduler cfq registered (default)\r
+[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 3.134301] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 3.134302] pci_bus 0000:00: scanning bus\r
+[ 3.134304] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 3.134306] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 3.134329] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 3.134336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.134354] pci_bus 0000:00: fixups for bus\r
+[ 3.134355] pci_bus 0000:00: bus scan returning with max=00\r
+[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 3.134361] pci 0000:00:00.0: fixup irq: got 33\r
+[ 3.134363] pci 0000:00:00.0: assigning IRQ 33\r
+[ 3.134365] pci 0000:00:01.0: fixup irq: got 34\r
+[ 3.134367] pci 0000:00:01.0: assigning IRQ 34\r
+[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 3.134372] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 3.134377] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.134813] ata_piix 0000:00:01.0: version 2.13\r
+[ 3.134815] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 3.134820] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 3.135009] scsi0 : ata_piix\r
+[ 3.135063] scsi1 : ata_piix\r
+[ 3.135081] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 3.135082] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.135143] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.135144] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.135148] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.135150] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.290565] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 3.290566] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 3.290572] ata1.00: configured for UDMA/33\r
+[ 3.290589] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 3.290650] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 3.290658] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 3.290672] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 3.290673] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 3.290680] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 3.290733] sda: sda1\r
+[ 3.290795] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 3.410824] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 3.410825] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 3.410832] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 3.410833] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 3.410841] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 3.410842] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 3.410886] usbcore: registered new interface driver usb-storage\r
+[ 3.410912] mousedev: PS/2 mouse device common for all mice\r
+[ 3.411009] usbcore: registered new interface driver usbhid\r
+[ 3.411010] usbhid: USB HID core driver\r
+[ 3.411025] TCP: cubic registered\r
+[ 3.411026] NET: Registered protocol family 17\r
+\0[ 3.411204] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 3.411214] devtmpfs: mounted\r
+[ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+\0\0\rINIT: \0version 2.88 booting\0\r\r
+\0Starting udev\r
+[ 3.446950] udevd[607]: starting version 182\r
+Starting Bootlog daemon: bootlogd.\r\r
+[ 3.532262] random: dd urandom read with 19 bits of entropy available\r
+Populating dev cache\r\r
+net.ipv4.conf.default.rp_filter = 1\r\r
+net.ipv4.conf.all.rp_filter = 1\r\r
+hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
+Mon Jan 27 08:00:00 UTC 2014\r\r
+hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
+\rINIT: Entering runlevel: 5\r\r\r
+Configuring network interfaces... udhcpc (v1.21.1) started\r\r
+[ 3.640780] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+Sending discover...\r\r
+Sending discover...\r\r
+Sending discover...\r\r
+No lease, forking to background\r\r
+done.\r\r
+Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
+rpcbind: cannot create socket for tcp6\r\r\r
+done.\r\r
+rpcbind: cannot get uid of '': Success\r\r\r
+creating NFS state directory: done\r\r
+starting statd: done\r\r
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 18:27:58
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Exiting @ tick 44221003000 because target called exit()
+++ /dev/null
-
- SYSTEM TYPE...
- __ZTC__ := False
- __UNIX__ := True
- __RISC__ := True
- SPEC_CPU2000_LP64 := True
- __MAC__ := False
- __BCC__ := False
- __BORLANDC__ := False
- __GUI__ := False
- __WTC__ := False
- __HP__ := False
-
- CODE OPTIONS...
- __MACROIZE_HM__ := True
- __MACROIZE_MEM__ := True
- ENV01 := True
- USE_HPP_STYPE_HDRS := False
- USE_H_STYPE_HDRS := False
-
- CODE INCLUSION PARAMETERS...
- INCLUDE_ALL_CODE := False
- INCLUDE_DELETE_CODE := True
- __SWAP_GRP_POS__ := True
- __INCLUDE_MTRX__ := False
- __BAD_CODE__ := False
- API_INCLUDE := False
- BE_CAREFUL := False
- OLDWAY := False
- NOTUSED := False
-
- SYSTEM PARAMETERS...
- EXT_ENUM := 999999999L
- CHUNK_CONSTANT := 55555555
- CORE_CONSTANT := 55555555
- CORE_LIMIT := 20971520
- CorePage_Size := 384000
- ALIGN_BYTES := True
- CORE_BLOCK_ALIGN := 8
- FAR_MEM := False
-
- MEMORY MANAGEMENT PARAMETERS...
- SYSTEM_ALLOC := True
- SYSTEM_FREESTORE := True
- __NO_DISKCACHE__ := False
- __FREEZE_VCHUNKS__ := True
- __FREEZE_GRP_PACKETS__ := True
- __MINIMIZE_TREE_CACHE__:= True
-
- SYSTEM STD PARAMETERS...
- __STDOUT__ := False
- NULL := 0
- LPTR := False
- False_Status := 1
- True_Status := 0
- LARGE := True
- TWOBYTE_BOOL := False
- __NOSTR__ := False
-
- MEMORY VALIDATION PARAMETERS...
- CORE_CRC_CHECK := False
- VALIDATE_MEM_CHUNKS := False
-
- SYSTEM DEBUG OPTIONS...
- DEBUG := False
- MCSTAT := False
- TRACKBACK := False
- FLUSH_FILES := False
- DEBUG_CORE0 := False
- DEBUG_RISC := False
- __TREE_BUG__ := False
- __TRACK_FILE_READS__ := False
- PAGE_SPACE := False
- LEAVE_NO_TRACE := True
- NULL_TRACE_STRS := False
-
- TIME PARAMETERS...
- CLOCK_IS_LONG := False
- __DISPLAY_TIME__ := False
- __TREE_TIME__ := False
- __DISPLAY_ERRORS__ := False
-
- API MACROS...
- __BMT01__ := True
- OPTIMIZE := True
-
- END OF DEFINES.
-
-
-
- ... IMPLODE MEMORY ...
-
- SWAP to DiskCache := False
-
- FREEZE_GRP_PACKETS:= True
-
- QueBug := 1000
-
- sizeof(boolean) = 4
- sizeof(sizetype) = 4
- sizeof(chunkstruc) = 32
-
- sizeof(shorttype ) = 2
- sizeof(idtype ) = 2
- sizeof(sizetype ) = 4
- sizeof(indextype ) = 4
- sizeof(numtype ) = 4
- sizeof(handletype) = 4
- sizeof(tokentype ) = 8
-
- sizeof(short ) = 2
- sizeof(int ) = 4
-
- sizeof(lt64 ) = 4
- sizeof(farlongtype) = 4
- sizeof(long ) = 8
- sizeof(longaddr ) = 8
-
- sizeof(float ) = 4
- sizeof(double ) = 8
-
- sizeof(addrtype ) = 8
- sizeof(char * ) = 8
- ALLOC CORE_1 :: 16
- BHOOLE NATH
-
- OPEN File ./input/lendian.rnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 2030c0
- DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
- DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
- DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
- DB Handle Chunk's StackPtr = 20797
-
- DB[ 1] LOADED; Handles= 20797
- KERNEL in CORE[ 1] Restored @ 4005c800
-
- OPEN File ./input/lendian.wnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 21c40
- DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
- DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
- DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
- DB Handle Chunk's StackPtr = 17
-
- DB[ 2] LOADED; Handles= 17
- VORTEx_Status == -8 || fffffff8
-
- BE HERE NOW !!!
-
-
-
- ... VORTEx ON LINE ...
-
-
- ... END OF SESSION ...
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.044221 # Number of seconds simulated
-sim_ticks 44221003000 # Number of ticks simulated
-final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2813944 # Simulator instruction rate (inst/s)
-host_op_rate 2813942 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1408584494 # Simulator tick rate (ticks/s)
-host_mem_usage 287952 # Number of bytes of host memory used
-host_seconds 31.39 # Real time elapsed on the host
-sim_insts 88340673 # Number of instructions simulated
-sim_ops 88340673 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory
-system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 353752292 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 353752292 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 91652896 # Number of bytes written to this memory
-system.physmem.bytes_written::total 91652896 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 88438073 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 20276638 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 108714711 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 14613377 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 14613377 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7999644241 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2865214229 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 10864858470 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7999644241 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7999644241 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 2072610067 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2072610067 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 108714711 # Transaction distribution
-system.membus.trans_dist::ReadResp 108714711 # Transaction distribution
-system.membus.trans_dist::WriteReq 14613377 # Transaction distribution
-system.membus.trans_dist::WriteResp 14613377 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 123328088 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram
-system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 123328088 # Request fanout histogram
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 20276638 # DTB read hits
-system.cpu.dtb.read_misses 90148 # DTB read misses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 20366786 # DTB read accesses
-system.cpu.dtb.write_hits 14613377 # DTB write hits
-system.cpu.dtb.write_misses 7252 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 14620629 # DTB write accesses
-system.cpu.dtb.data_hits 34890015 # DTB hits
-system.cpu.dtb.data_misses 97400 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 34987415 # DTB accesses
-system.cpu.itb.fetch_hits 88438073 # ITB hits
-system.cpu.itb.fetch_misses 3934 # ITB misses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 88442007 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 4583 # Number of system calls
-system.cpu.numCycles 88442007 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 88340673 # Number of instructions committed
-system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
-system.cpu.num_func_calls 3321606 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
-system.cpu.num_int_insts 78039444 # number of integer instructions
-system.cpu.num_fp_insts 267757 # number of float instructions
-system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
-system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
-system.cpu.num_mem_refs 34987415 # number of memory refs
-system.cpu.num_load_insts 20366786 # Number of load instructions
-system.cpu.num_store_insts 14620629 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 88442007 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 13754477 # Number of branches fetched
-system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction
-system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction
-system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction
-system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction
-system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction
-system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction
-system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction
-system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction
-system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 88438073 # Class of executed instruction
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=262144
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_top_level=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 18:28:33
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Exiting @ tick 133634727000 because target called exit()
+++ /dev/null
-
- SYSTEM TYPE...
- __ZTC__ := False
- __UNIX__ := True
- __RISC__ := True
- SPEC_CPU2000_LP64 := True
- __MAC__ := False
- __BCC__ := False
- __BORLANDC__ := False
- __GUI__ := False
- __WTC__ := False
- __HP__ := False
-
- CODE OPTIONS...
- __MACROIZE_HM__ := True
- __MACROIZE_MEM__ := True
- ENV01 := True
- USE_HPP_STYPE_HDRS := False
- USE_H_STYPE_HDRS := False
-
- CODE INCLUSION PARAMETERS...
- INCLUDE_ALL_CODE := False
- INCLUDE_DELETE_CODE := True
- __SWAP_GRP_POS__ := True
- __INCLUDE_MTRX__ := False
- __BAD_CODE__ := False
- API_INCLUDE := False
- BE_CAREFUL := False
- OLDWAY := False
- NOTUSED := False
-
- SYSTEM PARAMETERS...
- EXT_ENUM := 999999999L
- CHUNK_CONSTANT := 55555555
- CORE_CONSTANT := 55555555
- CORE_LIMIT := 20971520
- CorePage_Size := 384000
- ALIGN_BYTES := True
- CORE_BLOCK_ALIGN := 8
- FAR_MEM := False
-
- MEMORY MANAGEMENT PARAMETERS...
- SYSTEM_ALLOC := True
- SYSTEM_FREESTORE := True
- __NO_DISKCACHE__ := False
- __FREEZE_VCHUNKS__ := True
- __FREEZE_GRP_PACKETS__ := True
- __MINIMIZE_TREE_CACHE__:= True
-
- SYSTEM STD PARAMETERS...
- __STDOUT__ := False
- NULL := 0
- LPTR := False
- False_Status := 1
- True_Status := 0
- LARGE := True
- TWOBYTE_BOOL := False
- __NOSTR__ := False
-
- MEMORY VALIDATION PARAMETERS...
- CORE_CRC_CHECK := False
- VALIDATE_MEM_CHUNKS := False
-
- SYSTEM DEBUG OPTIONS...
- DEBUG := False
- MCSTAT := False
- TRACKBACK := False
- FLUSH_FILES := False
- DEBUG_CORE0 := False
- DEBUG_RISC := False
- __TREE_BUG__ := False
- __TRACK_FILE_READS__ := False
- PAGE_SPACE := False
- LEAVE_NO_TRACE := True
- NULL_TRACE_STRS := False
-
- TIME PARAMETERS...
- CLOCK_IS_LONG := False
- __DISPLAY_TIME__ := False
- __TREE_TIME__ := False
- __DISPLAY_ERRORS__ := False
-
- API MACROS...
- __BMT01__ := True
- OPTIMIZE := True
-
- END OF DEFINES.
-
-
-
- ... IMPLODE MEMORY ...
-
- SWAP to DiskCache := False
-
- FREEZE_GRP_PACKETS:= True
-
- QueBug := 1000
-
- sizeof(boolean) = 4
- sizeof(sizetype) = 4
- sizeof(chunkstruc) = 32
-
- sizeof(shorttype ) = 2
- sizeof(idtype ) = 2
- sizeof(sizetype ) = 4
- sizeof(indextype ) = 4
- sizeof(numtype ) = 4
- sizeof(handletype) = 4
- sizeof(tokentype ) = 8
-
- sizeof(short ) = 2
- sizeof(int ) = 4
-
- sizeof(lt64 ) = 4
- sizeof(farlongtype) = 4
- sizeof(long ) = 8
- sizeof(longaddr ) = 8
-
- sizeof(float ) = 4
- sizeof(double ) = 8
-
- sizeof(addrtype ) = 8
- sizeof(char * ) = 8
- ALLOC CORE_1 :: 16
- BHOOLE NATH
-
- OPEN File ./input/lendian.rnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 2030c0
- DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
- DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
- DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
- DB Handle Chunk's StackPtr = 20797
-
- DB[ 1] LOADED; Handles= 20797
- KERNEL in CORE[ 1] Restored @ 4005c800
-
- OPEN File ./input/lendian.wnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 21c40
- DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
- DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
- DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
- DB Handle Chunk's StackPtr = 17
-
- DB[ 2] LOADED; Handles= 17
- VORTEx_Status == -8 || fffffff8
-
- BE HERE NOW !!!
-
-
-
- ... VORTEx ON LINE ...
-
-
- ... END OF SESSION ...
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.133634 # Number of seconds simulated
-sim_ticks 133634149500 # Number of ticks simulated
-final_tick 133634149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1329181 # Simulator instruction rate (inst/s)
-host_op_rate 1329181 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2010669405 # Simulator tick rate (ticks/s)
-host_mem_usage 301232 # Number of bytes of host memory used
-host_seconds 66.46 # Real time elapsed on the host
-sim_insts 88340673 # Number of instructions simulated
-sim_ops 88340673 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10136896 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10569792 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 432896 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 432896 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7294848 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7294848 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 6764 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 158389 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 165153 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 113982 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 113982 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 3239411 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 75855581 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 79094992 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 3239411 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 3239411 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 54588202 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 54588202 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 54588202 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 3239411 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 75855581 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 133683195 # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 20276638 # DTB read hits
-system.cpu.dtb.read_misses 90148 # DTB read misses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 20366786 # DTB read accesses
-system.cpu.dtb.write_hits 14613377 # DTB write hits
-system.cpu.dtb.write_misses 7252 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 14620629 # DTB write accesses
-system.cpu.dtb.data_hits 34890015 # DTB hits
-system.cpu.dtb.data_misses 97400 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 34987415 # DTB accesses
-system.cpu.itb.fetch_hits 88438074 # ITB hits
-system.cpu.itb.fetch_misses 3934 # ITB misses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 88442008 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 4583 # Number of system calls
-system.cpu.numCycles 267268299 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 88340673 # Number of instructions committed
-system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
-system.cpu.num_func_calls 3321606 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
-system.cpu.num_int_insts 78039444 # number of integer instructions
-system.cpu.num_fp_insts 267757 # number of float instructions
-system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
-system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
-system.cpu.num_mem_refs 34987415 # number of memory refs
-system.cpu.num_load_insts 20366786 # Number of load instructions
-system.cpu.num_store_insts 14620629 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 267268299 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 13754477 # Number of branches fetched
-system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction
-system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction
-system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction
-system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction
-system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction
-system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction
-system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction
-system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction
-system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction
-system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 88438073 # Class of executed instruction
-system.cpu.dcache.tags.replacements 200248 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4078.863526 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 936464000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863526 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.441159 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.834957 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52507.717670 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.084046 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.084046 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52501.668150 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52501.668150 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 113982 # number of writebacks
-system.cpu.l2cache.writebacks::total 113982 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 6764 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27508 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 34272 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130881 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 130881 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 6764 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 158389 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 165153 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 158389 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 165153 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 274073000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1114207000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1388280000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5300691500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5300691500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 274073000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6414898500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 6688971500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 274073000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6414898500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 6688971500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.452687 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.249792 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911567 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911567 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.588194 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.588194 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.367238 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40504.834957 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40507.703081 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.084046 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.084046 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152872 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577063 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 729935 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 449155 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 449155 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 449155 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 34272 # Transaction distribution
-system.membus.trans_dist::ReadResp 34272 # Transaction distribution
-system.membus.trans_dist::Writeback 113982 # Transaction distribution
-system.membus.trans_dist::ReadExReq 130881 # Transaction distribution
-system.membus.trans_dist::ReadExResp 130881 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 279135 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 279135 # Request fanout histogram
-system.membus.reqLayer0.occupancy 748161500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 825765500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-port=system.membus.slave[6]
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.membus.slave[4]
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-port=system.membus.slave[5]
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.membus.slave[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 18:03:38
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x49b6380
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Exiting @ tick 53932157000 because target called exit()
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.048960 # Number of seconds simulated
-sim_ticks 48960011000 # Number of ticks simulated
-final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1566427 # Simulator instruction rate (inst/s)
-host_op_rate 2003243 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1081494789 # Simulator tick rate (ticks/s)
-host_mem_usage 308080 # Number of bytes of host memory used
-host_seconds 45.27 # Real time elapsed on the host
-sim_insts 70913181 # Number of instructions simulated
-sim_ops 90688136 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory
-system.physmem.bytes_read::total 419153617 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 312580272 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 312580272 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory
-system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 78145068 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 101064798 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 6384399546 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2176742669 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 8561142215 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 6384399546 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 6384399546 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1606621596 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1606621596 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 6384399546 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3783364264 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 10167763810 # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 97920023 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 70913181 # Number of instructions committed
-system.cpu.committedOps 90688136 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
-system.cpu.num_func_calls 3311620 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls
-system.cpu.num_int_insts 81528488 # number of integer instructions
-system.cpu.num_fp_insts 56 # number of float instructions
-system.cpu.num_int_register_reads 141479310 # number of times the integer registers were read
-system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 266608028 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written
-system.cpu.num_mem_refs 43422001 # number of memory refs
-system.cpu.num_load_insts 22866262 # Number of load instructions
-system.cpu.num_store_insts 20555739 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 97920022.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 13741485 # Number of branches fetched
-system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction
-system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction
-system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 90690083 # Class of executed instruction
-system.membus.trans_dist::ReadReq 100925135 # Transaction distribution
-system.membus.trans_dist::ReadResp 100941054 # Transaction distribution
-system.membus.trans_dist::WriteReq 19849901 # Transaction distribution
-system.membus.trans_dist::WriteResp 19849901 # Transaction distribution
-system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution
-system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution
-system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution
-system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution
-system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290136 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 241861236 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580272 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 120930618 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram
-system.membus.snoop_fanout::3 78145068 64.62% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
-system.membus.snoop_fanout::total 120930618 # Request fanout histogram
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=262144
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-port=system.cpu.toL2Bus.slave[5]
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-port=system.cpu.toL2Bus.slave[4]
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_top_level=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex lendian.raw
-cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 18:04:30
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x5604d00
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Exiting @ tick 132689045000 because target called exit()
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.127293 # Number of seconds simulated
-sim_ticks 127293405500 # Number of ticks simulated
-final_tick 127293405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 802256 # Simulator instruction rate (inst/s)
-host_op_rate 1024256 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1451138855 # Simulator tick rate (ticks/s)
-host_mem_usage 317568 # Number of bytes of host memory used
-host_seconds 87.72 # Real time elapsed on the host
-sim_insts 70373628 # Number of instructions simulated
-sim_ops 89847362 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory
-system.physmem.bytes_read::total 8179968 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 255488 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 255488 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5370176 # Number of bytes written to this memory
-system.physmem.bytes_written::total 5370176 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3992 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2007080 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 62253657 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 64260737 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2007080 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2007080 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 42187386 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 42187386 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 42187386 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2007080 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 62253657 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 106448122 # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 254586811 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 70373628 # Number of instructions committed
-system.cpu.committedOps 89847362 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
-system.cpu.num_func_calls 3311620 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls
-system.cpu.num_int_insts 81528488 # number of integer instructions
-system.cpu.num_fp_insts 56 # number of float instructions
-system.cpu.num_int_register_reads 141328474 # number of times the integer registers were read
-system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 334802003 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written
-system.cpu.num_mem_refs 43422001 # number of memory refs
-system.cpu.num_load_insts 22866262 # Number of load instructions
-system.cpu.num_store_insts 20555739 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 254586810.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 13741485 # Number of branches fetched
-system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction
-system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction
-system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction
-system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 90690083 # Class of executed instruction
-system.cpu.dcache.tags.replacements 155902 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4076.389361 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 42608169 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 266.304385 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 1061070000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389361 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 22749839 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 22749839 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 83623 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 42492708 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 42492708 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 42576331 # number of overall hits
-system.cpu.dcache.overall_hits::total 42576331 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 30228 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 30228 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data 137260 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 137260 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 177381 # number of overall misses
-system.cpu.dcache.overall_misses::total 177381 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 517066000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 517066000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689116000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 5689116000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 6206182000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 6206182000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 6206182000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 6206182000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324226 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.324226 # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17105.531295 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17105.531295 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.412064 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.412064 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45214.789451 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45214.789451 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 34987.862285 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 34987.862285 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks
-system.cpu.dcache.writebacks::total 128239 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1120 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1120 # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1120 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1120 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1120 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1120 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 457995500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 457995500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5528568000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5528568000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1058278000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1058278000 # number of SoftPFReq MSHR miss cycles
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.063551 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.063551 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37816 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 448235 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 486051 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 307145 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 25532 # Transaction distribution
-system.membus.trans_dist::ReadResp 25532 # Transaction distribution
-system.membus.trans_dist::Writeback 83909 # Transaction distribution
-system.membus.trans_dist::ReadExReq 102280 # Transaction distribution
-system.membus.trans_dist::ReadExResp 102280 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 214640 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 214640 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 214640 # Request fanout histogram
-system.membus.reqLayer0.occupancy 566253984 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
-system.membus.respLayer1.occupancy 642220500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.dtb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.interrupts]
-type=SparcInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=SparcISA
-eventq_index=0
-
-[system.cpu.itb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex bendian.raw
-cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: ignoring syscall time(4026528248, 4026527848, ...)
-warn: ignoring syscall time(1375098, 4026527400, ...)
-warn: ignoring syscall time(1, 4026527312, ...)
-warn: ignoring syscall time(413, 4026527048, ...)
-warn: ignoring syscall time(414, 4026527048, ...)
-warn: ignoring syscall time(4026527688, 4026527288, ...)
-warn: ignoring syscall time(1375098, 4026526840, ...)
-warn: ignoring syscall time(409, 4026527048, ...)
-warn: ignoring syscall time(409, 4026527048, ...)
-warn: ignoring syscall time(409, 4026526960, ...)
-warn: ignoring syscall time(409, 4026527040, ...)
-warn: ignoring syscall time(409, 4026527000, ...)
-warn: ignoring syscall time(409, 4026526984, ...)
-warn: ignoring syscall time(409, 4026526984, ...)
-warn: ignoring syscall time(409, 4026526872, ...)
-warn: ignoring syscall time(19045, 4026526312, ...)
-warn: ignoring syscall time(409, 4026526832, ...)
-warn: ignoring syscall time(409, 4026526872, ...)
-warn: ignoring syscall time(409, 4026526872, ...)
-warn: ignoring syscall time(409, 4026526848, ...)
-warn: ignoring syscall time(409, 4026526840, ...)
-warn: ignoring syscall time(409, 4026526872, ...)
-warn: ignoring syscall time(409, 4026526856, ...)
-warn: ignoring syscall time(409, 4026526848, ...)
-warn: ignoring syscall time(409, 4026526936, ...)
-warn: ignoring syscall time(4026527408, 4026527008, ...)
-warn: ignoring syscall time(1375098, 4026526560, ...)
-warn: ignoring syscall time(18732, 4026527184, ...)
-warn: ignoring syscall time(409, 4026526632, ...)
-warn: ignoring syscall time(0, 4026526736, ...)
-warn: ignoring syscall time(0, 4026527320, ...)
-warn: ignoring syscall time(225, 4026527744, ...)
-warn: ignoring syscall time(409, 4026527048, ...)
-warn: ignoring syscall time(409, 4026526856, ...)
-warn: ignoring syscall time(409, 4026526872, ...)
-warn: ignoring syscall time(4026527496, 4026527096, ...)
-warn: ignoring syscall time(1375098, 4026526648, ...)
-warn: ignoring syscall time(0, 4026526824, ...)
-warn: ignoring syscall time(0, 4026527320, ...)
-warn: ignoring syscall time(1879089152, 4026527184, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall time(1595768, 4026527472, ...)
-warn: ignoring syscall time(17300, 4026526912, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(19045, 4026526912, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(19045, 4026526912, ...)
-warn: ignoring syscall time(17300, 4026526912, ...)
-warn: ignoring syscall time(20500, 4026525968, ...)
-warn: ignoring syscall time(4026526436, 4026525968, ...)
-warn: ignoring syscall time(7004192, 4026526056, ...)
-warn: ignoring syscall time(4, 4026527512, ...)
-warn: ignoring syscall time(0, 4026525760, ...)
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 22 2014 17:04:27
-gem5 started Jan 22 2014 19:46:20
-gem5 executing on u200540-lin
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Exiting @ tick 68148672000 because target called exit()
+++ /dev/null
-
- SYSTEM TYPE...
- __ZTC__ := False
- __UNIX__ := True
- __RISC__ := True
- SPEC_CPU2000_LP64 := False
- __MAC__ := False
- __BCC__ := False
- __BORLANDC__ := False
- __GUI__ := False
- __WTC__ := False
- __HP__ := False
-
- CODE OPTIONS...
- __MACROIZE_HM__ := True
- __MACROIZE_MEM__ := True
- ENV01 := True
- USE_HPP_STYPE_HDRS := False
- USE_H_STYPE_HDRS := False
-
- CODE INCLUSION PARAMETERS...
- INCLUDE_ALL_CODE := False
- INCLUDE_DELETE_CODE := True
- __SWAP_GRP_POS__ := True
- __INCLUDE_MTRX__ := False
- __BAD_CODE__ := False
- API_INCLUDE := False
- BE_CAREFUL := False
- OLDWAY := False
- NOTUSED := False
-
- SYSTEM PARAMETERS...
- EXT_ENUM := 999999999L
- CHUNK_CONSTANT := 55555555
- CORE_CONSTANT := 55555555
- CORE_LIMIT := 20971520
- CorePage_Size := 384000
- ALIGN_BYTES := True
- CORE_BLOCK_ALIGN := 8
- FAR_MEM := False
-
- MEMORY MANAGEMENT PARAMETERS...
- SYSTEM_ALLOC := True
- SYSTEM_FREESTORE := True
- __NO_DISKCACHE__ := False
- __FREEZE_VCHUNKS__ := True
- __FREEZE_GRP_PACKETS__ := True
- __MINIMIZE_TREE_CACHE__:= True
-
- SYSTEM STD PARAMETERS...
- __STDOUT__ := False
- NULL := 0
- LPTR := False
- False_Status := 1
- True_Status := 0
- LARGE := True
- TWOBYTE_BOOL := False
- __NOSTR__ := False
-
- MEMORY VALIDATION PARAMETERS...
- CORE_CRC_CHECK := False
- VALIDATE_MEM_CHUNKS := False
-
- SYSTEM DEBUG OPTIONS...
- DEBUG := False
- MCSTAT := False
- TRACKBACK := False
- FLUSH_FILES := False
- DEBUG_CORE0 := False
- DEBUG_RISC := False
- __TREE_BUG__ := False
- __TRACK_FILE_READS__ := False
- PAGE_SPACE := False
- LEAVE_NO_TRACE := True
- NULL_TRACE_STRS := False
-
- TIME PARAMETERS...
- CLOCK_IS_LONG := False
- __DISPLAY_TIME__ := False
- __TREE_TIME__ := False
- __DISPLAY_ERRORS__ := False
-
- API MACROS...
- __BMT01__ := True
- OPTIMIZE := True
-
- END OF DEFINES.
-
-
-
- ... IMPLODE MEMORY ...
-
- SWAP to DiskCache := False
-
- FREEZE_GRP_PACKETS:= True
-
- QueBug := 1000
-
- sizeof(boolean) = 4
- sizeof(sizetype) = 4
- sizeof(chunkstruc) = 32
-
- sizeof(shorttype ) = 2
- sizeof(idtype ) = 2
- sizeof(sizetype ) = 4
- sizeof(indextype ) = 4
- sizeof(numtype ) = 4
- sizeof(handletype) = 4
- sizeof(tokentype ) = 8
-
- sizeof(short ) = 2
- sizeof(int ) = 4
-
- sizeof(lt64 ) = 4
- sizeof(farlongtype) = 4
- sizeof(long ) = 4
- sizeof(longaddr ) = 4
-
- sizeof(float ) = 4
- sizeof(double ) = 8
-
- sizeof(addrtype ) = 4
- sizeof(char * ) = 4
- ALLOC CORE_1 :: 8
- BHOOLE NATH
-
- OPEN File ./input/bendian.rnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 2030c0
- DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
- DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
- DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
- DB Handle Chunk's StackPtr = 20797
-
- DB[ 1] LOADED; Handles= 20797
- KERNEL in CORE[ 1] Restored @ 1b4750
-
- OPEN File ./input/bendian.wnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 21c40
- DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
- DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
- DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
- DB Handle Chunk's StackPtr = 17
-
- DB[ 2] LOADED; Handles= 17
- VORTEx_Status == -8 || fffffff8
-
- BE HERE NOW !!!
-
-
-
- ... VORTEx ON LINE ...
-
-
- ... END OF SESSION ...
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.068149 # Number of seconds simulated
-sim_ticks 68148672000 # Number of ticks simulated
-final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2078407 # Simulator instruction rate (inst/s)
-host_op_rate 2105318 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1053881878 # Simulator tick rate (ticks/s)
-host_mem_usage 288492 # Number of bytes of host memory used
-host_seconds 64.66 # Real time elapsed on the host
-sim_insts 134398962 # Number of instructions simulated
-sim_ops 136139190 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 538214280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory
-system.physmem.bytes_read::total 685773640 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 538214280 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 538214280 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory
-system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 134553570 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 171784870 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory
-system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory
-system.physmem.num_other::total 15916 # Number of other requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7897648835 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2165256573 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 10062905408 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7897648835 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7897648835 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1318924454 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1318924454 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 171784870 # Transaction distribution
-system.membus.trans_dist::ReadResp 171784870 # Transaction distribution
-system.membus.trans_dist::WriteReq 20864304 # Transaction distribution
-system.membus.trans_dist::WriteResp 20864304 # Transaction distribution
-system.membus.trans_dist::SwapReq 15916 # Transaction distribution
-system.membus.trans_dist::SwapResp 15916 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107140 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 385330180 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214280 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 775783918 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 192665090 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram
-system.membus.snoop_fanout::1 134553570 69.84% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 192665090 # Request fanout histogram
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 136297345 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 134398962 # Number of instructions committed
-system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses
-system.cpu.num_func_calls 1709332 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls
-system.cpu.num_int_insts 115187746 # number of integer instructions
-system.cpu.num_fp_insts 2326977 # number of float instructions
-system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read
-system.cpu.num_int_register_writes 113147734 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
-system.cpu.num_mem_refs 58160248 # number of memory refs
-system.cpu.num_load_insts 37275867 # Number of load instructions
-system.cpu.num_store_insts 20884381 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 136297344.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 12719095 # Number of branches fetched
-system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction
-system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction
-system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction
-system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction
-system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 136293798 # Class of executed instruction
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=262144
-
-[system.cpu.dtb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=SparcInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=SparcISA
-eventq_index=0
-
-[system.cpu.itb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.l2cache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_top_level=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=vortex bendian.raw
-cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: ignoring syscall time(4026528248, 4026527848, ...)
-warn: ignoring syscall time(1375098, 4026527400, ...)
-warn: ignoring syscall time(1, 4026527312, ...)
-warn: ignoring syscall time(413, 4026527048, ...)
-warn: ignoring syscall time(414, 4026527048, ...)
-warn: ignoring syscall time(4026527688, 4026527288, ...)
-warn: ignoring syscall time(1375098, 4026526840, ...)
-warn: ignoring syscall time(409, 4026527048, ...)
-warn: ignoring syscall time(409, 4026527048, ...)
-warn: ignoring syscall time(409, 4026526960, ...)
-warn: ignoring syscall time(409, 4026527040, ...)
-warn: ignoring syscall time(409, 4026527000, ...)
-warn: ignoring syscall time(409, 4026526984, ...)
-warn: ignoring syscall time(409, 4026526984, ...)
-warn: ignoring syscall time(409, 4026526872, ...)
-warn: ignoring syscall time(19045, 4026526312, ...)
-warn: ignoring syscall time(409, 4026526832, ...)
-warn: ignoring syscall time(409, 4026526872, ...)
-warn: ignoring syscall time(409, 4026526872, ...)
-warn: ignoring syscall time(409, 4026526848, ...)
-warn: ignoring syscall time(409, 4026526840, ...)
-warn: ignoring syscall time(409, 4026526872, ...)
-warn: ignoring syscall time(409, 4026526856, ...)
-warn: ignoring syscall time(409, 4026526848, ...)
-warn: ignoring syscall time(409, 4026526936, ...)
-warn: ignoring syscall time(4026527408, 4026527008, ...)
-warn: ignoring syscall time(1375098, 4026526560, ...)
-warn: ignoring syscall time(18732, 4026527184, ...)
-warn: ignoring syscall time(409, 4026526632, ...)
-warn: ignoring syscall time(0, 4026526736, ...)
-warn: ignoring syscall time(0, 4026527320, ...)
-warn: ignoring syscall time(225, 4026527744, ...)
-warn: ignoring syscall time(409, 4026527048, ...)
-warn: ignoring syscall time(409, 4026526856, ...)
-warn: ignoring syscall time(409, 4026526872, ...)
-warn: ignoring syscall time(4026527496, 4026527096, ...)
-warn: ignoring syscall time(1375098, 4026526648, ...)
-warn: ignoring syscall time(0, 4026526824, ...)
-warn: ignoring syscall time(0, 4026527320, ...)
-warn: ignoring syscall time(1879089152, 4026527184, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall times(246, 4026527728, ...)
-warn: ignoring syscall time(1595768, 4026527472, ...)
-warn: ignoring syscall time(17300, 4026526912, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(19045, 4026526912, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(0, 4026527472, ...)
-warn: ignoring syscall time(19045, 4026526912, ...)
-warn: ignoring syscall time(17300, 4026526912, ...)
-warn: ignoring syscall time(20500, 4026525968, ...)
-warn: ignoring syscall time(4026526436, 4026525968, ...)
-warn: ignoring syscall time(7004192, 4026526056, ...)
-warn: ignoring syscall time(4, 4026527512, ...)
-warn: ignoring syscall time(0, 4026525760, ...)
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 22 2014 17:04:27
-gem5 started Jan 22 2014 19:47:13
-gem5 executing on u200540-lin
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Exiting @ tick 202242260000 because target called exit()
+++ /dev/null
-
- SYSTEM TYPE...
- __ZTC__ := False
- __UNIX__ := True
- __RISC__ := True
- SPEC_CPU2000_LP64 := False
- __MAC__ := False
- __BCC__ := False
- __BORLANDC__ := False
- __GUI__ := False
- __WTC__ := False
- __HP__ := False
-
- CODE OPTIONS...
- __MACROIZE_HM__ := True
- __MACROIZE_MEM__ := True
- ENV01 := True
- USE_HPP_STYPE_HDRS := False
- USE_H_STYPE_HDRS := False
-
- CODE INCLUSION PARAMETERS...
- INCLUDE_ALL_CODE := False
- INCLUDE_DELETE_CODE := True
- __SWAP_GRP_POS__ := True
- __INCLUDE_MTRX__ := False
- __BAD_CODE__ := False
- API_INCLUDE := False
- BE_CAREFUL := False
- OLDWAY := False
- NOTUSED := False
-
- SYSTEM PARAMETERS...
- EXT_ENUM := 999999999L
- CHUNK_CONSTANT := 55555555
- CORE_CONSTANT := 55555555
- CORE_LIMIT := 20971520
- CorePage_Size := 384000
- ALIGN_BYTES := True
- CORE_BLOCK_ALIGN := 8
- FAR_MEM := False
-
- MEMORY MANAGEMENT PARAMETERS...
- SYSTEM_ALLOC := True
- SYSTEM_FREESTORE := True
- __NO_DISKCACHE__ := False
- __FREEZE_VCHUNKS__ := True
- __FREEZE_GRP_PACKETS__ := True
- __MINIMIZE_TREE_CACHE__:= True
-
- SYSTEM STD PARAMETERS...
- __STDOUT__ := False
- NULL := 0
- LPTR := False
- False_Status := 1
- True_Status := 0
- LARGE := True
- TWOBYTE_BOOL := False
- __NOSTR__ := False
-
- MEMORY VALIDATION PARAMETERS...
- CORE_CRC_CHECK := False
- VALIDATE_MEM_CHUNKS := False
-
- SYSTEM DEBUG OPTIONS...
- DEBUG := False
- MCSTAT := False
- TRACKBACK := False
- FLUSH_FILES := False
- DEBUG_CORE0 := False
- DEBUG_RISC := False
- __TREE_BUG__ := False
- __TRACK_FILE_READS__ := False
- PAGE_SPACE := False
- LEAVE_NO_TRACE := True
- NULL_TRACE_STRS := False
-
- TIME PARAMETERS...
- CLOCK_IS_LONG := False
- __DISPLAY_TIME__ := False
- __TREE_TIME__ := False
- __DISPLAY_ERRORS__ := False
-
- API MACROS...
- __BMT01__ := True
- OPTIMIZE := True
-
- END OF DEFINES.
-
-
-
- ... IMPLODE MEMORY ...
-
- SWAP to DiskCache := False
-
- FREEZE_GRP_PACKETS:= True
-
- QueBug := 1000
-
- sizeof(boolean) = 4
- sizeof(sizetype) = 4
- sizeof(chunkstruc) = 32
-
- sizeof(shorttype ) = 2
- sizeof(idtype ) = 2
- sizeof(sizetype ) = 4
- sizeof(indextype ) = 4
- sizeof(numtype ) = 4
- sizeof(handletype) = 4
- sizeof(tokentype ) = 8
-
- sizeof(short ) = 2
- sizeof(int ) = 4
-
- sizeof(lt64 ) = 4
- sizeof(farlongtype) = 4
- sizeof(long ) = 4
- sizeof(longaddr ) = 4
-
- sizeof(float ) = 4
- sizeof(double ) = 8
-
- sizeof(addrtype ) = 4
- sizeof(char * ) = 4
- ALLOC CORE_1 :: 8
- BHOOLE NATH
-
- OPEN File ./input/bendian.rnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 2030c0
- DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
- DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
- DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
- DB Handle Chunk's StackPtr = 20797
-
- DB[ 1] LOADED; Handles= 20797
- KERNEL in CORE[ 1] Restored @ 1b4750
-
- OPEN File ./input/bendian.wnv
- *Status = 0
- DB HDR restored from FileVbn[ 0]
- DB BlkDirOffset : @ 21c40
- DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
- DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
- DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
- DB Handle Chunk's StackPtr = 17
-
- DB[ 2] LOADED; Handles= 17
- VORTEx_Status == -8 || fffffff8
-
- BE HERE NOW !!!
-
-
-
- ... VORTEx ON LINE ...
-
-
- ... END OF SESSION ...
+++ /dev/null
- CREATE Db Header and Db Primal ...
- NEW DB [ 3] Created.
-
-VORTEX INPUT PARAMETERS::
- MESSAGE FileName: smred.msg
- OUTPUT FileName: smred.out
- DISK CACHE FileName: NULL
- PART DB FileName: parts.db
- DRAW DB FileName: draw.db
- PERSON DB FileName: emp.db
- PERSONS Data FileName: ./input/persons.250
- PARTS Count : 100
- OUTER Loops : 1
- INNER Loops : 1
- LOOKUP Parts : 25
- DELETE Parts : 10
- STUFF Parts : 10
- DEPTH Traverse: 5
- % DECREASE Parts : 0
- % INCREASE LookUps : 0
- % INCREASE Deletes : 0
- % INCREASE Stuffs : 0
- FREEZE_PACKETS : 1
- ALLOC_CHUNKS : 10000
- EXTEND_CHUNKS : 5000
- DELETE Draw objects : True
- DELETE Part objects : False
- QUE_BUG : 1000
- VOID_BOUNDARY : 67108864
- VOID_RESERVE : 1048576
-
- COMMIT_DBS : False
-
-
-
- BMT TEST :: files...
- EdbName := PartLib
- EdbFileName := parts.db
- DrwName := DrawLib
- DrwFileName := draw.db
- EmpName := PersonLib
- EmpFileName := emp.db
-
- Swap to DiskCache := False
- Freeze the cache := True
-
-
- BMT TEST :: parms...
- DeBug modulo := 1000
- Create Parts count:= 100
- Outer Loops := 1
- Inner Loops := 1
- Look Ups := 25
- Delete Parts := 10
- Stuff Parts := 10
- Traverse Limit := 5
- Delete Draws := True
- Delete Parts := False
- Delete ALL Parts := after every <mod 0>Outer Loop
-
- INITIALIZE LIBRARY ::
-
- INITIALIZE SCHEMA ::
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 4] Created.
- PartLibCreate:: Db[ 4]; VpartsDir= 1
-
- Part Count= 1
-
- Initialize the Class maps
- LIST HEADS loaded ... DbListHead_Class = 207
- DbListNode_Class = 206
-
-...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
-
-
-...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
-
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 5] Created.
- DrawLibCreate:: Db[ 5]; VpartsDir= 1
-
- Initialize the Class maps of this schema.
- Primal_CreateDb Accessed !!!
- CREATE Db Header and Db Primal ...
- NEW DB [ 6] Created.
-
- ***NOTE*** Persons Library Extended!
-
- Create <131072> Persons.
- ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
-
- LAST Person Read::
- ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
-
- BUILD <Query0> for <Part2> class::
-
- if (link[1].length >= 5) ::
-
- Build Query2 for <Address> class::
-
- if (State == CA || State == T*)
-
- Build Query1 for <Person> class::
-
- if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
-
- BUILD <Query3> for <DrawObj> class::
-
- if (Id >= 3000
- && (Id >= 3000 && Id <= 3001)
- && Id >= 3002)
-
- BUILD <Query4> for <NamedDrawObj> class::
-
- if (Nam == Pre*
- || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
- || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
- && Id <= 7)
- SEED := 1008; Swap = False; RgnEntries = 135
-
- OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
-
- Create 100 New Parts
- Create Part 1. Token[ 4: 2].
-
- < 100> Parts Created. CurrentId= 100
-
- Connect each instantiated Part TO 3 unique Parts
- Connect Part 1. Token[ 4: 2]
- Connect Part 25. Token[ 4: 26] FromList= 26.
- Connect Part 12. Token[ 4: 13] FromList= 13.
- Connect Part 59. Token[ 4: 60] FromList= 60.
-
- SET <DrawObjs> entries::
- 1. [ 5: 5] := <1 >; @[: 6]
- Iteration count = 100
-
- SET <NamedDrawObjs> entries::
- 1. [ 5: 39] := <14 >;
- Iteration count = 12
-
- SET <LibRectangles> entries::
- 1. [ 5: 23] := <8 >; @[: 24]
- Iteration count = 12
-
- LIST <DbRectangles> entries::
- 1. [ 5: 23]
- Iteration count = 12
-
- SET <PersonNames > entries::
- Iteration count = 250
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 100
- < 100> Part images' Committed.
- < 0> are Named.
- < 50> Point images' Committed.
- < 81> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. TestObj Committed.
- < 0> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
- < 0> CartesianPoint images' Committed.
-
- BEGIN Inner Loop Sequence::.
-
- INNER LOOP [ 1: 1] :
-
- LOOK UP 25 Random Parts and Export each Part.
-
- LookUp for 26 parts; Asserts = 8
- <Part2 > Asserts = 2; NULL Asserts = 3.
- <DrawObj > Asserts = 0; NULL Asserts = 5.
- <NamedObj > Asserts = 0; NULL Asserts = 0.
- <Person > Asserts = 0; NULL Asserts = 5.
- <TestObj > Asserts = 60; NULL Asserts = 0.
-
- DELETE 10 Random Parts.
-
- PartDelete :: Token[ 4: 91].
- PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
- DisConnect link [ 0]:= 50; PartToken[ 51: 51].
- DisConnect link [ 1]:= 17; PartToken[ 18: 18].
- DisConnect link [ 2]:= 72; PartToken[ 73: 73].
- DeleteFromList:: Vchunk[ 4: 91]. (* 1)
- DisConnect FromList[ 0]:= 56; Token[ 57: 57].
- Vlists[ 89] := 100;
-
- Delete for 11 parts;
-
- Traverse Count= 0
-
- TRAVERSE PartId[ 6] and all Connections to 5 Levels
- SEED In Traverse Part [ 4: 65] @ Level = 4.
-
- Traverse Count= 357
- Traverse Asserts = 5. True Tests = 1
- < 5> DrawObj objects DELETED.
- < 2> are Named.
- < 2> Point objects DELETED.
-
- CREATE 10 Additional Parts
-
- Create 10 New Parts
- Create Part 101. Token[ 4: 102].
-
- < 10> Parts Created. CurrentId= 110
-
- Connect each instantiated Part TO 3 unique Parts
-
- COMMIT All Image copies:: Release=<True>; Max Parts= 110
- < 81> Part images' Committed.
- < 0> are Named.
- < 38> Point images' Committed.
- < 31> Person images' Committed.
-
- COMMIT Parts(* 100)
-
- Commit TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Committed.
- < 15> TestObj images' Committed.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
- < 16> CartesianPoint images' Committed.
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- ItNum 0. Token[ 3: 4]. TestObj Deleted.
- < 15> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
- < 16> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
-
- END INNER LOOP [ 1: 1].
-
- DELETE All TestObj objects;
-
- Delete TestObj_Class in <Primal> DB.
- < 0> TestObj objects Deleted.
-
- Commit CartesianPoint_Class in <Primal> DB.
- < 0> CartesianPoint objects Deleted.
-
- DELETE TestObj and Point objects...
- STATUS= -201
-V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.202242 # Number of seconds simulated
-sim_ticks 202242028500 # Number of ticks simulated
-final_tick 202242028500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1201078 # Simulator instruction rate (inst/s)
-host_op_rate 1216630 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1807368744 # Simulator tick rate (ticks/s)
-host_mem_usage 300888 # Number of bytes of host memory used
-host_seconds 111.90 # Real time elapsed on the host
-sim_insts 134398962 # Number of instructions simulated
-sim_ops 136139190 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 7826624 # Number of bytes read from this memory
-system.physmem.bytes_read::total 8418112 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 591488 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 591488 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5303552 # Number of bytes written to this memory
-system.physmem.bytes_written::total 5303552 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 9242 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 122291 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 131533 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 82868 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 82868 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2924654 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 38699295 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 41623950 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2924654 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2924654 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 26223788 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 26223788 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 26223788 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2924654 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 38699295 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 67847737 # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 404484057 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 134398962 # Number of instructions committed
-system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses
-system.cpu.num_func_calls 1709332 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls
-system.cpu.num_int_insts 115187746 # number of integer instructions
-system.cpu.num_fp_insts 2326977 # number of float instructions
-system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read
-system.cpu.num_int_register_writes 113147733 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
-system.cpu.num_mem_refs 58160248 # number of memory refs
-system.cpu.num_load_insts 37275867 # Number of load instructions
-system.cpu.num_store_insts 20884381 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 404484056.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 12719095 # Number of branches fetched
-system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction
-system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction
-system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction
-system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction
-system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction
-system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 136293798 # Class of executed instruction
-system.cpu.dcache.tags.replacements 146582 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4087.648320 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 769041000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648320 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 3530 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits
-system.cpu.dcache.overall_hits::total 57944941 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses
-system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses
-system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses
-system.cpu.dcache.overall_misses::total 150663 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475000000 # number of ReadReq miss cycles
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-system.cpu.l2cache.overall_miss_rate::cpu.data 0.811605 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.389494 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52509.251244 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52502.044212 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52504.244146 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52509.251244 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.351620 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52500.976941 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52509.251244 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.351620 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52500.976941 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 82868 # number of writebacks
-system.cpu.l2cache.writebacks::total 82868 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9242 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21035 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 30277 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101256 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 101256 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 9242 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 122291 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 131533 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 9242 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 122291 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 131533 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 374386000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 851960500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1226346500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4100868000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4100868000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 374386000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4952828500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 5327214500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 374386000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4952828500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 5327214500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.462318 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.130211 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962702 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962702 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.389494 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.389494 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40509.197143 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40502.044212 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40504.227632 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40509.197143 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.351620 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.973140 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40509.197143 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.351620 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.973140 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374048 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 425326 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 799374 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17577472 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 461672 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 461672 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 461672 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 30277 # Transaction distribution
-system.membus.trans_dist::ReadResp 30277 # Transaction distribution
-system.membus.trans_dist::Writeback 82868 # Transaction distribution
-system.membus.trans_dist::ReadExReq 101256 # Transaction distribution
-system.membus.trans_dist::ReadExResp 101256 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 214401 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 214401 # Request fanout histogram
-system.membus.reqLayer0.occupancy 558284500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.membus.respLayer1.occupancy 657665500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: ignoring syscall sigprocmask(1, ...)
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 19:22:57
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic
-Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sav
-Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 45951567500 because target called exit()
+++ /dev/null
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-
-
-NOTE: Restart file .rs2 not used
-
-TimberWolf will perform a global route step
-rowSep: 1.000000
-feedThruWidth: 4
-
-******************
-BLOCK DATA
-block:1 desire:85
-block:2 desire:85
-Total Desired Length: 170
-total cell length: 168
-total block length: 168
-block x-span:84 block y-span:78
-implicit feed thru range: -84
-Using default value of bin.penalty.control:1.000000
-numBins automatically set to:5
-binWidth = average_cell_width + 0 sigma= 17
-average_cell_width is:16
-standard deviation of cell length is:23.6305
-TimberWolfSC starting from the beginning
-
-
-
-THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
-The number of nets with 1 pin is 4
-The number of nets with 2 pin is 9
-The number of nets with 3 pin is 0
-The number of nets with 4 pin is 2
-The number of nets with 5 pin is 0
-The number of nets with 6 pin is 0
-The number of nets with 7 pin is 0
-The number of nets with 8 pin is 0
-The number of nets with 9 pin is 0
-The number of nets with 10 pin or more is 0
-
-New Cost Function: Initial Horizontal Cost:242
-New Cost Function: FEEDS:0 MISSING_ROWS:-46
-
-bdxlen:86 bdylen:78
-l:0 t:78 r:86 b:0
-
-
-
-THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
-
-
-
-THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
-
-The rand generator seed was at utemp() : 1
-
-
- tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
- tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
- tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
- tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
-
- I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
- 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
- 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
- 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46
- 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
- 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
- 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
- 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
- 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
- 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
- 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
- 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
- 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
- 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
- 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
- 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
- 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
- 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
- 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
- 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
- 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
- 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
- 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
- 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
- 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
- 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
- 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
- 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
- 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
- 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
- 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
- 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
- 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
- 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
- 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
- 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
- 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
- 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
- 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
- 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
- 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48
- 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
- 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
- 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
- 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
- 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
- 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
- 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
- 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
- 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
- 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
- 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
- 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
- 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
- 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
- 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
- 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
- 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
- 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
- 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
- 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
- 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
- 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
- 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
- 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
- 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
- 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
- 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
- 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
- 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
- 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
- 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
- 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
- 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
- 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
- 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
- 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
- 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
- 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
- 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
- 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
- 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
- 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
- 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
- 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
- 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
- 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
- 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
- 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
- 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
- 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
- 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
- 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
- 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
- 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
- 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
- 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
- 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
- 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
- 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
-100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
-101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
-102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
-103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
-104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
-105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
-106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
-107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
-108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
-109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
-110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
-111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
-112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
-113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
-114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
-115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
-116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
-117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
-118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
-119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
-120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
-121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
-
-Initial Wiring Cost: 645 Final Wiring Cost: 732
-############## Percent Wire Cost Reduction: -13
-
-
-Initial Wire Length: 645 Final Wire Length: 732
-************** Percent Wire Length Reduction: -13
-
-
-Initial Horiz. Wire: 216 Final Horiz. Wire: 147
-$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
-
-
-Initial Vert. Wire: 429 Final Vert. Wire: 585
-@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
-
-Before Feeds are Added:
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 82 -20
- 2 86 -16
-
-LONGEST Block is:2 Its length is:86
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 86 -16
- 2 86 -16
-
-LONGEST Block is:1 Its length is:86
-Added: 1 feed-through cells
-
-Removed the cell overlaps --- Will do neighbor interchanges only now
-
-TOTAL INTERCONNECT LENGTH: 994
-OVERLAP PENALTY: 0
-
-initialRowControl: 1.650
-finalRowControl: 0.300
-iter T Wire accept
- 122 0.001 976 16%
- 123 0.001 971 0%
- 124 0.001 971 0%
-Total Feed-Alignment Movement (Pass 1): 0
-Total Feed-Alignment Movement (Pass 2): 0
-Total Feed-Alignment Movement (Pass 3): 0
-Total Feed-Alignment Movement (Pass 4): 0
-Total Feed-Alignment Movement (Pass 5): 0
-Total Feed-Alignment Movement (Pass 6): 0
-Total Feed-Alignment Movement (Pass 7): 0
-Total Feed-Alignment Movement (Pass 8): 0
-
-The rand generator seed was at globroute() : 987654321
-
-
-Total Number of Net Segments: 9
-Number of Switchable Net Segments: 0
-
-Number of channels: 3
-
-
-
-THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
-
-
-no. of accepted flips: 0
-no. of attempted flips: 0
-THIS IS THE NUMBER OF TRACKS: 5
-
-
-
-FINAL NUMBER OF ROUTING TRACKS: 5
-
-MAX OF CHANNEL: 1 is: 0
-MAX OF CHANNEL: 2 is: 4
-MAX OF CHANNEL: 3 is: 1
-FINAL TOTAL INTERCONNECT LENGTH: 978
-FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
-MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
-
-
-cost_scale_factor:3.90616
-
-Number of Feed Thrus: 0
-Number of Implicit Feed Thrus: 0
-
-Statistics:
-Number of Standard Cells: 10
-Number of Pads: 0
-Number of Nets: 15
-Number of Pins: 46
-Usage statistics not available
+++ /dev/null
-$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
-$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
-B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
-B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
-B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
+++ /dev/null
-$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
-$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
-$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
-ACOUNT_1 14 0 18 26 2 1
-twfeed1 18 0 22 26 0 1
-$COUNT_1/$FJK3_1 22 0 86 26 0 1
-$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
-$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
-$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
-$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
-$COUNT_1/$FJK3_2 22 52 86 78 0 2
+++ /dev/null
-1 0 0 86 26 0 0
-2 0 52 86 78 0 0
+++ /dev/null
-0.009592
-121
-0
-1
-0.000000
-0.500000
-3.906156
-1
-1 1 2 37 13
-2 2 0 34 65
-3 2 2 63 65
-4 1 0 59 13
-5 1 2 32 13
-6 2 0 23 65
-7 1 2 12 13
-8 2 0 6 65
-9 1 0 70 13
-10 2 0 70 65
+++ /dev/null
-0.001000
-123
-0
-2
-0.000000
-0.500000
-3.906156
-1
-1 1 2 16 13
-2 2 2 19 65
-3 2 2 14 65
-4 1 0 11 13
-5 1 2 6 13
-6 2 0 3 65
-7 1 0 2 13
-8 2 2 9 65
-9 1 0 50 13
-10 2 0 54 65
-11 1 0 84 13
+++ /dev/null
-net 1
-segment channel 2
- pin1 1 pin2 7 0 0
-net 2
-segment channel 3
-pin1 41 pin2 42 0 0
-segment channel 2
-pin1 12 pin2 3 0 0
-net 3
-segment channel 2
-pin1 35 pin2 36 0 0
-segment channel 2
-pin1 19 pin2 35 0 0
-net 4
-segment channel 2
- pin1 5 pin2 38 0 0
-net 5
-net 7
-segment channel 2
- pin1 14 pin2 43 0 0
-net 8
-segment channel 2
- pin1 23 pin2 17 0 0
-net 9
-net 11
-segment channel 2
- pin1 25 pin2 31 0 0
-net 14
-net 15
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.045952 # Number of seconds simulated
-sim_ticks 45951567500 # Number of ticks simulated
-final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2845952 # Simulator instruction rate (inst/s)
-host_op_rate 2845951 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1422976169 # Simulator tick rate (ticks/s)
-host_mem_usage 283520 # Number of bytes of host memory used
-host_seconds 32.29 # Real time elapsed on the host
-sim_insts 91903056 # Number of instructions simulated
-sim_ops 91903056 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 108337521 # Number of bytes read from this memory
-system.physmem.bytes_read::total 475949877 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 367612356 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 367612356 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 30920974 # Number of bytes written to this memory
-system.physmem.bytes_written::total 30920974 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 91903089 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 19996198 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 111899287 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 6501103 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 6501103 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7999995996 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2357645819 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 10357641815 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7999995996 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7999995996 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 672903574 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 672903574 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 111899287 # Transaction distribution
-system.membus.trans_dist::ReadResp 111899287 # Transaction distribution
-system.membus.trans_dist::WriteReq 6501103 # Transaction distribution
-system.membus.trans_dist::WriteResp 6501103 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 183806178 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 52994602 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 236800780 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 367612356 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 139258495 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 506870851 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 118400390 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.776206 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.416786 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 26497301 22.38% 22.38% # Request fanout histogram
-system.membus.snoop_fanout::1 91903089 77.62% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 118400390 # Request fanout histogram
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 19996198 # DTB read hits
-system.cpu.dtb.read_misses 10 # DTB read misses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 19996208 # DTB read accesses
-system.cpu.dtb.write_hits 6501103 # DTB write hits
-system.cpu.dtb.write_misses 23 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 6501126 # DTB write accesses
-system.cpu.dtb.data_hits 26497301 # DTB hits
-system.cpu.dtb.data_misses 33 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 26497334 # DTB accesses
-system.cpu.itb.fetch_hits 91903089 # ITB hits
-system.cpu.itb.fetch_misses 47 # ITB misses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 91903136 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 389 # Number of system calls
-system.cpu.numCycles 91903136 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 91903056 # Number of instructions committed
-system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
-system.cpu.num_func_calls 2059216 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
-system.cpu.num_int_insts 79581109 # number of integer instructions
-system.cpu.num_fp_insts 6862064 # number of float instructions
-system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
-system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
-system.cpu.num_mem_refs 26497334 # number of memory refs
-system.cpu.num_load_insts 19996208 # Number of load instructions
-system.cpu.num_store_insts 6501126 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 91903136 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 10240685 # Number of branches fetched
-system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction
-system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction
-system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction
-system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction
-system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction
-system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction
-system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction
-system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 91903089 # Class of executed instruction
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=262144
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_top_level=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: ignoring syscall sigprocmask(1, ...)
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 19:23:43
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
-Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav
-Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 118729316000 because target called exit()
+++ /dev/null
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-
-
-NOTE: Restart file .rs2 not used
-
-TimberWolf will perform a global route step
-rowSep: 1.000000
-feedThruWidth: 4
-
-******************
-BLOCK DATA
-block:1 desire:85
-block:2 desire:85
-Total Desired Length: 170
-total cell length: 168
-total block length: 168
-block x-span:84 block y-span:78
-implicit feed thru range: -84
-Using default value of bin.penalty.control:1.000000
-numBins automatically set to:5
-binWidth = average_cell_width + 0 sigma= 17
-average_cell_width is:16
-standard deviation of cell length is:23.6305
-TimberWolfSC starting from the beginning
-
-
-
-THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
-The number of nets with 1 pin is 4
-The number of nets with 2 pin is 9
-The number of nets with 3 pin is 0
-The number of nets with 4 pin is 2
-The number of nets with 5 pin is 0
-The number of nets with 6 pin is 0
-The number of nets with 7 pin is 0
-The number of nets with 8 pin is 0
-The number of nets with 9 pin is 0
-The number of nets with 10 pin or more is 0
-
-New Cost Function: Initial Horizontal Cost:242
-New Cost Function: FEEDS:0 MISSING_ROWS:-46
-
-bdxlen:86 bdylen:78
-l:0 t:78 r:86 b:0
-
-
-
-THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
-
-
-
-THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
-
-The rand generator seed was at utemp() : 1
-
-
- tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
- tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
- tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
- tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
-
- I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
- 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
- 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
- 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46
- 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
- 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
- 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
- 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
- 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
- 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
- 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
- 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
- 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
- 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
- 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
- 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
- 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
- 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
- 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
- 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
- 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
- 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
- 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
- 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
- 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
- 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
- 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
- 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
- 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
- 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
- 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
- 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
- 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
- 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
- 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
- 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
- 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
- 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
- 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
- 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
- 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48
- 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
- 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
- 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
- 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
- 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
- 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
- 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
- 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
- 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
- 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
- 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
- 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
- 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
- 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
- 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
- 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
- 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
- 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
- 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
- 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
- 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
- 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
- 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
- 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
- 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
- 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
- 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
- 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
- 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
- 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
- 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
- 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
- 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
- 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
- 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
- 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
- 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
- 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
- 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
- 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
- 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
- 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
- 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
- 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
- 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
- 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
- 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
- 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
- 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
- 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
- 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
- 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
- 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
- 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
- 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
- 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
- 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
- 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
- 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
-100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
-101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
-102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
-103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
-104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
-105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
-106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
-107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
-108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
-109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
-110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
-111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
-112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
-113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
-114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
-115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
-116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
-117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
-118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
-119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
-120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
-121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
-
-Initial Wiring Cost: 645 Final Wiring Cost: 732
-############## Percent Wire Cost Reduction: -13
-
-
-Initial Wire Length: 645 Final Wire Length: 732
-************** Percent Wire Length Reduction: -13
-
-
-Initial Horiz. Wire: 216 Final Horiz. Wire: 147
-$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
-
-
-Initial Vert. Wire: 429 Final Vert. Wire: 585
-@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
-
-Before Feeds are Added:
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 82 -20
- 2 86 -16
-
-LONGEST Block is:2 Its length is:86
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 86 -16
- 2 86 -16
-
-LONGEST Block is:1 Its length is:86
-Added: 1 feed-through cells
-
-Removed the cell overlaps --- Will do neighbor interchanges only now
-
-TOTAL INTERCONNECT LENGTH: 994
-OVERLAP PENALTY: 0
-
-initialRowControl: 1.650
-finalRowControl: 0.300
-iter T Wire accept
- 122 0.001 976 16%
- 123 0.001 971 0%
- 124 0.001 971 0%
-Total Feed-Alignment Movement (Pass 1): 0
-Total Feed-Alignment Movement (Pass 2): 0
-Total Feed-Alignment Movement (Pass 3): 0
-Total Feed-Alignment Movement (Pass 4): 0
-Total Feed-Alignment Movement (Pass 5): 0
-Total Feed-Alignment Movement (Pass 6): 0
-Total Feed-Alignment Movement (Pass 7): 0
-Total Feed-Alignment Movement (Pass 8): 0
-
-The rand generator seed was at globroute() : 987654321
-
-
-Total Number of Net Segments: 9
-Number of Switchable Net Segments: 0
-
-Number of channels: 3
-
-
-
-THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
-
-
-no. of accepted flips: 0
-no. of attempted flips: 0
-THIS IS THE NUMBER OF TRACKS: 5
-
-
-
-FINAL NUMBER OF ROUTING TRACKS: 5
-
-MAX OF CHANNEL: 1 is: 0
-MAX OF CHANNEL: 2 is: 4
-MAX OF CHANNEL: 3 is: 1
-FINAL TOTAL INTERCONNECT LENGTH: 978
-FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
-MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
-
-
-cost_scale_factor:3.90616
-
-Number of Feed Thrus: 0
-Number of Implicit Feed Thrus: 0
-
-Statistics:
-Number of Standard Cells: 10
-Number of Pads: 0
-Number of Nets: 15
-Number of Pins: 46
-Usage statistics not available
+++ /dev/null
-$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
-$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
-B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
-B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
-B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
+++ /dev/null
-$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
-$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
-$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
-ACOUNT_1 14 0 18 26 2 1
-twfeed1 18 0 22 26 0 1
-$COUNT_1/$FJK3_1 22 0 86 26 0 1
-$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
-$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
-$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
-$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
-$COUNT_1/$FJK3_2 22 52 86 78 0 2
+++ /dev/null
-1 0 0 86 26 0 0
-2 0 52 86 78 0 0
+++ /dev/null
-0.009592
-121
-0
-1
-0.000000
-0.500000
-3.906156
-1
-1 1 2 37 13
-2 2 0 34 65
-3 2 2 63 65
-4 1 0 59 13
-5 1 2 32 13
-6 2 0 23 65
-7 1 2 12 13
-8 2 0 6 65
-9 1 0 70 13
-10 2 0 70 65
+++ /dev/null
-0.001000
-123
-0
-2
-0.000000
-0.500000
-3.906156
-1
-1 1 2 16 13
-2 2 2 19 65
-3 2 2 14 65
-4 1 0 11 13
-5 1 2 6 13
-6 2 0 3 65
-7 1 0 2 13
-8 2 2 9 65
-9 1 0 50 13
-10 2 0 54 65
-11 1 0 84 13
+++ /dev/null
-net 1
-segment channel 2
- pin1 1 pin2 7 0 0
-net 2
-segment channel 3
-pin1 41 pin2 42 0 0
-segment channel 2
-pin1 12 pin2 3 0 0
-net 3
-segment channel 2
-pin1 35 pin2 36 0 0
-segment channel 2
-pin1 19 pin2 35 0 0
-net 4
-segment channel 2
- pin1 5 pin2 38 0 0
-net 5
-net 7
-segment channel 2
- pin1 14 pin2 43 0 0
-net 8
-segment channel 2
- pin1 23 pin2 17 0 0
-net 9
-net 11
-segment channel 2
- pin1 25 pin2 31 0 0
-net 14
-net 15
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.118729 # Number of seconds simulated
-sim_ticks 118729316500 # Number of ticks simulated
-final_tick 118729316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1507080 # Simulator instruction rate (inst/s)
-host_op_rate 1507080 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1946992285 # Simulator tick rate (ticks/s)
-host_mem_usage 297820 # Number of bytes of host memory used
-host_seconds 60.98 # Real time elapsed on the host
-sim_insts 91903056 # Number of instructions simulated
-sim_ops 91903056 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory
-system.physmem.bytes_read::total 304960 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 167744 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 167744 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1412827 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1155704 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2568532 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1412827 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1412827 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 19996198 # DTB read hits
-system.cpu.dtb.read_misses 10 # DTB read misses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 19996208 # DTB read accesses
-system.cpu.dtb.write_hits 6501103 # DTB write hits
-system.cpu.dtb.write_misses 23 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 6501126 # DTB write accesses
-system.cpu.dtb.data_hits 26497301 # DTB hits
-system.cpu.dtb.data_misses 33 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 26497334 # DTB accesses
-system.cpu.itb.fetch_hits 91903090 # ITB hits
-system.cpu.itb.fetch_misses 47 # ITB misses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 91903137 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 389 # Number of system calls
-system.cpu.numCycles 237458633 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 91903056 # Number of instructions committed
-system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
-system.cpu.num_func_calls 2059216 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
-system.cpu.num_int_insts 79581109 # number of integer instructions
-system.cpu.num_fp_insts 6862064 # number of float instructions
-system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
-system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
-system.cpu.num_mem_refs 26497334 # number of memory refs
-system.cpu.num_load_insts 19996208 # Number of load instructions
-system.cpu.num_store_insts 6501126 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 237458633 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 10240685 # Number of branches fetched
-system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction
-system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction
-system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction
-system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction
-system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction
-system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction
-system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction
-system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction
-system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 91903089 # Class of executed instruction
-system.cpu.dcache.tags.replacements 157 # number of replacements
-system.cpu.dcache.tags.tagsinuse 1442.043377 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043377 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 487 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits
-system.cpu.dcache.overall_hits::total 26495078 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses
-system.cpu.dcache.overall_misses::total 2223 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
-system.cpu.dcache.writebacks::total 107 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23186500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 23186500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92426000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 92426000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115612500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 115612500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115612500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 115612500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48813.684211 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48813.684211 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52875.286041 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52875.286041 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 6681 # number of replacements
-system.cpu.icache.tags.tagsinuse 1418.052759 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks.
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-system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 3043 # Transaction distribution
-system.membus.trans_dist::ReadResp 3043 # Transaction distribution
-system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
-system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 4765 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 4765 # Request fanout histogram
-system.membus.reqLayer0.occupancy 4765500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 23825500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-port=system.membus.slave[6]
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.membus.slave[4]
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-port=system.membus.slave[5]
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.membus.slave[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 18:37:39
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
-Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x5fbc6c0
-info: Entering event queue @ 0. Starting simulation...
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-info: Increasing stack size by one page.
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 103106766000 because target called exit()
+++ /dev/null
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-
-
-NOTE: Restart file .rs2 not used
-
-TimberWolf will perform a global route step
-rowSep: 1.000000
-feedThruWidth: 4
-
-******************
-BLOCK DATA
-block:1 desire:85
-block:2 desire:85
-Total Desired Length: 170
-total cell length: 168
-total block length: 168
-block x-span:84 block y-span:78
-implicit feed thru range: -84
-Using default value of bin.penalty.control:1.000000
-numBins automatically set to:5
-binWidth = average_cell_width + 0 sigma= 17
-average_cell_width is:16
-standard deviation of cell length is:23.6305
-TimberWolfSC starting from the beginning
-
-
-
-THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
-The number of nets with 1 pin is 4
-The number of nets with 2 pin is 9
-The number of nets with 3 pin is 0
-The number of nets with 4 pin is 2
-The number of nets with 5 pin is 0
-The number of nets with 6 pin is 0
-The number of nets with 7 pin is 0
-The number of nets with 8 pin is 0
-The number of nets with 9 pin is 0
-The number of nets with 10 pin or more is 0
-
-New Cost Function: Initial Horizontal Cost:242
-New Cost Function: FEEDS:0 MISSING_ROWS:-46
-
-bdxlen:86 bdylen:78
-l:0 t:78 r:86 b:0
-
-
-
-THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
-
-
-
-THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
-
-The rand generator seed was at utemp() : 1
-
-
- tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
- tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
- tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
- tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
-
- I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
- 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
- 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
- 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
- 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
- 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
- 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
- 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
- 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
- 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
- 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
- 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
- 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
- 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
- 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
- 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
- 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
- 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
- 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
- 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
- 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
- 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
- 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
- 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
- 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
- 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
- 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
- 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
- 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
- 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
- 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
- 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
- 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
- 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
- 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
- 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
- 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
- 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
- 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
- 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
- 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
- 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
- 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
- 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
- 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
- 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
- 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
- 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
- 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
- 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
- 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
- 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
- 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
- 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
- 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
- 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
- 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
- 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
- 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
- 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
- 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
- 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
- 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
- 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
- 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
- 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
- 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
- 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
- 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
- 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
- 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
- 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
- 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
- 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
- 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
- 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
- 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
- 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
- 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
- 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
- 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
- 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
- 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
- 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
- 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
- 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
- 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
- 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
- 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
- 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
- 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
- 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
- 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
- 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
- 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
- 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
- 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
- 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
- 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
- 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
-100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
-101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
-102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
-103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
-104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
-105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
-106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
-107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
-108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
-109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
-110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
-111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
-112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
-113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
-114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
-115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
-116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
-117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
-118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
-119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
-120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
-121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
-
-Initial Wiring Cost: 645 Final Wiring Cost: 732
-############## Percent Wire Cost Reduction: -13
-
-
-Initial Wire Length: 645 Final Wire Length: 732
-************** Percent Wire Length Reduction: -13
-
-
-Initial Horiz. Wire: 216 Final Horiz. Wire: 147
-$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
-
-
-Initial Vert. Wire: 429 Final Vert. Wire: 585
-@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
-
-Before Feeds are Added:
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 82 -20
- 2 86 -16
-
-LONGEST Block is:2 Its length is:86
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 86 -16
- 2 86 -16
-
-LONGEST Block is:1 Its length is:86
-Added: 1 feed-through cells
-
-Removed the cell overlaps --- Will do neighbor interchanges only now
-
-TOTAL INTERCONNECT LENGTH: 994
-OVERLAP PENALTY: 0
-
-initialRowControl: 1.650
-finalRowControl: 0.300
-iter T Wire accept
- 122 0.001 976 16%
- 123 0.001 971 0%
- 124 0.001 971 0%
-Total Feed-Alignment Movement (Pass 1): 0
-Total Feed-Alignment Movement (Pass 2): 0
-Total Feed-Alignment Movement (Pass 3): 0
-Total Feed-Alignment Movement (Pass 4): 0
-Total Feed-Alignment Movement (Pass 5): 0
-Total Feed-Alignment Movement (Pass 6): 0
-Total Feed-Alignment Movement (Pass 7): 0
-Total Feed-Alignment Movement (Pass 8): 0
-
-The rand generator seed was at globroute() : 987654321
-
-
-Total Number of Net Segments: 9
-Number of Switchable Net Segments: 0
-
-Number of channels: 3
-
-
-
-THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
-
-
-no. of accepted flips: 0
-no. of attempted flips: 0
-THIS IS THE NUMBER OF TRACKS: 5
-
-
-
-FINAL NUMBER OF ROUTING TRACKS: 5
-
-MAX OF CHANNEL: 1 is: 0
-MAX OF CHANNEL: 2 is: 4
-MAX OF CHANNEL: 3 is: 1
-FINAL TOTAL INTERCONNECT LENGTH: 978
-FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
-MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
-
-
-cost_scale_factor:3.90616
-
-Number of Feed Thrus: 0
-Number of Implicit Feed Thrus: 0
-
-Statistics:
-Number of Standard Cells: 10
-Number of Pads: 0
-Number of Nets: 15
-Number of Pins: 46
-Usage statistics not available
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.099596 # Number of seconds simulated
-sim_ticks 99596491000 # Number of ticks simulated
-final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1940320 # Simulator instruction rate (inst/s)
-host_op_rate 2045410 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1121471108 # Simulator tick rate (ticks/s)
-host_mem_usage 304628 # Number of bytes of host memory used
-host_seconds 88.81 # Real time elapsed on the host
-sim_insts 172317409 # Number of instructions simulated
-sim_ops 181650341 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory
-system.physmem.bytes_read::total 869973865 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 759440204 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 759440204 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory
-system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 189860051 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 27777721 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 217637772 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7625170288 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1109814813 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 8734985101 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7625170288 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7625170288 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 454362795 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 454362795 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7625170288 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1564177607 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 9189347896 # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 199192983 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 172317409 # Number of instructions committed
-system.cpu.committedOps 181650341 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
-system.cpu.num_func_calls 3545028 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls
-system.cpu.num_int_insts 143085668 # number of integer instructions
-system.cpu.num_fp_insts 1752310 # number of float instructions
-system.cpu.num_int_register_reads 241970171 # number of times the integer registers were read
-system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 543309967 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written
-system.cpu.num_mem_refs 40540779 # number of memory refs
-system.cpu.num_load_insts 27896144 # Number of load instructions
-system.cpu.num_store_insts 12644635 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 199192982.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 40300311 # Number of branches fetched
-system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction
-system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction
-system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction
-system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 181650742 # Class of executed instruction
-system.membus.trans_dist::ReadReq 217614902 # Transaction distribution
-system.membus.trans_dist::ReadResp 217637309 # Transaction distribution
-system.membus.trans_dist::WriteReq 12364287 # Transaction distribution
-system.membus.trans_dist::WriteResp 12364287 # Transaction distribution
-system.membus.trans_dist::SoftPFReq 463 # Transaction distribution
-system.membus.trans_dist::SoftPFResp 463 # Transaction distribution
-system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution
-system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution
-system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720102 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 460048932 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440204 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 230024466 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.825391 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 40164415 17.46% 17.46% # Request fanout histogram
-system.membus.snoop_fanout::3 189860051 82.54% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
-system.membus.snoop_fanout::total 230024466 # Request fanout histogram
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=262144
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-port=system.cpu.toL2Bus.slave[5]
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-port=system.cpu.toL2Bus.slave[4]
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_top_level=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 18:39:21
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
-Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.isa: ISA system set to: 0 0x5d0ed00
-info: Entering event queue @ 0. Starting simulation...
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-info: Increasing stack size by one page.
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 232072304000 because target called exit()
+++ /dev/null
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-
-
-NOTE: Restart file .rs2 not used
-
-TimberWolf will perform a global route step
-rowSep: 1.000000
-feedThruWidth: 4
-
-******************
-BLOCK DATA
-block:1 desire:85
-block:2 desire:85
-Total Desired Length: 170
-total cell length: 168
-total block length: 168
-block x-span:84 block y-span:78
-implicit feed thru range: -84
-Using default value of bin.penalty.control:1.000000
-numBins automatically set to:5
-binWidth = average_cell_width + 0 sigma= 17
-average_cell_width is:16
-standard deviation of cell length is:23.6305
-TimberWolfSC starting from the beginning
-
-
-
-THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
-The number of nets with 1 pin is 4
-The number of nets with 2 pin is 9
-The number of nets with 3 pin is 0
-The number of nets with 4 pin is 2
-The number of nets with 5 pin is 0
-The number of nets with 6 pin is 0
-The number of nets with 7 pin is 0
-The number of nets with 8 pin is 0
-The number of nets with 9 pin is 0
-The number of nets with 10 pin or more is 0
-
-New Cost Function: Initial Horizontal Cost:242
-New Cost Function: FEEDS:0 MISSING_ROWS:-46
-
-bdxlen:86 bdylen:78
-l:0 t:78 r:86 b:0
-
-
-
-THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
-
-
-
-THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
-
-The rand generator seed was at utemp() : 1
-
-
- tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
- tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
- tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
- tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
-
- I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
- 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
- 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
- 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
- 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
- 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
- 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
- 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
- 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
- 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
- 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
- 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
- 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
- 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
- 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
- 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
- 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
- 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
- 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
- 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
- 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
- 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
- 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
- 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
- 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
- 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
- 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
- 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
- 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
- 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
- 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
- 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
- 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
- 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
- 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
- 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
- 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
- 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
- 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
- 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
- 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
- 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
- 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
- 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
- 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
- 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
- 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
- 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
- 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
- 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
- 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
- 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
- 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
- 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
- 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
- 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
- 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
- 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
- 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
- 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
- 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
- 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
- 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
- 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
- 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
- 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
- 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
- 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
- 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
- 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
- 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
- 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
- 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
- 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
- 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
- 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
- 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
- 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
- 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
- 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
- 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
- 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
- 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
- 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
- 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
- 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
- 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
- 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
- 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
- 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
- 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
- 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
- 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
- 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
- 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
- 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
- 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
- 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
- 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
- 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
-100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
-101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
-102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
-103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
-104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
-105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
-106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
-107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
-108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
-109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
-110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
-111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
-112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
-113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
-114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
-115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
-116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
-117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
-118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
-119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
-120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
-121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
-
-Initial Wiring Cost: 645 Final Wiring Cost: 732
-############## Percent Wire Cost Reduction: -13
-
-
-Initial Wire Length: 645 Final Wire Length: 732
-************** Percent Wire Length Reduction: -13
-
-
-Initial Horiz. Wire: 216 Final Horiz. Wire: 147
-$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
-
-
-Initial Vert. Wire: 429 Final Vert. Wire: 585
-@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
-
-Before Feeds are Added:
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 82 -20
- 2 86 -16
-
-LONGEST Block is:2 Its length is:86
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 86 -16
- 2 86 -16
-
-LONGEST Block is:1 Its length is:86
-Added: 1 feed-through cells
-
-Removed the cell overlaps --- Will do neighbor interchanges only now
-
-TOTAL INTERCONNECT LENGTH: 994
-OVERLAP PENALTY: 0
-
-initialRowControl: 1.650
-finalRowControl: 0.300
-iter T Wire accept
- 122 0.001 976 16%
- 123 0.001 971 0%
- 124 0.001 971 0%
-Total Feed-Alignment Movement (Pass 1): 0
-Total Feed-Alignment Movement (Pass 2): 0
-Total Feed-Alignment Movement (Pass 3): 0
-Total Feed-Alignment Movement (Pass 4): 0
-Total Feed-Alignment Movement (Pass 5): 0
-Total Feed-Alignment Movement (Pass 6): 0
-Total Feed-Alignment Movement (Pass 7): 0
-Total Feed-Alignment Movement (Pass 8): 0
-
-The rand generator seed was at globroute() : 987654321
-
-
-Total Number of Net Segments: 9
-Number of Switchable Net Segments: 0
-
-Number of channels: 3
-
-
-
-THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
-
-
-no. of accepted flips: 0
-no. of attempted flips: 0
-THIS IS THE NUMBER OF TRACKS: 5
-
-
-
-FINAL NUMBER OF ROUTING TRACKS: 5
-
-MAX OF CHANNEL: 1 is: 0
-MAX OF CHANNEL: 2 is: 4
-MAX OF CHANNEL: 3 is: 1
-FINAL TOTAL INTERCONNECT LENGTH: 978
-FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
-MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
-
-
-cost_scale_factor:3.90616
-
-Number of Feed Thrus: 0
-Number of Implicit Feed Thrus: 0
-
-Statistics:
-Number of Standard Cells: 10
-Number of Pads: 0
-Number of Nets: 15
-Number of Pins: 46
-Usage statistics not available
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.230173 # Number of seconds simulated
-sim_ticks 230173357500 # Number of ticks simulated
-final_tick 230173357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1098511 # Simulator instruction rate (inst/s)
-host_op_rate 1158108 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1471393960 # Simulator tick rate (ticks/s)
-host_mem_usage 313104 # Number of bytes of host memory used
-host_seconds 156.43 # Real time elapsed on the host
-sim_insts 171842483 # Number of instructions simulated
-sim_ops 181165370 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory
-system.physmem.bytes_read::total 220992 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 480751 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 479360 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 960111 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 480751 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 480751 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 460346715 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 171842483 # Number of instructions committed
-system.cpu.committedOps 181165370 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
-system.cpu.num_func_calls 3545028 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls
-system.cpu.num_int_insts 143085668 # number of integer instructions
-system.cpu.num_fp_insts 1752310 # number of float instructions
-system.cpu.num_int_register_reads 242291225 # number of times the integer registers were read
-system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 626384527 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written
-system.cpu.num_mem_refs 40540779 # number of memory refs
-system.cpu.num_load_insts 27896144 # Number of load instructions
-system.cpu.num_store_insts 12644635 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 460346714.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 40300311 # Number of branches fetched
-system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction
-system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction
-system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction
-system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 181650742 # Class of executed instruction
-system.cpu.dcache.tags.replacements 40 # number of replacements
-system.cpu.dcache.tags.tagsinuse 1363.619277 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619277 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits
-system.cpu.dcache.overall_hits::total 40117812 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
-system.cpu.dcache.overall_misses::total 1789 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles
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-system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52552.053210 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52536.392405 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52547.861076 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52527.930403 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52527.930403 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52541.558065 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52541.558065 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1729 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 632 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 2361 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70024500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25596000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 95620500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44226000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44226000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70024500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 69822000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 139846500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70024500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 69822000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 139846500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6102 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3594 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 9696 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 4856 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 2361 # Transaction distribution
-system.membus.trans_dist::ReadResp 2361 # Transaction distribution
-system.membus.trans_dist::ReadExReq 1092 # Transaction distribution
-system.membus.trans_dist::ReadExResp 1092 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3453 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 3453 # Request fanout histogram
-system.membus.reqLayer0.occupancy 3596500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 17408500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.dtb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.interrupts]
-type=SparcInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=SparcISA
-eventq_index=0
-
-[system.cpu.itb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/twolf
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 22 2014 17:04:27
-gem5 started Jan 22 2014 19:48:57
-gem5 executing on u200540-lin
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
-Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav
-Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-info: Increasing stack size by one page.
-122 123 124 Exiting @ tick 96722945000 because target called exit()
+++ /dev/null
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-
-
-NOTE: Restart file .rs2 not used
-
-TimberWolf will perform a global route step
-rowSep: 1.000000
-feedThruWidth: 4
-
-******************
-BLOCK DATA
-block:1 desire:85
-block:2 desire:85
-Total Desired Length: 170
-total cell length: 168
-total block length: 168
-block x-span:84 block y-span:78
-implicit feed thru range: -84
-Using default value of bin.penalty.control:1.000000
-numBins automatically set to:5
-binWidth = average_cell_width + 0 sigma= 17
-average_cell_width is:16
-standard deviation of cell length is:23.6305
-TimberWolfSC starting from the beginning
-
-
-
-THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
-The number of nets with 1 pin is 4
-The number of nets with 2 pin is 9
-The number of nets with 3 pin is 0
-The number of nets with 4 pin is 2
-The number of nets with 5 pin is 0
-The number of nets with 6 pin is 0
-The number of nets with 7 pin is 0
-The number of nets with 8 pin is 0
-The number of nets with 9 pin is 0
-The number of nets with 10 pin or more is 0
-
-New Cost Function: Initial Horizontal Cost:242
-New Cost Function: FEEDS:0 MISSING_ROWS:-46
-
-bdxlen:86 bdylen:78
-l:0 t:78 r:86 b:0
-
-
-
-THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
-
-
-
-THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
-
-The rand generator seed was at utemp() : 1
-
-
- tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
- tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
- tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
- tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
-
- I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
- 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
- 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
- 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
- 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
- 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
- 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
- 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
- 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
- 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
- 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
- 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
- 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
- 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
- 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
- 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
- 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
- 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
- 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
- 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
- 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
- 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
- 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
- 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
- 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
- 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
- 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
- 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
- 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
- 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
- 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
- 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
- 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
- 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
- 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
- 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
- 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
- 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
- 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
- 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
- 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
- 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
- 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
- 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
- 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
- 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
- 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
- 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
- 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
- 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
- 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
- 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
- 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
- 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
- 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
- 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
- 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
- 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
- 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
- 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
- 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
- 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
- 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
- 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
- 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
- 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
- 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
- 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
- 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
- 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
- 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
- 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
- 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
- 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
- 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
- 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
- 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
- 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
- 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
- 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
- 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
- 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
- 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
- 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
- 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
- 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
- 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
- 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
- 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
- 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
- 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
- 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
- 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
- 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
- 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
- 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
- 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
- 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
- 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
- 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
-100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
-101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
-102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
-103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
-104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
-105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
-106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
-107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
-108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
-109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
-110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
-111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
-112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
-113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
-114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
-115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
-116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
-117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
-118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
-119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
-120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
-121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
-
-Initial Wiring Cost: 645 Final Wiring Cost: 732
-############## Percent Wire Cost Reduction: -13
-
-
-Initial Wire Length: 645 Final Wire Length: 732
-************** Percent Wire Length Reduction: -13
-
-
-Initial Horiz. Wire: 216 Final Horiz. Wire: 147
-$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
-
-
-Initial Vert. Wire: 429 Final Vert. Wire: 585
-@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
-
-Before Feeds are Added:
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 82 -20
- 2 86 -16
-
-LONGEST Block is:2 Its length is:86
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 86 -16
- 2 86 -16
-
-LONGEST Block is:1 Its length is:86
-Added: 1 feed-through cells
-
-Removed the cell overlaps --- Will do neighbor interchanges only now
-
-TOTAL INTERCONNECT LENGTH: 994
-OVERLAP PENALTY: 0
-
-initialRowControl: 1.650
-finalRowControl: 0.300
-iter T Wire accept
- 122 0.001 976 16%
- 123 0.001 971 0%
- 124 0.001 971 0%
-Total Feed-Alignment Movement (Pass 1): 0
-Total Feed-Alignment Movement (Pass 2): 0
-Total Feed-Alignment Movement (Pass 3): 0
-Total Feed-Alignment Movement (Pass 4): 0
-Total Feed-Alignment Movement (Pass 5): 0
-Total Feed-Alignment Movement (Pass 6): 0
-Total Feed-Alignment Movement (Pass 7): 0
-Total Feed-Alignment Movement (Pass 8): 0
-
-The rand generator seed was at globroute() : 987654321
-
-
-Total Number of Net Segments: 9
-Number of Switchable Net Segments: 0
-
-Number of channels: 3
-
-
-
-THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
-
-
-no. of accepted flips: 0
-no. of attempted flips: 0
-THIS IS THE NUMBER OF TRACKS: 5
-
-
-
-FINAL NUMBER OF ROUTING TRACKS: 5
-
-MAX OF CHANNEL: 1 is: 0
-MAX OF CHANNEL: 2 is: 4
-MAX OF CHANNEL: 3 is: 1
-FINAL TOTAL INTERCONNECT LENGTH: 978
-FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
-MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
-
-
-cost_scale_factor:3.90616
-
-Number of Feed Thrus: 0
-Number of Implicit Feed Thrus: 0
-
-Statistics:
-Number of Standard Cells: 10
-Number of Pads: 0
-Number of Nets: 15
-Number of Pins: 46
-Usage statistics not available
+++ /dev/null
-$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
-$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
-B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
-B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
-B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
+++ /dev/null
-$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
-$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
-$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
-ACOUNT_1 14 0 18 26 2 1
-twfeed1 18 0 22 26 0 1
-$COUNT_1/$FJK3_1 22 0 86 26 0 1
-$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
-$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
-$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
-$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
-$COUNT_1/$FJK3_2 22 52 86 78 0 2
+++ /dev/null
-1 0 0 86 26 0 0
-2 0 52 86 78 0 0
+++ /dev/null
-0.009592
-121
-0
-1
-0.000000
-0.500000
-3.906156
-1
-1 1 2 37 13
-2 2 0 34 65
-3 2 2 63 65
-4 1 0 59 13
-5 1 2 32 13
-6 2 0 23 65
-7 1 2 12 13
-8 2 0 6 65
-9 1 0 70 13
-10 2 0 70 65
+++ /dev/null
-0.001000
-123
-0
-2
-0.000000
-0.500000
-3.906156
-1
-1 1 2 16 13
-2 2 2 19 65
-3 2 2 14 65
-4 1 0 11 13
-5 1 2 6 13
-6 2 0 3 65
-7 1 0 2 13
-8 2 2 9 65
-9 1 0 50 13
-10 2 0 54 65
-11 1 0 84 13
+++ /dev/null
-net 1
-segment channel 2
- pin1 1 pin2 7 0 0
-net 2
-segment channel 3
-pin1 41 pin2 42 0 0
-segment channel 2
-pin1 12 pin2 3 0 0
-net 3
-segment channel 2
-pin1 35 pin2 36 0 0
-segment channel 2
-pin1 19 pin2 35 0 0
-net 4
-segment channel 2
- pin1 5 pin2 38 0 0
-net 5
-net 7
-segment channel 2
- pin1 14 pin2 43 0 0
-net 8
-segment channel 2
- pin1 23 pin2 17 0 0
-net 9
-net 11
-segment channel 2
- pin1 25 pin2 31 0 0
-net 14
-net 15
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.096723 # Number of seconds simulated
-sim_ticks 96722945000 # Number of ticks simulated
-final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2119754 # Simulator instruction rate (inst/s)
-host_op_rate 2119756 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1059884256 # Simulator tick rate (ticks/s)
-host_mem_usage 284956 # Number of bytes of host memory used
-host_seconds 91.26 # Real time elapsed on the host
-sim_insts 193444518 # Number of instructions simulated
-sim_ops 193444756 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory
-system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 773782140 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 773782140 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 72065412 # Number of bytes written to this memory
-system.physmem.bytes_written::total 72065412 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 193445535 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 57735068 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 251180603 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 18976439 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 18976439 # Number of write requests responded to by this memory
-system.physmem.num_other::cpu.data 22406 # Number of other requests responded to by this memory
-system.physmem.num_other::total 22406 # Number of other requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7999985319 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2310345420 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 10310330739 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7999985319 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7999985319 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 745070490 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 745070490 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 251180603 # Transaction distribution
-system.membus.trans_dist::ReadResp 251180603 # Transaction distribution
-system.membus.trans_dist::WriteReq 18976439 # Transaction distribution
-system.membus.trans_dist::WriteResp 18976439 # Transaction distribution
-system.membus.trans_dist::SwapReq 22406 # Transaction distribution
-system.membus.trans_dist::SwapResp 22406 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 386891070 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 153467826 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 540358896 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 773782140 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 295708073 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1069490213 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 270179448 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.715989 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.450942 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 76733913 28.40% 28.40% # Request fanout histogram
-system.membus.snoop_fanout::1 193445535 71.60% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 270179448 # Request fanout histogram
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.workload.num_syscalls 401 # Number of system calls
-system.cpu.numCycles 193445891 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 193444518 # Number of instructions committed
-system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses
-system.cpu.num_func_calls 1957920 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls
-system.cpu.num_int_insts 167974806 # number of integer instructions
-system.cpu.num_fp_insts 1970372 # number of float instructions
-system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read
-system.cpu.num_int_register_writes 163060124 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written
-system.cpu.num_mem_refs 76733958 # number of memory refs
-system.cpu.num_load_insts 57735091 # Number of load instructions
-system.cpu.num_store_insts 18998867 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 193445890.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 15132745 # Number of branches fetched
-system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction
-system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction
-system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction
-system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction
-system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 193445773 # Class of executed instruction
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=262144
-
-[system.cpu.dtb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=SparcInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=SparcISA
-eventq_index=0
-
-[system.cpu.itb]
-type=SparcTLB
-eventq_index=0
-size=64
-
-[system.cpu.l2cache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_top_level=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/twolf
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 22 2014 17:04:27
-gem5 started Jan 22 2014 19:50:23
-gem5 executing on u200540-lin
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
-Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
-Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-info: Increasing stack size by one page.
-122 123 124 Exiting @ tick 270563082000 because target called exit()
+++ /dev/null
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-
-
-NOTE: Restart file .rs2 not used
-
-TimberWolf will perform a global route step
-rowSep: 1.000000
-feedThruWidth: 4
-
-******************
-BLOCK DATA
-block:1 desire:85
-block:2 desire:85
-Total Desired Length: 170
-total cell length: 168
-total block length: 168
-block x-span:84 block y-span:78
-implicit feed thru range: -84
-Using default value of bin.penalty.control:1.000000
-numBins automatically set to:5
-binWidth = average_cell_width + 0 sigma= 17
-average_cell_width is:16
-standard deviation of cell length is:23.6305
-TimberWolfSC starting from the beginning
-
-
-
-THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
-The number of nets with 1 pin is 4
-The number of nets with 2 pin is 9
-The number of nets with 3 pin is 0
-The number of nets with 4 pin is 2
-The number of nets with 5 pin is 0
-The number of nets with 6 pin is 0
-The number of nets with 7 pin is 0
-The number of nets with 8 pin is 0
-The number of nets with 9 pin is 0
-The number of nets with 10 pin or more is 0
-
-New Cost Function: Initial Horizontal Cost:242
-New Cost Function: FEEDS:0 MISSING_ROWS:-46
-
-bdxlen:86 bdylen:78
-l:0 t:78 r:86 b:0
-
-
-
-THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
-
-
-
-THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
-
-The rand generator seed was at utemp() : 1
-
-
- tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
- tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
- tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
- tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
-
- I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
- 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
- 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
- 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
- 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
- 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
- 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
- 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
- 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
- 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
- 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
- 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
- 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
- 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
- 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
- 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
- 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
- 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
- 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
- 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
- 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
- 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
- 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
- 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
- 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
- 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
- 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
- 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
- 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
- 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
- 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
- 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
- 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
- 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
- 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
- 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
- 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
- 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
- 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
- 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
- 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
- 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
- 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
- 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
- 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
- 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
- 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
- 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
- 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
- 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
- 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
- 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
- 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
- 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
- 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
- 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
- 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
- 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
- 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
- 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
- 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
- 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
- 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
- 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
- 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
- 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
- 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
- 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
- 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
- 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
- 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
- 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
- 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
- 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
- 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
- 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
- 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
- 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
- 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
- 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
- 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
- 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
- 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
- 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
- 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
- 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
- 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
- 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
- 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
- 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
- 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
- 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
- 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
- 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
- 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
- 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
- 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
- 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
- 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
- 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
-100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
-101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
-102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
-103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
-104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
-105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
-106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
-107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
-108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
-109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
-110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
-111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
-112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
-113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
-114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
-115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
-116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
-117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
-118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
-119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
-120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
-121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
-
-Initial Wiring Cost: 645 Final Wiring Cost: 732
-############## Percent Wire Cost Reduction: -13
-
-
-Initial Wire Length: 645 Final Wire Length: 732
-************** Percent Wire Length Reduction: -13
-
-
-Initial Horiz. Wire: 216 Final Horiz. Wire: 147
-$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
-
-
-Initial Vert. Wire: 429 Final Vert. Wire: 585
-@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
-
-Before Feeds are Added:
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 82 -20
- 2 86 -16
-
-LONGEST Block is:2 Its length is:86
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 86 -16
- 2 86 -16
-
-LONGEST Block is:1 Its length is:86
-Added: 1 feed-through cells
-
-Removed the cell overlaps --- Will do neighbor interchanges only now
-
-TOTAL INTERCONNECT LENGTH: 994
-OVERLAP PENALTY: 0
-
-initialRowControl: 1.650
-finalRowControl: 0.300
-iter T Wire accept
- 122 0.001 976 16%
- 123 0.001 971 0%
- 124 0.001 971 0%
-Total Feed-Alignment Movement (Pass 1): 0
-Total Feed-Alignment Movement (Pass 2): 0
-Total Feed-Alignment Movement (Pass 3): 0
-Total Feed-Alignment Movement (Pass 4): 0
-Total Feed-Alignment Movement (Pass 5): 0
-Total Feed-Alignment Movement (Pass 6): 0
-Total Feed-Alignment Movement (Pass 7): 0
-Total Feed-Alignment Movement (Pass 8): 0
-
-The rand generator seed was at globroute() : 987654321
-
-
-Total Number of Net Segments: 9
-Number of Switchable Net Segments: 0
-
-Number of channels: 3
-
-
-
-THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
-
-
-no. of accepted flips: 0
-no. of attempted flips: 0
-THIS IS THE NUMBER OF TRACKS: 5
-
-
-
-FINAL NUMBER OF ROUTING TRACKS: 5
-
-MAX OF CHANNEL: 1 is: 0
-MAX OF CHANNEL: 2 is: 4
-MAX OF CHANNEL: 3 is: 1
-FINAL TOTAL INTERCONNECT LENGTH: 978
-FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
-MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
-
-
-cost_scale_factor:3.90616
-
-Number of Feed Thrus: 0
-Number of Implicit Feed Thrus: 0
-
-Statistics:
-Number of Standard Cells: 10
-Number of Pads: 0
-Number of Nets: 15
-Number of Pins: 46
-Usage statistics not available
+++ /dev/null
-$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
-$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
-B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
-B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
-B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
+++ /dev/null
-$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
-$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
-$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
-ACOUNT_1 14 0 18 26 2 1
-twfeed1 18 0 22 26 0 1
-$COUNT_1/$FJK3_1 22 0 86 26 0 1
-$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
-$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
-$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
-$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
-$COUNT_1/$FJK3_2 22 52 86 78 0 2
+++ /dev/null
-1 0 0 86 26 0 0
-2 0 52 86 78 0 0
+++ /dev/null
-0.009592
-121
-0
-1
-0.000000
-0.500000
-3.906156
-1
-1 1 2 37 13
-2 2 0 34 65
-3 2 2 63 65
-4 1 0 59 13
-5 1 2 32 13
-6 2 0 23 65
-7 1 2 12 13
-8 2 0 6 65
-9 1 0 70 13
-10 2 0 70 65
+++ /dev/null
-0.001000
-123
-0
-2
-0.000000
-0.500000
-3.906156
-1
-1 1 2 16 13
-2 2 2 19 65
-3 2 2 14 65
-4 1 0 11 13
-5 1 2 6 13
-6 2 0 3 65
-7 1 0 2 13
-8 2 2 9 65
-9 1 0 50 13
-10 2 0 54 65
-11 1 0 84 13
+++ /dev/null
-net 1
-segment channel 2
- pin1 1 pin2 7 0 0
-net 2
-segment channel 3
-pin1 41 pin2 42 0 0
-segment channel 2
-pin1 12 pin2 3 0 0
-net 3
-segment channel 2
-pin1 35 pin2 36 0 0
-segment channel 2
-pin1 19 pin2 35 0 0
-net 4
-segment channel 2
- pin1 5 pin2 38 0 0
-net 5
-net 7
-segment channel 2
- pin1 14 pin2 43 0 0
-net 8
-segment channel 2
- pin1 23 pin2 17 0 0
-net 9
-net 11
-segment channel 2
- pin1 25 pin2 31 0 0
-net 14
-net 15
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.270563 # Number of seconds simulated
-sim_ticks 270563082500 # Number of ticks simulated
-final_tick 270563082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1283602 # Simulator instruction rate (inst/s)
-host_op_rate 1283603 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1795321724 # Simulator tick rate (ticks/s)
-host_mem_usage 297332 # Number of bytes of host memory used
-host_seconds 150.70 # Real time elapsed on the host
-sim_insts 193444518 # Number of instructions simulated
-sim_ops 193444756 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory
-system.physmem.bytes_read::total 331072 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 850848 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 372793 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1223641 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 850848 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 850848 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.workload.num_syscalls 401 # Number of system calls
-system.cpu.numCycles 541126165 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 193444518 # Number of instructions committed
-system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses
-system.cpu.num_func_calls 1957920 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls
-system.cpu.num_int_insts 167974806 # number of integer instructions
-system.cpu.num_fp_insts 1970372 # number of float instructions
-system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read
-system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written
-system.cpu.num_mem_refs 76733958 # number of memory refs
-system.cpu.num_load_insts 57735091 # Number of load instructions
-system.cpu.num_store_insts 18998867 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 541126164.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 15132745 # Number of branches fetched
-system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction
-system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction
-system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction
-system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction
-system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction
-system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 193445773 # Class of executed instruction
-system.cpu.dcache.tags.replacements 2 # number of replacements
-system.cpu.dcache.tags.tagsinuse 1237.203936 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203936 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits
-system.cpu.dcache.overall_hits::total 76709932 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses
-system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses
-system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses
-system.cpu.dcache.overall_misses::total 1575 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2 # number of writebacks
-system.cpu.dcache.writebacks::total 2 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26643000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 26643000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57619500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 57619500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53500 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total 53500 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84262500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 84262500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84262500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 84262500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53500 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53500 # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 10362 # number of replacements
-system.cpu.icache.tags.tagsinuse 1591.579164 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579164 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits
-system.cpu.icache.overall_hits::total 193433248 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses
-system.cpu.icache.overall_misses::total 12288 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 310818500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 310818500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 310818500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 310818500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 310818500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.474284 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 25294.474284 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 25294.474284 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 25294.474284 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292386500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 292386500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292386500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 292386500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292386500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 292386500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23794.474284 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23794.474284 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23794.474284 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 23794.474284 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23794.474284 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 23794.474284 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 2678.340853 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282913 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057487 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 116103 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 116103 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 2 # number of Writeback hits
-system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits
-system.cpu.l2cache.overall_hits::total 8691 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3597 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 498 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 4095 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses
-system.cpu.l2cache.overall_misses::total 5173 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 188843000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26145000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 214988000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56595000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 56595000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 188843000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 82740000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 271583000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 188843000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 82740000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 271583000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 12288 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 498 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 12786 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 2 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 2 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.320272 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.139005 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.122100 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52500.096656 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52500.096656 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 4095 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145678500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20169000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 165847500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43659000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43659000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145678500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63828000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 209506500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145678500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63828000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 209506500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24576 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 27730 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 13866 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 13866 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 13866 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 4095 # Transaction distribution
-system.membus.trans_dist::ReadResp 4095 # Transaction distribution
-system.membus.trans_dist::ReadExReq 1078 # Transaction distribution
-system.membus.trans_dist::ReadExResp 1078 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 5173 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 5173 # Request fanout histogram
-system.membus.reqLayer0.occupancy 5173500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 25865500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=apic_clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.membus.slave[4]
-
-[system.cpu.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu.apic_clk_domain
-eventq_index=0
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-system=system
-int_master=system.membus.slave[5]
-int_slave=system.membus.master[2]
-pio=system.membus.master[1]
-
-[system.cpu.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.membus.slave[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 22 2014 17:10:34
-gem5 started Jan 22 2014 22:11:10
-gem5 executing on u200540-lin
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
-Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
-Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 131393279000 because target called exit()
+++ /dev/null
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-
-
-NOTE: Restart file .rs2 not used
-
-TimberWolf will perform a global route step
-rowSep: 1.000000
-feedThruWidth: 4
-
-******************
-BLOCK DATA
-block:1 desire:85
-block:2 desire:85
-Total Desired Length: 170
-total cell length: 168
-total block length: 168
-block x-span:84 block y-span:78
-implicit feed thru range: -84
-Using default value of bin.penalty.control:1.000000
-numBins automatically set to:5
-binWidth = average_cell_width + 0 sigma= 17
-average_cell_width is:16
-standard deviation of cell length is:23.6305
-TimberWolfSC starting from the beginning
-
-
-
-THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
-The number of nets with 1 pin is 4
-The number of nets with 2 pin is 9
-The number of nets with 3 pin is 0
-The number of nets with 4 pin is 2
-The number of nets with 5 pin is 0
-The number of nets with 6 pin is 0
-The number of nets with 7 pin is 0
-The number of nets with 8 pin is 0
-The number of nets with 9 pin is 0
-The number of nets with 10 pin or more is 0
-
-New Cost Function: Initial Horizontal Cost:242
-New Cost Function: FEEDS:0 MISSING_ROWS:-46
-
-bdxlen:86 bdylen:78
-l:0 t:78 r:86 b:0
-
-
-
-THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
-
-
-
-THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
-
-The rand generator seed was at utemp() : 1
-
-
- tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
- tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
- tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
- tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
-
- I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
- 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
- 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
- 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
- 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
- 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
- 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
- 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
- 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
- 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
- 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
- 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
- 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
- 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
- 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
- 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
- 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
- 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
- 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
- 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
- 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
- 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
- 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
- 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
- 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
- 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
- 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
- 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
- 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
- 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
- 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
- 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
- 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
- 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
- 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
- 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
- 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
- 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
- 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
- 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
- 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
- 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
- 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
- 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
- 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
- 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
- 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
- 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
- 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
- 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
- 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
- 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
- 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
- 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
- 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
- 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
- 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
- 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
- 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
- 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
- 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
- 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
- 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
- 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
- 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
- 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
- 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
- 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
- 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
- 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
- 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
- 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
- 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
- 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
- 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
- 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
- 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
- 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
- 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
- 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
- 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
- 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
- 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
- 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
- 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
- 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
- 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
- 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
- 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
- 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
- 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
- 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
- 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
- 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
- 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
- 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
- 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
- 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
- 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
- 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
-100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
-101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
-102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
-103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
-104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
-105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
-106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
-107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
-108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
-109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
-110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
-111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
-112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
-113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
-114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
-115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
-116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
-117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
-118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
-119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
-120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
-121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
-
-Initial Wiring Cost: 645 Final Wiring Cost: 732
-############## Percent Wire Cost Reduction: -13
-
-
-Initial Wire Length: 645 Final Wire Length: 732
-************** Percent Wire Length Reduction: -13
-
-
-Initial Horiz. Wire: 216 Final Horiz. Wire: 147
-$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
-
-
-Initial Vert. Wire: 429 Final Vert. Wire: 585
-@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
-
-Before Feeds are Added:
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 82 -20
- 2 86 -16
-
-LONGEST Block is:2 Its length is:86
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 86 -16
- 2 86 -16
-
-LONGEST Block is:1 Its length is:86
-Added: 1 feed-through cells
-
-Removed the cell overlaps --- Will do neighbor interchanges only now
-
-TOTAL INTERCONNECT LENGTH: 994
-OVERLAP PENALTY: 0
-
-initialRowControl: 1.650
-finalRowControl: 0.300
-iter T Wire accept
- 122 0.001 976 16%
- 123 0.001 971 0%
- 124 0.001 971 0%
-Total Feed-Alignment Movement (Pass 1): 0
-Total Feed-Alignment Movement (Pass 2): 0
-Total Feed-Alignment Movement (Pass 3): 0
-Total Feed-Alignment Movement (Pass 4): 0
-Total Feed-Alignment Movement (Pass 5): 0
-Total Feed-Alignment Movement (Pass 6): 0
-Total Feed-Alignment Movement (Pass 7): 0
-Total Feed-Alignment Movement (Pass 8): 0
-
-The rand generator seed was at globroute() : 987654321
-
-
-Total Number of Net Segments: 9
-Number of Switchable Net Segments: 0
-
-Number of channels: 3
-
-
-
-THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
-
-
-no. of accepted flips: 0
-no. of attempted flips: 0
-THIS IS THE NUMBER OF TRACKS: 5
-
-
-
-FINAL NUMBER OF ROUTING TRACKS: 5
-
-MAX OF CHANNEL: 1 is: 0
-MAX OF CHANNEL: 2 is: 4
-MAX OF CHANNEL: 3 is: 1
-FINAL TOTAL INTERCONNECT LENGTH: 978
-FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
-MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
-
-
-cost_scale_factor:3.90616
-
-Number of Feed Thrus: 0
-Number of Implicit Feed Thrus: 0
-
-Statistics:
-Number of Standard Cells: 10
-Number of Pads: 0
-Number of Nets: 15
-Number of Pins: 46
-Usage statistics not available
+++ /dev/null
-$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
-$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
-B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
-B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
-B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
+++ /dev/null
-$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
-$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
-$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
-ACOUNT_1 14 0 18 26 2 1
-twfeed1 18 0 22 26 0 1
-$COUNT_1/$FJK3_1 22 0 86 26 0 1
-$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
-$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
-$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
-$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
-$COUNT_1/$FJK3_2 22 52 86 78 0 2
+++ /dev/null
-1 0 0 86 26 0 0
-2 0 52 86 78 0 0
+++ /dev/null
-0.009592
-121
-0
-1
-0.000000
-0.500000
-3.906156
-1
-1 1 2 37 13
-2 2 0 34 65
-3 2 2 63 65
-4 1 0 59 13
-5 1 2 32 13
-6 2 0 23 65
-7 1 2 12 13
-8 2 0 6 65
-9 1 0 70 13
-10 2 0 70 65
+++ /dev/null
-0.001000
-123
-0
-2
-0.000000
-0.500000
-3.906156
-1
-1 1 2 16 13
-2 2 2 19 65
-3 2 2 14 65
-4 1 0 11 13
-5 1 2 6 13
-6 2 0 3 65
-7 1 0 2 13
-8 2 2 9 65
-9 1 0 50 13
-10 2 0 54 65
-11 1 0 84 13
+++ /dev/null
-net 1
-segment channel 2
- pin1 1 pin2 7 0 0
-net 2
-segment channel 3
-pin1 41 pin2 42 0 0
-segment channel 2
-pin1 12 pin2 3 0 0
-net 3
-segment channel 2
-pin1 35 pin2 36 0 0
-segment channel 2
-pin1 19 pin2 35 0 0
-net 4
-segment channel 2
- pin1 5 pin2 38 0 0
-net 5
-net 7
-segment channel 2
- pin1 14 pin2 43 0 0
-net 8
-segment channel 2
- pin1 23 pin2 17 0 0
-net 9
-net 11
-segment channel 2
- pin1 25 pin2 31 0 0
-net 14
-net 15
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.131393 # Number of seconds simulated
-sim_ticks 131393279000 # Number of ticks simulated
-final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1264426 # Simulator instruction rate (inst/s)
-host_op_rate 2119294 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1257935779 # Simulator tick rate (ticks/s)
-host_mem_usage 324376 # Number of bytes of host memory used
-host_seconds 104.45 # Real time elapsed on the host
-sim_insts 132071193 # Number of instructions simulated
-sim_ops 221363385 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 310423752 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1698378688 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1387954936 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1387954936 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 99822191 # Number of bytes written to this memory
-system.physmem.bytes_written::total 99822191 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 173494367 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 56682005 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 230176372 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 20515731 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 20515731 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 10563363260 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2362554267 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 12925917527 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 10563363260 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 10563363260 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 759720678 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 759720678 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 230176372 # Transaction distribution
-system.membus.trans_dist::ReadResp 230176372 # Transaction distribution
-system.membus.trans_dist::WriteReq 20515731 # Transaction distribution
-system.membus.trans_dist::WriteResp 20515731 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 250692103 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.692062 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 77197736 30.79% 30.79% # Request fanout histogram
-system.membus.snoop_fanout::3 173494367 69.21% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
-system.membus.snoop_fanout::total 250692103 # Request fanout histogram
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 262786559 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 132071193 # Number of instructions committed
-system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
-system.cpu.num_func_calls 1595632 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
-system.cpu.num_int_insts 219019986 # number of integer instructions
-system.cpu.num_fp_insts 2162459 # number of float instructions
-system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read
-system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written
-system.cpu.num_mem_refs 77165304 # number of memory refs
-system.cpu.num_load_insts 56649587 # Number of load instructions
-system.cpu.num_store_insts 20515717 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 262786558.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 12326938 # Number of branches fetched
-system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction
-system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction
-system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction
-system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction
-system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction
-system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 221363385 # Class of executed instruction
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-
-[system.cpu.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=262144
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu.apic_clk_domain
-eventq_index=0
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-system=system
-int_master=system.membus.slave[2]
-int_slave=system.membus.master[2]
-pio=system.membus.master[1]
-
-[system.cpu.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_top_level=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
-drivers=
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
-gid=100
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-snoop_filter=Null
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
-slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 22 2014 17:10:34
-gem5 started Jan 22 2014 22:12:53
-gem5 executing on u200540-lin
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
-Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
-Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 250953957000 because target called exit()
+++ /dev/null
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-
-
-NOTE: Restart file .rs2 not used
-
-TimberWolf will perform a global route step
-rowSep: 1.000000
-feedThruWidth: 4
-
-******************
-BLOCK DATA
-block:1 desire:85
-block:2 desire:85
-Total Desired Length: 170
-total cell length: 168
-total block length: 168
-block x-span:84 block y-span:78
-implicit feed thru range: -84
-Using default value of bin.penalty.control:1.000000
-numBins automatically set to:5
-binWidth = average_cell_width + 0 sigma= 17
-average_cell_width is:16
-standard deviation of cell length is:23.6305
-TimberWolfSC starting from the beginning
-
-
-
-THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
-The number of nets with 1 pin is 4
-The number of nets with 2 pin is 9
-The number of nets with 3 pin is 0
-The number of nets with 4 pin is 2
-The number of nets with 5 pin is 0
-The number of nets with 6 pin is 0
-The number of nets with 7 pin is 0
-The number of nets with 8 pin is 0
-The number of nets with 9 pin is 0
-The number of nets with 10 pin or more is 0
-
-New Cost Function: Initial Horizontal Cost:242
-New Cost Function: FEEDS:0 MISSING_ROWS:-46
-
-bdxlen:86 bdylen:78
-l:0 t:78 r:86 b:0
-
-
-
-THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
-
-
-
-THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
-
-The rand generator seed was at utemp() : 1
-
-
- tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
- tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
- tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
- tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
-
- I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
- 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
- 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
- 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
- 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
- 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
- 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
- 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
- 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
- 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
- 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
- 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
- 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
- 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
- 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
- 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
- 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
- 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
- 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
- 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
- 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
- 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
- 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
- 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
- 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
- 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
- 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
- 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
- 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
- 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
- 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
- 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
- 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
- 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
- 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
- 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
- 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
- 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
- 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
- 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
- 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
- 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
- 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
- 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
- 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
- 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
- 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
- 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
- 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
- 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
- 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
- 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
- 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
- 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
- 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
- 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
- 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
- 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
- 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
- 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
- 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
- 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
- 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
- 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
- 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
- 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
- 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
- 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
- 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
- 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
- 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
- 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
- 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
- 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
- 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
- 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
- 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
- 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
- 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
- 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
- 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
- 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
- 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
- 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
- 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
- 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
- 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
- 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
- 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
- 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
- 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
- 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
- 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
- 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
- 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
- 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
- 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
- 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
- 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
- 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
-100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
-101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
-102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
-103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
-104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
-105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
-106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
-107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
-108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
-109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
-110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
-111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
-112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
-113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
-114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
-115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
-116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
-117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
-118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
-119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
-120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
-121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
-
-Initial Wiring Cost: 645 Final Wiring Cost: 732
-############## Percent Wire Cost Reduction: -13
-
-
-Initial Wire Length: 645 Final Wire Length: 732
-************** Percent Wire Length Reduction: -13
-
-
-Initial Horiz. Wire: 216 Final Horiz. Wire: 147
-$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
-
-
-Initial Vert. Wire: 429 Final Vert. Wire: 585
-@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
-
-Before Feeds are Added:
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 82 -20
- 2 86 -16
-
-LONGEST Block is:2 Its length is:86
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 86 -16
- 2 86 -16
-
-LONGEST Block is:1 Its length is:86
-Added: 1 feed-through cells
-
-Removed the cell overlaps --- Will do neighbor interchanges only now
-
-TOTAL INTERCONNECT LENGTH: 994
-OVERLAP PENALTY: 0
-
-initialRowControl: 1.650
-finalRowControl: 0.300
-iter T Wire accept
- 122 0.001 976 16%
- 123 0.001 971 0%
- 124 0.001 971 0%
-Total Feed-Alignment Movement (Pass 1): 0
-Total Feed-Alignment Movement (Pass 2): 0
-Total Feed-Alignment Movement (Pass 3): 0
-Total Feed-Alignment Movement (Pass 4): 0
-Total Feed-Alignment Movement (Pass 5): 0
-Total Feed-Alignment Movement (Pass 6): 0
-Total Feed-Alignment Movement (Pass 7): 0
-Total Feed-Alignment Movement (Pass 8): 0
-
-The rand generator seed was at globroute() : 987654321
-
-
-Total Number of Net Segments: 9
-Number of Switchable Net Segments: 0
-
-Number of channels: 3
-
-
-
-THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
-
-
-no. of accepted flips: 0
-no. of attempted flips: 0
-THIS IS THE NUMBER OF TRACKS: 5
-
-
-
-FINAL NUMBER OF ROUTING TRACKS: 5
-
-MAX OF CHANNEL: 1 is: 0
-MAX OF CHANNEL: 2 is: 4
-MAX OF CHANNEL: 3 is: 1
-FINAL TOTAL INTERCONNECT LENGTH: 978
-FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
-MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
-
-
-cost_scale_factor:3.90616
-
-Number of Feed Thrus: 0
-Number of Implicit Feed Thrus: 0
-
-Statistics:
-Number of Standard Cells: 10
-Number of Pads: 0
-Number of Nets: 15
-Number of Pins: 46
-Usage statistics not available
+++ /dev/null
-$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
-$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
-B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
-B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
-B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
+++ /dev/null
-$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
-$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
-$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
-ACOUNT_1 14 0 18 26 2 1
-twfeed1 18 0 22 26 0 1
-$COUNT_1/$FJK3_1 22 0 86 26 0 1
-$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
-$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
-$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
-$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
-$COUNT_1/$FJK3_2 22 52 86 78 0 2
+++ /dev/null
-1 0 0 86 26 0 0
-2 0 52 86 78 0 0
+++ /dev/null
-0.009592
-121
-0
-1
-0.000000
-0.500000
-3.906156
-1
-1 1 2 37 13
-2 2 0 34 65
-3 2 2 63 65
-4 1 0 59 13
-5 1 2 32 13
-6 2 0 23 65
-7 1 2 12 13
-8 2 0 6 65
-9 1 0 70 13
-10 2 0 70 65
+++ /dev/null
-0.001000
-123
-0
-2
-0.000000
-0.500000
-3.906156
-1
-1 1 2 16 13
-2 2 2 19 65
-3 2 2 14 65
-4 1 0 11 13
-5 1 2 6 13
-6 2 0 3 65
-7 1 0 2 13
-8 2 2 9 65
-9 1 0 50 13
-10 2 0 54 65
-11 1 0 84 13
+++ /dev/null
-net 1
-segment channel 2
- pin1 1 pin2 7 0 0
-net 2
-segment channel 3
-pin1 41 pin2 42 0 0
-segment channel 2
-pin1 12 pin2 3 0 0
-net 3
-segment channel 2
-pin1 35 pin2 36 0 0
-segment channel 2
-pin1 19 pin2 35 0 0
-net 4
-segment channel 2
- pin1 5 pin2 38 0 0
-net 5
-net 7
-segment channel 2
- pin1 14 pin2 43 0 0
-net 8
-segment channel 2
- pin1 23 pin2 17 0 0
-net 9
-net 11
-segment channel 2
- pin1 25 pin2 31 0 0
-net 14
-net 15
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.250954 # Number of seconds simulated
-sim_ticks 250953957500 # Number of ticks simulated
-final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 722726 # Simulator instruction rate (inst/s)
-host_op_rate 1211354 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1373280924 # Simulator tick rate (ticks/s)
-host_mem_usage 338728 # Number of bytes of host memory used
-host_seconds 182.74 # Real time elapsed on the host
-sim_insts 132071193 # Number of instructions simulated
-sim_ops 221363385 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory
-system.physmem.bytes_read::total 303040 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 724276 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 483276 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1207552 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 724276 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 724276 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 501907915 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 132071193 # Number of instructions committed
-system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
-system.cpu.num_func_calls 1595632 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
-system.cpu.num_int_insts 219019986 # number of integer instructions
-system.cpu.num_fp_insts 2162459 # number of float instructions
-system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read
-system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written
-system.cpu.num_mem_refs 77165304 # number of memory refs
-system.cpu.num_load_insts 56649587 # Number of load instructions
-system.cpu.num_store_insts 20515717 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 501907914.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 12326938 # Number of branches fetched
-system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction
-system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction
-system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction
-system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction
-system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction
-system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction
-system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction
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-system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id
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-system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits
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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
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-system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.978593 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.629357 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52506.161972 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.687500 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52506.012658 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52504.012672 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52504.012672 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2840 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 320 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 3160 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115020000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12960000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 127980000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63787500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63787500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115020000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 76747500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 191767500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115020000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 76747500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 191767500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.629357 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9388 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3817 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 13205 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 6606 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 6606 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 6606 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 3160 # Transaction distribution
-system.membus.trans_dist::ReadResp 3160 # Transaction distribution
-system.membus.trans_dist::ReadExReq 1575 # Transaction distribution
-system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 4735 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 4735 # Request fanout histogram
-system.membus.reqLayer0.occupancy 4754000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 23694000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
-cache_line_size=64
-clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_generic_timer=false
-have_large_asid_64=false
-have_lpae=false
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=atomic
-mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-num_work_ids=16
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
-reset_addr_64=0
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-delay=50000
-eventq_index=0
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=AtomicSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu0.dstage2_mmu
-dtb=system.cpu0.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-istage2_mmu=system.cpu0.istage2_mmu
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-width=1
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=6
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=8
-two_queue=false
-write_buffers=16
-cpu_side=system.cpu0.dcache_port
-mem_side=system.cpu0.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu0.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.dtb
-
-[system.cpu0.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu0.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu0.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu0.toL2Bus.slave[3]
-
-[system.cpu0.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=1
-is_top_level=true
-max_miss_count=0
-mshrs=2
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=8
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu0.icache_port
-mem_side=system.cpu0.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=1
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=ArmISA
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu0.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.itb
-
-[system.cpu0.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.istage2_mmu.stage2_tlb.walker
-
-[system.cpu0.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu0.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu0.toL2Bus.slave[2]
-
-[system.cpu0.l2cache]
-type=BaseCache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615
-assoc=16
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=12
-is_top_level=false
-max_miss_count=0
-mshrs=16
-prefetch_on_access=true
-prefetcher=system.cpu0.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tags=system.cpu0.l2cache.tags
-tgts_per_mshr=8
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu0.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu0.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=12
-sequential_access=false
-size=1048576
-
-[system.cpu0.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-response_latency=1
-snoop_filter=Null
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=AtomicSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=1
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu1.dstage2_mmu
-dtb=system.cpu1.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu1.interrupts
-isa=system.cpu1.isa
-istage2_mmu=system.cpu1.istage2_mmu
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu1.tracer
-width=1
-workload=
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=6
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.dcache.tags
-tgts_per_mshr=8
-two_queue=false
-write_buffers=16
-cpu_side=system.cpu1.dcache_port
-mem_side=system.cpu1.toL2Bus.slave[1]
-
-[system.cpu1.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu1.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.dtb
-
-[system.cpu1.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu1.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu1.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu1.toL2Bus.slave[3]
-
-[system.cpu1.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=1
-is_top_level=true
-max_miss_count=0
-mshrs=2
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.icache.tags
-tgts_per_mshr=8
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu1.icache_port
-mem_side=system.cpu1.toL2Bus.slave[0]
-
-[system.cpu1.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=1
-sequential_access=false
-size=32768
-
-[system.cpu1.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu1.isa]
-type=ArmISA
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu1.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.itb
-
-[system.cpu1.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.istage2_mmu.stage2_tlb.walker
-
-[system.cpu1.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu1.toL2Bus.slave[2]
-
-[system.cpu1.l2cache]
-type=BaseCache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615
-assoc=16
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=12
-is_top_level=false
-max_miss_count=0
-mshrs=16
-prefetch_on_access=true
-prefetcher=system.cpu1.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tags=system.cpu1.l2cache.tags
-tgts_per_mshr=8
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu1.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu1.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu1.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=12
-sequential_access=false
-size=1048576
-
-[system.cpu1.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-response_latency=1
-snoop_filter=Null
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-response_latency=2
-use_default_range=true
-width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=BaseCache
-children=tags
-addr_ranges=2147483648:2415919103
-assoc=8
-clk_domain=system.clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=false
-hit_latency=50
-is_top_level=true
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.master[27]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-hit_latency=50
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_top_level=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=0
-pio_latency=100000
-pio_size=8
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=2147483648:2415919103
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470024192
-pio_latency=100000
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-disks=
-eventq_index=0
-io_shift=2
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-platform=system.realview
-system=system
-config=system.iobus.master[9]
-dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-pio_addr=470286336
-pio_latency=100000
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-platform=system.realview
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-config=system.iobus.master[26]
-dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_num=29
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-int_latency=10000
-it_lines=128
-msix_addr=0
-platform=system.realview
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-pio_addr=721420288
-pio_latency=10000
-pixel_clock=7299
-system=system
-vnc=system.vncserver
-dma=system.membus.slave[0]
-pio=system.iobus.master[5]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-disks=system.cf0
-eventq_index=0
-io_shift=0
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-platform=system.realview
-system=system
-config=system.iobus.master[24]
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-pio_addr=470155264
-pio_latency=100000
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[6]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-pio_addr=470220800
-pio_latency=100000
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-pio_addr=738721792
-pio_latency=100000
-system=system
-pio=system.membus.master[3]
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470089728
-pio_latency=100000
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:67108863
-port=system.membus.master[1]
-
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=0
-pio_latency=30000
-platform=system.realview
-size=268435456
-system=system
-pio=system.iobus.default
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-eventq_index=0
-idreg=35979264
-pio_addr=469827584
-pio_latency=100000
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-pio_addr=471269376
-pio_latency=100000
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=true
-pio_addr=469893120
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-pio_addr=470876160
-pio_latency=100000
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-pio_addr=470941696
-pio_latency=100000
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470417408
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470482944
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470548480
-pio_latency=100000
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-pio_delay=10000
-platform=system.realview
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[4]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=402653184:436207615
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470745088
-pio_latency=100000
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-response_latency=1
-snoop_filter=Null
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 29 2014 15:46:15
-gem5 started Oct 29 2014 16:01:47
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
- 0: system.cpu0.isa: ISA system set to: 0x52fab00 0x52fab00
- 0: system.cpu1.isa: ISA system set to: 0x52fab00 0x52fab00
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 47256535568000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 47.216814 # Number of seconds simulated
-sim_ticks 47216814145000 # Number of ticks simulated
-final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1225013 # Simulator instruction rate (inst/s)
-host_op_rate 1441119 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 59296512316 # Simulator tick rate (ticks/s)
-host_mem_usage 723320 # Number of bytes of host memory used
-host_seconds 796.28 # Real time elapsed on the host
-sim_insts 975457230 # Number of instructions simulated
-sim_ops 1147538415 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 154048 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128704 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 3911220 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 35234584 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 222912 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 221184 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 2638152 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 38475968 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 412928 # Number of bytes read from this memory
-system.physmem.bytes_read::total 81399700 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 3911220 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 2638152 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 6549372 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 100563072 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 100583888 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 2407 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2011 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 101520 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 550562 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 3483 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 3456 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 41328 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 601205 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6452 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1312424 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1571298 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1573901 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 3263 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 2726 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 82835 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 746230 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 4721 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 4684 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 55873 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 814879 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8745 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1723956 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 82835 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 55873 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 138708 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2129815 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 441 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2130256 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2129815 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 3263 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 82835 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 746670 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 4721 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 4684 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 55873 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 814879 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8745 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3854211 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
-system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 125229 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.inst_hits 0 # ITB inst hits
-system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 92662773 # DTB read hits
-system.cpu0.dtb.read_misses 88786 # DTB read misses
-system.cpu0.dtb.write_hits 85694958 # DTB write hits
-system.cpu0.dtb.write_misses 36443 # DTB write misses
-system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 92751559 # DTB read accesses
-system.cpu0.dtb.write_accesses 85731401 # DTB write accesses
-system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 178357731 # DTB hits
-system.cpu0.dtb.misses 125229 # DTB misses
-system.cpu0.dtb.accesses 178482960 # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 61377 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 497696393 # ITB inst hits
-system.cpu0.itb.inst_misses 61377 # ITB inst misses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 497757770 # ITB inst accesses
-system.cpu0.itb.hits 497696393 # DTB hits
-system.cpu0.itb.misses 61377 # DTB misses
-system.cpu0.itb.accesses 497757770 # DTB accesses
-system.cpu0.numCycles 94433641544 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 497466384 # Number of instructions committed
-system.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses
-system.cpu0.num_func_calls 28869117 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 536103359 # number of integer instructions
-system.cpu0.num_fp_insts 526132 # number of float instructions
-system.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written
-system.cpu0.num_mem_refs 178459396 # number of memory refs
-system.cpu0.num_load_insts 92737001 # Number of load instructions
-system.cpu0.num_store_insts 85722395 # Number of store instructions
-system.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles
-system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles
-system.cpu0.Branches 111287587 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 405476023 69.28% 69.28% # Class of executed instruction
-system.cpu0.op_class::IntMult 1232194 0.21% 69.49% # Class of executed instruction
-system.cpu0.op_class::IntDiv 59840 0.01% 69.50% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 72507 0.01% 69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction
-system.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 585300003 # Class of executed instruction
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements 6272759 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 172015744 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 6273271 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 27.420423 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 35630500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 363162158 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 363162158 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 86214905 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 86214905 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 80919887 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 80919887 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215655 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 215655 # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 262024 # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total 262024 # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036774 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 2036774 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 167134792 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 167134792 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 167350447 # number of overall hits
-system.cpu0.dcache.overall_hits::total 167350447 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 3309378 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 3309378 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1475526 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1475526 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772138 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 772138 # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 831696 # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total 831696 # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158369 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 158369 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 4784904 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 4784904 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 5557042 # number of overall misses
-system.cpu0.dcache.overall_misses::total 5557042 # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524283 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 89524283 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395413 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 82395413 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1093720 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total 1093720 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 171919696 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 171919696 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 172907489 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 172907489 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017908 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.017908 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781680 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781680 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.760429 # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072145 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072145 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027832 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.027832 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032139 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.032139 # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 4469723 # number of writebacks
-system.cpu0.dcache.writebacks::total 4469723 # number of writebacks
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 5539081 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits
-system.cpu0.icache.overall_hits::total 492212891 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses
-system.cpu0.icache.overall_misses::total 5539598 # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011129 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.011129 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011129 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
-system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements 2710840 # number of replacements
-system.cpu0.l2cache.tags.tagsinuse 16208.843540 # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs 11548798 # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs 2726836 # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs 4.235237 # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 5735.641953 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 53.550576 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 55.046098 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4528.763909 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5835.841004 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks 0.350076 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003268 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003360 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.276414 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.356191 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total 0.989309 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15944 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1162 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4591 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5299 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4659 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973145 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses 278654950 # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses 278654950 # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 269350 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 141753 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4971397 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.data 2944075 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total 8326575 # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks 4469723 # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total 4469723 # number of Writeback hits
-system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 222737 # number of WriteInvalidateReq hits
-system.cpu0.l2cache.WriteInvalidateReq_hits::total 222737 # number of WriteInvalidateReq hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3521 # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total 3521 # number of UpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data 634814 # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total 634814 # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 269350 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker 141753 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst 4971397 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data 3578889 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total 8961389 # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 269350 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker 141753 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst 4971397 # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data 3578889 # number of overall hits
-system.cpu0.l2cache.overall_hits::total 8961389 # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11316 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8593 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.inst 568201 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.data 1257257 # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total 1845367 # number of ReadReq misses
-system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 608598 # number of WriteInvalidateReq misses
-system.cpu0.l2cache.WriteInvalidateReq_misses::total 608598 # number of WriteInvalidateReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128143 # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total 128143 # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158369 # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total 158369 # number of SCUpgradeReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709409 # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total 709409 # number of ReadExReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11316 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8593 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst 568201 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data 1966666 # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total 2554776 # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11316 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8593 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst 568201 # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data 1966666 # number of overall misses
-system.cpu0.l2cache.overall_misses::total 2554776 # number of overall misses
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 280666 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 150346 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5539598 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4201332 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total 10171942 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks 4469723 # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total 4469723 # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 831335 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.WriteInvalidateReq_accesses::total 831335 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131664 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total 131664 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158369 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total 158369 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344223 # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total 1344223 # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 280666 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 150346 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data 5545555 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total 11516165 # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 280666 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 150346 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data 5545555 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total 11516165 # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057155 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102571 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.299252 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total 0.181417 # miss rate for ReadReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.732073 # miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.732073 # miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973258 # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973258 # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527747 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527747 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.057155 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102571 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354638 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total 0.221843 # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.057155 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102571 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354638 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total 0.221843 # miss rate for overall accesses
-system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks 1573452 # number of writebacks
-system.cpu0.l2cache.writebacks::total 1573452 # number of writebacks
-system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 10363949 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 10363949 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 32448 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 32448 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 4469723 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 831335 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 831335 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 131664 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158369 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 290033 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1344223 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1344223 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11165446 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17933523 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 30193699 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 694376897 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1053462589 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 3346385 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 20385280 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 3.155096 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.361996 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 17223609 84.49% 84.49% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 3161671 15.51% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 20385280 # Request fanout histogram
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 144041 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.inst_hits 0 # ITB inst hits
-system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 90153061 # DTB read hits
-system.cpu1.dtb.read_misses 111753 # DTB read misses
-system.cpu1.dtb.write_hits 81132787 # DTB write hits
-system.cpu1.dtb.write_misses 32288 # DTB write misses
-system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 90264814 # DTB read accesses
-system.cpu1.dtb.write_accesses 81165075 # DTB write accesses
-system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 171285848 # DTB hits
-system.cpu1.dtb.misses 144041 # DTB misses
-system.cpu1.dtb.accesses 171429889 # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 60885 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 478248118 # ITB inst hits
-system.cpu1.itb.inst_misses 60885 # ITB inst misses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 478309003 # ITB inst accesses
-system.cpu1.itb.hits 478248118 # DTB hits
-system.cpu1.itb.misses 60885 # DTB misses
-system.cpu1.itb.accesses 478309003 # DTB accesses
-system.cpu1.numCycles 94433634550 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 477990846 # Number of instructions committed
-system.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses
-system.cpu1.num_func_calls 28237407 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 516282159 # number of integer instructions
-system.cpu1.num_fp_insts 374678 # number of float instructions
-system.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written
-system.cpu1.num_mem_refs 171406825 # number of memory refs
-system.cpu1.num_load_insts 90251973 # Number of load instructions
-system.cpu1.num_store_insts 81154852 # Number of store instructions
-system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles
-system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles
-system.cpu1.Branches 106497601 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction
-system.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction
-system.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
-system.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction
-system.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 562879339 # Class of executed instruction
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed
-system.cpu1.dcache.tags.replacements 5945049 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.856036 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.856036 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 76990336 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 76990336 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 63447 # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total 63447 # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048907 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 2048907 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 160687900 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 160687900 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 160875754 # number of overall hits
-system.cpu1.dcache.overall_hits::total 160875754 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 1453140 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 1453140 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 427052 # number of WriteInvalidateReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::total 427052 # number of WriteInvalidateReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158842 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 158842 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 4811362 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 4811362 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 5603713 # number of overall misses
-system.cpu1.dcache.overall_misses::total 5603713 # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 490499 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::total 490499 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 2207749 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 165499262 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 165499262 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018525 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.018525 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.870648 # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.870648 # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071947 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071947 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029072 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.029072 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033660 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.033660 # miss rate for overall accesses
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 4030826 # number of writebacks
-system.cpu1.dcache.writebacks::total 4030826 # number of writebacks
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements 4741297 # number of replacements
-system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 961346635 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 961346635 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 473560604 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 473560604 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 473560604 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 473560604 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 473560604 # number of overall hits
-system.cpu1.icache.overall_hits::total 473560604 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 4741809 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 4741809 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 4741809 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 4741809 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 4741809 # number of overall misses
-system.cpu1.icache.overall_misses::total 4741809 # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 478302413 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 478302413 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 478302413 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 478302413 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 478302413 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 478302413 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009914 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.009914 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009914 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.009914 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009914 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.009914 # miss rate for overall accesses
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
-system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements 2278914 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 13451.937852 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 10861278 # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs 2294953 # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs 4.732680 # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle 9726491516500 # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 5180.760257 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 68.434503 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 91.707533 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2828.453932 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5282.581627 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks 0.316209 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004177 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005597 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.172635 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.322423 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total 0.821041 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023 105 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15934 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 64 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1583 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5963 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4534 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3771 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006409 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.972534 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses 254019378 # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses 254019378 # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 325118 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141158 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4217165 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data 3057891 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total 7741332 # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks 4030826 # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total 4030826 # number of Writeback hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 161366 # number of WriteInvalidateReq hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::total 161366 # number of WriteInvalidateReq hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3865 # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total 3865 # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614191 # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total 614191 # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 325118 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141158 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst 4217165 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data 3672082 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total 8355523 # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 325118 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141158 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst 4217165 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data 3672082 # number of overall hits
-system.cpu1.l2cache.overall_hits::total 8355523 # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12489 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9780 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst 524644 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data 1239502 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total 1786415 # number of ReadReq misses
-system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 265480 # number of WriteInvalidateReq misses
-system.cpu1.l2cache.WriteInvalidateReq_misses::total 265480 # number of WriteInvalidateReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133591 # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total 133591 # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158842 # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total 158842 # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data 701699 # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total 701699 # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12489 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9780 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst 524644 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data 1941201 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total 2488114 # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12489 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9780 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst 524644 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data 1941201 # number of overall misses
-system.cpu1.l2cache.overall_misses::total 2488114 # number of overall misses
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 337607 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 150938 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4741809 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4297393 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total 9527747 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks 4030826 # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total 4030826 # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 426846 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.WriteInvalidateReq_accesses::total 426846 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137456 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total 137456 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158842 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total 158842 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 337607 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 150938 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total 10843637 # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 337607 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150938 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total 10843637 # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.064795 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.110642 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288431 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total 0.187496 # miss rate for ReadReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.621957 # miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.621957 # miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.971882 # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.971882 # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533250 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533250 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064795 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110642 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345823 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total 0.229454 # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064795 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110642 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345823 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total 0.229454 # miss rate for overall accesses
-system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks 1183487 # number of writebacks
-system.cpu1.l2cache.writebacks::total 1183487 # number of writebacks
-system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 9645413 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 4030826 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 426846 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 426846 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 137456 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158842 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 296298 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9483878 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16729164 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 27412486 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 644579516 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 952853588 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 3730448 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 19274314 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 3.184989 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.388288 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 15708784 81.50% 81.50% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 3565530 18.50% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 19274314 # Request fanout histogram
-system.iobus.trans_dist::ReadReq 40295 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40295 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136634 # Transaction distribution
-system.iobus.trans_dist::WriteResp 29906 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.replacements 115585 # number of replacements
-system.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use
-system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
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-system.iocache.tags.tag_accesses 1040793 # Number of tag accesses
-system.iocache.tags.data_accesses 1040793 # Number of data accesses
-system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses
-system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses
-system.iocache.demand_misses::total 8916 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 8876 # number of overall misses
-system.iocache.overall_misses::total 8916 # number of overall misses
-system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
-system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks::writebacks 106694 # number of writebacks
-system.iocache.writebacks::total 106694 # number of writebacks
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 1759966 # number of replacements
-system.l2c.tags.tagsinuse 62842.185631 # Cycle average of tags in use
-system.l2c.tags.total_refs 3707512 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 1818705 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 2.038545 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 482634500 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 35219.340736 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 46.907098 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 57.886687 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 3338.956610 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 6965.181537 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 309.496433 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 430.211698 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 2959.236338 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 13514.968494 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.537404 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000716 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.000883 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.050948 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.106280 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004723 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker 0.006565 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.045154 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.206222 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.958896 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023 231 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 58508 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 549 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 3406 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 5650 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 48840 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023 0.003525 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.892761 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 66406004 # Number of tag accesses
-system.l2c.tags.data_accesses 66406004 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 6334 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 4677 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 509782 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 744386 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 5569 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 3610 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 483417 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 692017 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 2449792 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 2756939 # number of Writeback hits
-system.l2c.Writeback_hits::total 2756939 # number of Writeback hits
-system.l2c.WriteInvalidateReq_hits::cpu0.data 121538 # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu1.data 97977 # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::total 219515 # number of WriteInvalidateReq hits
-system.l2c.UpgradeReq_hits::cpu0.data 13827 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 10932 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 24759 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 1566 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 1304 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 2870 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 202688 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 171255 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 373943 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 6334 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 4677 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 509782 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 947074 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 5569 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 3610 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 483417 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 863272 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2823735 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 6334 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 4677 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 509782 # number of overall hits
-system.l2c.overall_hits::cpu0.data 947074 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 5569 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 3610 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 483417 # number of overall hits
-system.l2c.overall_hits::cpu1.data 863272 # number of overall hits
-system.l2c.overall_hits::total 2823735 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker 2407 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker 2011 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 58419 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 184134 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker 3483 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker 3456 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 41227 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 189746 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 484883 # number of ReadReq misses
-system.l2c.WriteInvalidateReq_misses::cpu0.data 479213 # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::cpu1.data 160846 # number of WriteInvalidateReq misses
-system.l2c.WriteInvalidateReq_misses::total 640059 # number of WriteInvalidateReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 58018 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 53853 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 111871 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 7722 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 7423 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 15145 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 377543 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 418309 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 795852 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 2407 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker 2011 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 58419 # number of demand (read+write) misses
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-system.l2c.demand_misses::cpu1.itb.walker 3456 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 41227 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 608055 # number of demand (read+write) misses
-system.l2c.demand_misses::total 1280735 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 2407 # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker 2011 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 58419 # number of overall misses
-system.l2c.overall_misses::cpu0.data 561677 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 3483 # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker 3456 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 41227 # number of overall misses
-system.l2c.overall_misses::cpu1.data 608055 # number of overall misses
-system.l2c.overall_misses::total 1280735 # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 8741 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 6688 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 568201 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 928520 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 9052 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 7066 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 524644 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 881763 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2934675 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 2756939 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 2756939 # number of Writeback accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu0.data 600751 # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::cpu1.data 258823 # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.WriteInvalidateReq_accesses::total 859574 # number of WriteInvalidateReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 71845 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 64785 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 136630 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 9288 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 8727 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 18015 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 580231 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 589564 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 1169795 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 8741 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 6688 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 568201 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 1508751 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 9052 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 7066 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 524644 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 1471327 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 4104470 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 8741 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 6688 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 568201 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 1508751 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 9052 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 7066 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 524644 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 1471327 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 4104470 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.300688 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.102814 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.198309 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.489103 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.078581 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.215189 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.165225 # miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.797690 # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.621452 # miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_miss_rate::total 0.744623 # miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.807544 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.831257 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.818788 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.831395 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.850579 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.840688 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.650677 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.709523 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.680335 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.300688 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.102814 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.372279 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker 0.489103 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.078581 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.413270 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.312034 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.300688 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.102814 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.372279 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker 0.489103 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.078581 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.413270 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.312034 # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 1464604 # number of writebacks
-system.l2c.writebacks::total 1464604 # number of writebacks
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 575939 # Transaction distribution
-system.membus.trans_dist::ReadResp 575939 # Transaction distribution
-system.membus.trans_dist::WriteReq 38831 # Transaction distribution
-system.membus.trans_dist::WriteResp 38831 # Transaction distribution
-system.membus.trans_dist::Writeback 1571298 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 742240 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 742240 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 327418 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 314341 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 148936 # Transaction distribution
-system.membus.trans_dist::ReadExReq 965776 # Transaction distribution
-system.membus.trans_dist::ReadExResp 778482 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6332069 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 6482289 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337982 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 337982 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6820271 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215456868 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 215667865 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229440 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 14229440 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 229897305 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 4414869 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 4414869 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 4414869 # Request fanout histogram
-system.realview.ethernet.txBytes 966 # Bytes Transmitted
-system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets 3 # Total Packets
-system.realview.ethernet.totBytes 966 # Total Bytes
-system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 3713925 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 3713925 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38831 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38831 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 2756939 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 859574 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp 859574 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 330257 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 317211 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 647468 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 1357089 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 1357089 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8689428 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7301285 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 15990713 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301218837 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249930820 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 551149657 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 117306 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 9368496 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.012344 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.110415 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 9252852 98.77% 98.77% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 115644 1.23% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 9368496 # Request fanout histogram
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[ 0.000000] Initializing cgroup subsys cpu\r
-[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[ 0.000000] Memory limited to 256MB\r
-[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[ 0.000000] On node 0 totalpages: 65536\r
-[ 0.000000] DMA zone: 896 pages used for memmap\r
-[ 0.000000] DMA zone: 0 pages reserved\r
-[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
-[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
-[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[ 0.000000] Virtual kernel memory layout:\r
-[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
-[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
-[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
-[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
-[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
-[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
-[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[ 0.000000] Preemptible hierarchical RCU implementation.\r
-[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000013] Console: colour dummy device 80x25\r
-[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000015] pid_max: default: 32768 minimum: 301\r
-[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000066] hw perfevents: no hardware support available\r
-[ 0.060015] CPU1: Booted secondary processor\r
-[ 1.080050] CPU2: failed to come online\r
-[ 2.100100] CPU3: failed to come online\r
-[ 2.100101] Brought up 2 CPUs\r
-[ 2.100102] SMP: Total of 2 processors activated.\r
-[ 2.100134] devtmpfs: initialized\r
-[ 2.100536] atomic64_test: passed\r
-[ 2.100559] regulator-dummy: no parameters\r
-[ 2.100800] NET: Registered protocol family 16\r
-[ 2.100894] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 2.100898] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 2.100937] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 2.100938] Serial: AMBA PL011 UART driver\r
-[ 2.101059] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 2.101082] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 2.101116] console [ttyAMA0] enabled\r
-[ 2.101154] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 2.101168] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 2.101183] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 2.101195] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 2.140179] 3V3: 3300 mV \r
-[ 2.140202] vgaarb: loaded\r
-[ 2.140232] SCSI subsystem initialized\r
-[ 2.140246] libata version 3.00 loaded.\r
-[ 2.140272] usbcore: registered new interface driver usbfs\r
-[ 2.140279] usbcore: registered new interface driver hub\r
-[ 2.140288] usbcore: registered new device driver usb\r
-[ 2.140300] pps_core: LinuxPPS API ver. 1 registered\r
-[ 2.140301] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 2.140304] PTP clock support registered\r
-[ 2.140381] Switched to clocksource arch_sys_counter\r
-[ 2.141215] NET: Registered protocol family 2\r
-[ 2.141272] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 2.141277] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 2.141282] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 2.141285] TCP: reno registered\r
-[ 2.141286] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.141288] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.141303] NET: Registered protocol family 1\r
-[ 2.141330] RPC: Registered named UNIX socket transport module.\r
-[ 2.141331] RPC: Registered udp transport module.\r
-[ 2.141331] RPC: Registered tcp transport module.\r
-[ 2.141332] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 2.141334] PCI: CLS 0 bytes, default 64\r
-[ 2.141433] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 2.141477] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 2.143024] fuse init (API version 7.23)\r
-[ 2.143091] msgmni has been set to 469\r
-[ 2.143142] io scheduler noop registered\r
-[ 2.143175] io scheduler cfq registered (default)\r
-[ 2.143447] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 2.143448] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 2.143450] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 2.143451] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 2.143453] pci_bus 0000:00: scanning bus\r
-[ 2.143455] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 2.143457] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 2.143460] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.143476] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 2.143477] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 2.143479] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 2.143481] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 2.143482] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 2.143484] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 2.143486] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.143503] pci_bus 0000:00: fixups for bus\r
-[ 2.143505] pci_bus 0000:00: bus scan returning with max=00\r
-[ 2.143506] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 2.143511] pci 0000:00:00.0: fixup irq: got 33\r
-[ 2.143512] pci 0000:00:00.0: assigning IRQ 33\r
-[ 2.143515] pci 0000:00:01.0: fixup irq: got 34\r
-[ 2.143516] pci 0000:00:01.0: assigning IRQ 34\r
-[ 2.143519] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 2.143520] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 2.143522] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 2.143524] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 2.143525] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 2.143527] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 2.143529] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 2.143531] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 2.143891] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 2.144060] ata_piix 0000:00:01.0: version 2.13\r
-[ 2.144062] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 2.144068] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 2.144250] scsi0 : ata_piix\r
-[ 2.144297] scsi1 : ata_piix\r
-[ 2.144314] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 2.144315] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 2.144376] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 2.144377] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 2.144381] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 2.144382] e1000 0000:00:00.0: enabling bus mastering\r
-[ 2.290388] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 2.290389] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 2.290395] ata1.00: configured for UDMA/33\r
-[ 2.290412] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 2.290466] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 2.290469] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 2.290484] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 2.290486] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 2.290493] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 2.290548] sda: sda1\r
-[ 2.290610] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 2.410644] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 2.410646] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 2.410652] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 2.410653] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 2.410661] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 2.410662] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 2.410706] usbcore: registered new interface driver usb-storage\r
-[ 2.410735] mousedev: PS/2 mouse device common for all mice\r
-[ 2.410834] usbcore: registered new interface driver usbhid\r
-[ 2.410835] usbhid: USB HID core driver\r
-[ 2.410850] TCP: cubic registered\r
-[ 2.410852] NET: Registered protocol family 17\r
-\0[ 2.411039] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 2.411050] devtmpfs: mounted\r
-[ 2.411057] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[ 2.446370] udevd[609]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[ 2.512067] random: dd urandom read with 17 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 2.610614] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-done.\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
-Starting auto-serial-console:
\ No newline at end of file
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
-cache_line_size=64
-clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_generic_timer=false
-have_large_asid_64=false
-have_lpae=false
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=atomic
-mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-num_work_ids=16
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
-reset_addr_64=0
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-delay=50000
-eventq_index=0
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_top_level=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=4194304
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-response_latency=1
-snoop_filter=Null
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-response_latency=2
-use_default_range=true
-width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=BaseCache
-children=tags
-addr_ranges=2147483648:2415919103
-assoc=8
-clk_domain=system.clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=false
-hit_latency=50
-is_top_level=true
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.master[27]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-hit_latency=50
-sequential_access=false
-size=1024
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=0
-pio_latency=100000
-pio_size=8
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=2147483648:2415919103
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470024192
-pio_latency=100000
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-disks=
-eventq_index=0
-io_shift=2
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-platform=system.realview
-system=system
-config=system.iobus.master[9]
-dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-pio_addr=470286336
-pio_latency=100000
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-platform=system.realview
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-config=system.iobus.master[26]
-dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_num=29
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-int_latency=10000
-it_lines=128
-msix_addr=0
-platform=system.realview
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-pio_addr=721420288
-pio_latency=10000
-pixel_clock=7299
-system=system
-vnc=system.vncserver
-dma=system.membus.slave[0]
-pio=system.iobus.master[5]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-disks=system.cf0
-eventq_index=0
-io_shift=0
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-platform=system.realview
-system=system
-config=system.iobus.master[24]
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-pio_addr=470155264
-pio_latency=100000
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[6]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-pio_addr=470220800
-pio_latency=100000
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-pio_addr=738721792
-pio_latency=100000
-system=system
-pio=system.membus.master[3]
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470089728
-pio_latency=100000
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:67108863
-port=system.membus.master[1]
-
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=0
-pio_latency=30000
-platform=system.realview
-size=268435456
-system=system
-pio=system.iobus.default
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-eventq_index=0
-idreg=35979264
-pio_addr=469827584
-pio_latency=100000
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-pio_addr=471269376
-pio_latency=100000
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=true
-pio_addr=469893120
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-pio_addr=470876160
-pio_latency=100000
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-pio_addr=470941696
-pio_latency=100000
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470417408
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470482944
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470548480
-pio_latency=100000
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-pio_delay=10000
-platform=system.realview
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[4]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=402653184:436207615
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470745088
-pio_latency=100000
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 29 2014 15:46:15
-gem5 started Oct 29 2014 16:00:57
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-atomic
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
- 0: system.cpu.isa: ISA system set to: 0x54cdb00 0x54cdb00
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 51111167186000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 51.111153 # Number of seconds simulated
-sim_ticks 51111152682000 # Number of ticks simulated
-final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1276359 # Simulator instruction rate (inst/s)
-host_op_rate 1499931 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 66258489115 # Simulator tick rate (ticks/s)
-host_mem_usage 712024 # Number of bytes of host memory used
-host_seconds 771.39 # Real time elapsed on the host
-sim_insts 984570519 # Number of instructions simulated
-sim_ops 1157031967 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 376512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 5562740 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 74833672 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory
-system.physmem.bytes_read::total 81627068 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 5562740 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 103042944 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 103063524 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 5883 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 127325 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1169289 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1315843 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1610046 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1612619 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 7367 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 108836 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1464136 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1597050 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 108836 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2016056 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2016459 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2016056 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 7367 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 108836 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1464539 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3613509 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
-system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 265715 # Table walker walks requested
-system.cpu.dtb.walker.walksLong 265715 # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walkWaitTime::samples 265715 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 265715 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 204282 89.47% 89.47% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M 24037 10.53% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 228319 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265715 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265715 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228319 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228319 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 494034 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 184014035 # DTB read hits
-system.cpu.dtb.read_misses 194198 # DTB read misses
-system.cpu.dtb.write_hits 168232768 # DTB write hits
-system.cpu.dtb.write_misses 71517 # DTB write misses
-system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 82353 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 9303 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 184208233 # DTB read accesses
-system.cpu.dtb.write_accesses 168304285 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 352246803 # DTB hits
-system.cpu.dtb.misses 265715 # DTB misses
-system.cpu.dtb.accesses 352512518 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 126837 # Table walker walks requested
-system.cpu.itb.walker.walksLong 126837 # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walkWaitTime::samples 126837 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 126837 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 126837 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 113576 99.02% 99.02% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M 1123 0.98% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 114699 # Table walker page sizes translated
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126837 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 126837 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114699 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 114699 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 241536 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 985047321 # ITB inst hits
-system.cpu.itb.inst_misses 126837 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 58174 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 985174158 # ITB inst accesses
-system.cpu.itb.hits 985047321 # DTB hits
-system.cpu.itb.misses 126837 # DTB misses
-system.cpu.itb.accesses 985174158 # DTB accesses
-system.cpu.numCycles 102222322140 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 984570519 # Number of instructions committed
-system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 880805 # Number of float alu accesses
-system.cpu.num_func_calls 57056367 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 151940834 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1060455466 # number of integer instructions
-system.cpu.num_fp_insts 880805 # number of float instructions
-system.cpu.num_int_register_reads 1564002170 # number of times the integer registers were read
-system.cpu.num_int_register_writes 842444791 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 747920 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 264407058 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 263829403 # number of times the CC registers were written
-system.cpu.num_mem_refs 352465606 # number of memory refs
-system.cpu.num_load_insts 184180431 # Number of load instructions
-system.cpu.num_store_insts 168285175 # Number of store instructions
-system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles
-system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles
-system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.988675 # Percentage of idle cycles
-system.cpu.Branches 220088562 # Number of branches fetched
-system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 802636616 69.33% 69.33% # Class of executed instruction
-system.cpu.op_class::IntMult 2354747 0.20% 69.54% # Class of executed instruction
-system.cpu.op_class::IntDiv 101759 0.01% 69.54% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 8 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 13 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 21 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.55% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
-system.cpu.op_class::MemRead 184180431 15.91% 85.46% # Class of executed instruction
-system.cpu.op_class::MemWrite 168285175 14.54% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 1157666593 # Class of executed instruction
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed
-system.cpu.dcache.tags.replacements 11612141 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 29.345233 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1421167352 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1421167352 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 171567259 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 171567259 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 159522870 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 159522870 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 424020 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 424020 # number of SoftPFReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337709 # number of WriteInvalidateReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::total 337709 # number of WriteInvalidateReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310545 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 4310545 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 4562464 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 331090129 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 331090129 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 331514149 # number of overall hits
-system.cpu.dcache.overall_hits::total 331514149 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 6010080 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 6010080 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2570257 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2570257 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 1584397 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 1584397 # number of SoftPFReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245349 # number of WriteInvalidateReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::total 1245349 # number of WriteInvalidateReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 253721 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 253721 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 8580337 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 8580337 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 10164734 # number of overall misses
-system.cpu.dcache.overall_misses::total 10164734 # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data 177577339 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 162093127 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008417 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 2008417 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583058 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total 1583058 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4564266 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 4562465 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 339670466 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 341678883 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 341678883 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033845 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.033845 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015857 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788879 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.788879 # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786673 # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055589 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055589 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025261 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.029749 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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-system.cpu.dcache.fast_writes 0 # number of fast writes performed
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-system.cpu.dcache.writebacks::writebacks 8921315 # number of writebacks
-system.cpu.dcache.writebacks::total 8921315 # number of writebacks
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 14295641 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 970865862 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 999458178 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 999458178 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 970865862 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 970865862 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 970865862 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 970865862 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 970865862 # number of overall hits
-system.cpu.icache.overall_hits::total 970865862 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 14296158 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 14296158 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 14296158 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 14296158 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 14296158 # number of overall misses
-system.cpu.icache.overall_misses::total 14296158 # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst 985162020 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 985162020 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses
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-system.cpu.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.014511 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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-system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 1722692 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 65341.862502 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 29983424 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 1785989 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 16.788135 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37141.715219 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.196824 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.735041 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 6261.263092 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 21184.952326 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.566738 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004733 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006771 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095539 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.323257 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 63019 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4 278 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2715 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4911 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54669 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961594 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 290307620 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 290307620 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255623 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 14211921 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 7504232 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 22478388 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 8921315 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 8921315 # number of Writeback hits
-system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 694333 # number of WriteInvalidateReq hits
-system.cpu.l2cache.WriteInvalidateReq_hits::total 694333 # number of WriteInvalidateReq hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 11223 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 11223 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 1692610 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 1692610 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 506612 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 255623 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 14211921 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 9196842 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 24170998 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 506612 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 255623 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 14211921 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 9196842 # number of overall hits
-system.cpu.l2cache.overall_hits::total 24170998 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6443 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5883 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 84237 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 343966 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 440529 # number of ReadReq misses
-system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 551016 # number of WriteInvalidateReq misses
-system.cpu.l2cache.WriteInvalidateReq_misses::total 551016 # number of WriteInvalidateReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 39917 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 39917 # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 826507 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 826507 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 6443 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker 5883 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 84237 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 1170473 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 1267036 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 6443 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker 5883 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 84237 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 1170473 # number of overall misses
-system.cpu.l2cache.overall_misses::total 1267036 # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 513055 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261506 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 14296158 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 7848198 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 22918917 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 8921315 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 8921315 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1245349 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.l2cache.WriteInvalidateReq_accesses::total 1245349 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51140 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 51140 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 2519117 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 513055 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 261506 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 14296158 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 10367315 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 25438034 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 513055 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 261506 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 14296158 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 10367315 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 25438034 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012558 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022497 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005892 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043827 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.019221 # miss rate for ReadReq accesses
-system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.442459 # miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.442459 # miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328094 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022497 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005892 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.112900 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.049809 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022497 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005892 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.112900 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.049809 # miss rate for overall accesses
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 1503415 # number of writebacks
-system.cpu.l2cache.writebacks::total 1503415 # number of writebacks
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 23372119 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28678566 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32383245 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 63363979 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 116338 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 36147883 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.003196 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.056441 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 36032362 99.68% 99.68% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram
-system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
-system.iobus.trans_dist::WriteResp 29851 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.replacements 115463 # number of replacements
-system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use
-system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1039686 # Number of tag accesses
-system.iocache.tags.data_accesses 1039686 # Number of data accesses
-system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
-system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses
-system.iocache.demand_misses::total 8857 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 8817 # number of overall misses
-system.iocache.overall_misses::total 8857 # number of overall misses
-system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
-system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks::writebacks 106631 # number of writebacks
-system.iocache.writebacks::total 106631 # number of writebacks
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 526062 # Transaction distribution
-system.membus.trans_dist::ReadResp 526062 # Transaction distribution
-system.membus.trans_dist::WriteReq 33606 # Transaction distribution
-system.membus.trans_dist::WriteResp 33606 # Transaction distribution
-system.membus.trans_dist::Writeback 1610046 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 657675 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 657675 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution
-system.membus.trans_dist::ReadExReq 825948 # Transaction distribution
-system.membus.trans_dist::ReadExResp 825948 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5310733 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5439925 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5777598 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212730912 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212899962 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3583537 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3583537 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3583537 # Request fanout histogram
-system.realview.ethernet.txBytes 966 # Bytes Transmitted
-system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets 3 # Total Packets
-system.realview.ethernet.totBytes 966 # Total Bytes
-system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[ 0.000000] Initializing cgroup subsys cpu\r
-[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[ 0.000000] Memory limited to 256MB\r
-[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[ 0.000000] On node 0 totalpages: 65536\r
-[ 0.000000] DMA zone: 896 pages used for memmap\r
-[ 0.000000] DMA zone: 0 pages reserved\r
-[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
-[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
-[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[ 0.000000] Virtual kernel memory layout:\r
-[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
-[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
-[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
-[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
-[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
-[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
-[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[ 0.000000] Preemptible hierarchical RCU implementation.\r
-[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000013] Console: colour dummy device 80x25\r
-[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000015] pid_max: default: 32768 minimum: 301\r
-[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000066] hw perfevents: no hardware support available\r
-[ 1.060049] CPU1: failed to come online\r
-[ 2.080098] CPU2: failed to come online\r
-[ 3.100148] CPU3: failed to come online\r
-[ 3.100150] Brought up 1 CPUs\r
-[ 3.100151] SMP: Total of 1 processors activated.\r
-[ 3.100177] devtmpfs: initialized\r
-[ 3.100579] atomic64_test: passed\r
-[ 3.100603] regulator-dummy: no parameters\r
-[ 3.100844] NET: Registered protocol family 16\r
-[ 3.100938] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.100941] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.100980] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.100981] Serial: AMBA PL011 UART driver\r
-[ 3.101103] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.101125] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.101160] console [ttyAMA0] enabled\r
-[ 3.101194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.101208] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.101222] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.101235] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130356] 3V3: 3300 mV \r
-[ 3.130377] vgaarb: loaded\r
-[ 3.130406] SCSI subsystem initialized\r
-[ 3.130425] libata version 3.00 loaded.\r
-[ 3.130450] usbcore: registered new interface driver usbfs\r
-[ 3.130457] usbcore: registered new interface driver hub\r
-[ 3.130471] usbcore: registered new device driver usb\r
-[ 3.130482] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.130483] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.130487] PTP clock support registered\r
-[ 3.130559] Switched to clocksource arch_sys_counter\r
-[ 3.131204] NET: Registered protocol family 2\r
-[ 3.131250] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.131255] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.131259] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.131263] TCP: reno registered\r
-[ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131281] NET: Registered protocol family 1\r
-[ 3.131310] RPC: Registered named UNIX socket transport module.\r
-[ 3.131311] RPC: Registered udp transport module.\r
-[ 3.131312] RPC: Registered tcp transport module.\r
-[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.131315] PCI: CLS 0 bytes, default 64\r
-[ 3.131413] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.131456] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.132687] fuse init (API version 7.23)\r
-[ 3.132738] msgmni has been set to 469\r
-[ 3.133992] io scheduler noop registered\r
-[ 3.134024] io scheduler cfq registered (default)\r
-[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.134301] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.134302] pci_bus 0000:00: scanning bus\r
-[ 3.134304] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.134306] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.134329] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.134336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.134354] pci_bus 0000:00: fixups for bus\r
-[ 3.134355] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.134361] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.134363] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.134365] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.134367] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.134372] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.134377] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.134813] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.134815] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.134820] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.135009] scsi0 : ata_piix\r
-[ 3.135063] scsi1 : ata_piix\r
-[ 3.135081] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.135082] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.135143] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.135144] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.135148] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.135150] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.290565] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.290566] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.290572] ata1.00: configured for UDMA/33\r
-[ 3.290589] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.290650] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.290658] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.290672] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.290673] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.290680] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.290733] sda: sda1\r
-[ 3.290795] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.410824] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.410825] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.410832] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.410833] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.410841] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.410842] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.410886] usbcore: registered new interface driver usb-storage\r
-[ 3.410912] mousedev: PS/2 mouse device common for all mice\r
-[ 3.411009] usbcore: registered new interface driver usbhid\r
-[ 3.411010] usbhid: USB HID core driver\r
-[ 3.411025] TCP: cubic registered\r
-[ 3.411026] NET: Registered protocol family 17\r
-\0[ 3.411204] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.411214] devtmpfs: mounted\r
-[ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[ 3.446950] udevd[607]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[ 3.532262] random: dd urandom read with 19 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.640780] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-done.\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
-cache_line_size=64
-clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_generic_timer=false
-have_large_asid_64=false
-have_lpae=false
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=timing
-mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-num_work_ids=16
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
-reset_addr_64=0
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-delay=50000
-eventq_index=0
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu0.dstage2_mmu
-dtb=system.cpu0.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-istage2_mmu=system.cpu0.istage2_mmu
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=6
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=8
-two_queue=false
-write_buffers=16
-cpu_side=system.cpu0.dcache_port
-mem_side=system.cpu0.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu0.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.dtb
-
-[system.cpu0.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu0.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu0.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu0.toL2Bus.slave[3]
-
-[system.cpu0.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=1
-is_top_level=true
-max_miss_count=0
-mshrs=2
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=8
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu0.icache_port
-mem_side=system.cpu0.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=1
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=ArmISA
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu0.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.itb
-
-[system.cpu0.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.istage2_mmu.stage2_tlb.walker
-
-[system.cpu0.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu0.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu0.toL2Bus.slave[2]
-
-[system.cpu0.l2cache]
-type=BaseCache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615
-assoc=16
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=12
-is_top_level=false
-max_miss_count=0
-mshrs=16
-prefetch_on_access=true
-prefetcher=system.cpu0.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tags=system.cpu0.l2cache.tags
-tgts_per_mshr=8
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu0.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu0.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=12
-sequential_access=false
-size=1048576
-
-[system.cpu0.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-response_latency=1
-snoop_filter=Null
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=1
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu1.dstage2_mmu
-dtb=system.cpu1.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu1.interrupts
-isa=system.cpu1.isa
-istage2_mmu=system.cpu1.istage2_mmu
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu1.tracer
-workload=
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=6
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.dcache.tags
-tgts_per_mshr=8
-two_queue=false
-write_buffers=16
-cpu_side=system.cpu1.dcache_port
-mem_side=system.cpu1.toL2Bus.slave[1]
-
-[system.cpu1.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu1.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.dtb
-
-[system.cpu1.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu1.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu1.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu1.toL2Bus.slave[3]
-
-[system.cpu1.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=1
-is_top_level=true
-max_miss_count=0
-mshrs=2
-prefetch_on_access=false
-prefetcher=Null
-response_latency=1
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.icache.tags
-tgts_per_mshr=8
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu1.icache_port
-mem_side=system.cpu1.toL2Bus.slave[0]
-
-[system.cpu1.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=1
-sequential_access=false
-size=32768
-
-[system.cpu1.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu1.isa]
-type=ArmISA
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu1.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.itb
-
-[system.cpu1.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.istage2_mmu.stage2_tlb.walker
-
-[system.cpu1.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu1.toL2Bus.slave[2]
-
-[system.cpu1.l2cache]
-type=BaseCache
-children=prefetcher tags
-addr_ranges=0:18446744073709551615
-assoc=16
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=12
-is_top_level=false
-max_miss_count=0
-mshrs=16
-prefetch_on_access=true
-prefetcher=system.cpu1.l2cache.prefetcher
-response_latency=12
-sequential_access=false
-size=1048576
-system=system
-tags=system.cpu1.l2cache.tags
-tgts_per_mshr=8
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu1.toL2Bus.master[0]
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu1.l2cache.prefetcher]
-type=StridePrefetcher
-cache_snoop=false
-clk_domain=system.cpu_clk_domain
-degree=8
-eventq_index=0
-latency=1
-max_conf=7
-min_conf=0
-on_data=true
-on_inst=true
-on_miss=false
-on_read=true
-on_write=true
-queue_filter=true
-queue_size=32
-queue_squash=true
-start_conf=4
-sys=system
-table_assoc=4
-table_sets=16
-tag_prefetch=true
-thresh_conf=4
-use_master_id=true
-
-[system.cpu1.l2cache.tags]
-type=RandomRepl
-assoc=16
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=12
-sequential_access=false
-size=1048576
-
-[system.cpu1.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-response_latency=1
-snoop_filter=Null
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-response_latency=2
-use_default_range=true
-width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=BaseCache
-children=tags
-addr_ranges=2147483648:2415919103
-assoc=8
-clk_domain=system.clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=false
-hit_latency=50
-is_top_level=true
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.master[27]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-hit_latency=50
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_top_level=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=0
-pio_latency=100000
-pio_size=8
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-page_policy=open_adaptive
-range=2147483648:2415919103
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470024192
-pio_latency=100000
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-disks=
-eventq_index=0
-io_shift=2
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-platform=system.realview
-system=system
-config=system.iobus.master[9]
-dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-pio_addr=470286336
-pio_latency=100000
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-platform=system.realview
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-config=system.iobus.master[26]
-dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_num=29
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-int_latency=10000
-it_lines=128
-msix_addr=0
-platform=system.realview
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-pio_addr=721420288
-pio_latency=10000
-pixel_clock=7299
-system=system
-vnc=system.vncserver
-dma=system.membus.slave[0]
-pio=system.iobus.master[5]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-disks=system.cf0
-eventq_index=0
-io_shift=0
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-platform=system.realview
-system=system
-config=system.iobus.master[24]
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-pio_addr=470155264
-pio_latency=100000
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[6]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-pio_addr=470220800
-pio_latency=100000
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-pio_addr=738721792
-pio_latency=100000
-system=system
-pio=system.membus.master[3]
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470089728
-pio_latency=100000
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:67108863
-port=system.membus.master[1]
-
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=0
-pio_latency=30000
-platform=system.realview
-size=268435456
-system=system
-pio=system.iobus.default
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-eventq_index=0
-idreg=35979264
-pio_addr=469827584
-pio_latency=100000
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-pio_addr=471269376
-pio_latency=100000
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=true
-pio_addr=469893120
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-pio_addr=470876160
-pio_latency=100000
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-pio_addr=470941696
-pio_latency=100000
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470417408
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470482944
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470548480
-pio_latency=100000
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-pio_delay=10000
-platform=system.realview
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[4]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=402653184:436207615
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470745088
-pio_latency=100000
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-response_latency=1
-snoop_filter=Null
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 29 2014 15:46:15
-gem5 started Oct 29 2014 16:01:57
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
- 0: system.cpu0.isa: ISA system set to: 0x5b5eb00 0x5b5eb00
- 0: system.cpu1.isa: ISA system set to: 0x5b5eb00 0x5b5eb00
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 47438274662000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 47.367818 # Number of seconds simulated
-sim_ticks 47367817574000 # Number of ticks simulated
-final_tick 47367817574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 678056 # Simulator instruction rate (inst/s)
-host_op_rate 798173 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38043399524 # Simulator tick rate (ticks/s)
-host_mem_usage 751768 # Number of bytes of host memory used
-host_seconds 1245.10 # Real time elapsed on the host
-sim_insts 844246943 # Number of instructions simulated
-sim_ops 993804803 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 36928 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 40576 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 2794548 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 9993048 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 9568064 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 72256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 86016 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 2509048 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 8105888 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 7582272 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 437184 # Number of bytes read from this memory
-system.physmem.bytes_read::total 41225828 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 2794548 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 2509048 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5303596 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 61292480 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 61313296 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 577 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 634 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 84072 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 156163 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 149501 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 1129 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 1344 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 39292 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 126669 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 118473 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6831 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 684685 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 957695 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 960298 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 780 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 857 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 58997 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 210967 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 201995 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 1525 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 1816 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 52969 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 171126 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 160072 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 9230 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 870334 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 58997 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 52969 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 111966 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1293969 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1294408 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1293969 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 780 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 857 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 58997 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 211406 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 201995 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 1525 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 1816 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 52969 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 171127 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 160072 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 9230 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2164742 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 684685 # Number of read requests accepted
-system.physmem.writeReqs 1596629 # Number of write requests accepted
-system.physmem.readBursts 684685 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1596629 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 43802304 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 17536 # Total number of bytes read from write queue
-system.physmem.bytesWritten 99044160 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 41225828 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 102038480 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 274 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 49035 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 111704 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 42136 # Per bank write bursts
-system.physmem.perBankRdBursts::1 44080 # Per bank write bursts
-system.physmem.perBankRdBursts::2 34958 # Per bank write bursts
-system.physmem.perBankRdBursts::3 41288 # Per bank write bursts
-system.physmem.perBankRdBursts::4 39326 # Per bank write bursts
-system.physmem.perBankRdBursts::5 49165 # Per bank write bursts
-system.physmem.perBankRdBursts::6 40428 # Per bank write bursts
-system.physmem.perBankRdBursts::7 47118 # Per bank write bursts
-system.physmem.perBankRdBursts::8 36254 # Per bank write bursts
-system.physmem.perBankRdBursts::9 81044 # Per bank write bursts
-system.physmem.perBankRdBursts::10 36070 # Per bank write bursts
-system.physmem.perBankRdBursts::11 40557 # Per bank write bursts
-system.physmem.perBankRdBursts::12 34453 # Per bank write bursts
-system.physmem.perBankRdBursts::13 38158 # Per bank write bursts
-system.physmem.perBankRdBursts::14 37145 # Per bank write bursts
-system.physmem.perBankRdBursts::15 42231 # Per bank write bursts
-system.physmem.perBankWrBursts::0 97165 # Per bank write bursts
-system.physmem.perBankWrBursts::1 99476 # Per bank write bursts
-system.physmem.perBankWrBursts::2 95543 # Per bank write bursts
-system.physmem.perBankWrBursts::3 98326 # Per bank write bursts
-system.physmem.perBankWrBursts::4 92692 # Per bank write bursts
-system.physmem.perBankWrBursts::5 102230 # Per bank write bursts
-system.physmem.perBankWrBursts::6 96747 # Per bank write bursts
-system.physmem.perBankWrBursts::7 98806 # Per bank write bursts
-system.physmem.perBankWrBursts::8 93672 # Per bank write bursts
-system.physmem.perBankWrBursts::9 100275 # Per bank write bursts
-system.physmem.perBankWrBursts::10 92352 # Per bank write bursts
-system.physmem.perBankWrBursts::11 96579 # Per bank write bursts
-system.physmem.perBankWrBursts::12 94667 # Per bank write bursts
-system.physmem.perBankWrBursts::13 97213 # Per bank write bursts
-system.physmem.perBankWrBursts::14 92658 # Per bank write bursts
-system.physmem.perBankWrBursts::15 99164 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 352 # Number of times write queue was full causing retry
-system.physmem.totGap 47367814519500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 43195 # Read request sizes (log2)
-system.physmem.readPktSize::3 37 # Read request sizes (log2)
-system.physmem.readPktSize::4 5 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 641448 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 2 # Write request sizes (log2)
-system.physmem.writePktSize::3 2601 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1594026 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 510577 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 50448 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 25290 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 21897 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 18597 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 16379 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 14128 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 12156 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 9819 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 2868 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 632 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 368 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 296 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 233 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 165 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 161 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 129 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 89 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 50983 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 63815 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 77905 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 83850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 85536 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 82535 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 80562 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 80737 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 81986 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 81840 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 82529 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 87953 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 83182 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 82789 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 95240 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 86941 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 82400 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 79288 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 6110 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 5077 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 5187 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 6766 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 6791 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 6137 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 5946 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 6638 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 5635 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 5287 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 4863 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 4938 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 3930 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 3705 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 3619 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 2936 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 2542 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 1583 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 1351 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 1091 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 887 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 738 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 719 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 631 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 743 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 541 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 504 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 526 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 424 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 339 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 1324 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 813055 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 175.690629 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 106.318755 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 249.924527 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 526198 64.72% 64.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 156067 19.20% 83.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 35208 4.33% 88.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 17256 2.12% 90.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 12096 1.49% 91.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 8107 1.00% 92.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 6222 0.77% 93.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 5625 0.69% 94.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 46276 5.69% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 813055 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 73772 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 9.277314 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 118.735455 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 73768 99.99% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 73772 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 73772 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.977674 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 19.369218 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 19.656514 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31 71961 97.55% 97.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47 712 0.97% 98.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63 29 0.04% 98.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79 36 0.05% 98.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95 132 0.18% 98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111 174 0.24% 99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127 342 0.46% 99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143 135 0.18% 99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159 19 0.03% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175 12 0.02% 99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191 64 0.09% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207 33 0.04% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223 12 0.02% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239 4 0.01% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255 4 0.01% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271 7 0.01% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287 6 0.01% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303 10 0.01% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319 9 0.01% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335 6 0.01% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351 10 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367 15 0.02% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399 2 0.00% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::432-447 1 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495 6 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511 2 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527 7 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559 2 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575 3 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::576-591 2 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::592-607 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-655 2 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::688-703 2 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::720-735 2 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 73772 # Writes before turning the bus around for reads
-system.physmem.totQLat 20326500723 # Total ticks spent queuing
-system.physmem.totMemAccLat 33159206973 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 3422055000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 29699.26 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 48449.26 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 0.92 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.09 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 0.87 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.15 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.02 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing
-system.physmem.readRowHits 509481 # Number of row buffer hits during reads
-system.physmem.writeRowHits 909439 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 74.44 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes
-system.physmem.avgGap 20763390.98 # Average gap between requests
-system.physmem.pageHitRate 63.57 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 3169991160 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1729657875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2640253200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 5060782800 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1178038765890 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27387322041000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 31671796931685 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.635370 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 45560807372172 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1581715460000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 225294290828 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 2976704640 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1624194000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 2698113600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 4967438400 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1169320459140 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 27394969678500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 31670392028040 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.605711 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 45573545582628 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1581715460000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 212554603622 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
-system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 95467 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 95467 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8616 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72889 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 95458 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 0.225230 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 69.587670 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-2047 95457 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::20480-22527 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 95458 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 81514 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 17324.683490 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 15769.335506 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 10694.107977 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 81100 99.49% 99.49% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 359 0.44% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 15 0.02% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 81514 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 1873275212 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 1.115454 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 -216276296 -11.55% -11.55% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 2089551508 111.55% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 1873275212 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 72890 89.43% 89.43% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 8616 10.57% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 81506 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 95467 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 95467 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81506 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81506 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 176973 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.inst_hits 0 # ITB inst hits
-system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 81219280 # DTB read hits
-system.cpu0.dtb.read_misses 71070 # DTB read misses
-system.cpu0.dtb.write_hits 73504932 # DTB write hits
-system.cpu0.dtb.write_misses 24397 # DTB write misses
-system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 38298 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 4007 # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 10240 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 81290350 # DTB read accesses
-system.cpu0.dtb.write_accesses 73529329 # DTB write accesses
-system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 154724212 # DTB hits
-system.cpu0.dtb.misses 95467 # DTB misses
-system.cpu0.dtb.accesses 154819679 # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 56383 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 56383 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 751 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 50468 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 56383 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 56383 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 56383 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 51219 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 19351.129327 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 17618.924664 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 12629.312385 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767 47792 93.31% 93.31% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535 2988 5.83% 99.14% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303 157 0.31% 99.45% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071 221 0.43% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.03% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607 4 0.01% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.03% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 51219 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples -241360296 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 -241360296 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total -241360296 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 50468 98.53% 98.53% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 751 1.47% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 51219 # Table walker page sizes translated
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56383 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 56383 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51219 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51219 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 107602 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 434853798 # ITB inst hits
-system.cpu0.itb.inst_misses 56383 # ITB inst misses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 26912 # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 434910181 # ITB inst accesses
-system.cpu0.itb.hits 434853798 # DTB hits
-system.cpu0.itb.misses 56383 # DTB misses
-system.cpu0.itb.accesses 434910181 # DTB accesses
-system.cpu0.numCycles 94735635148 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 434594659 # Number of instructions committed
-system.cpu0.committedOps 509819268 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 468245604 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 368958 # Number of float alu accesses
-system.cpu0.num_func_calls 25685063 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 65742912 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 468245604 # number of integer instructions
-system.cpu0.num_fp_insts 368958 # number of float instructions
-system.cpu0.num_int_register_reads 681605000 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 371986080 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 629019 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 237888 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 113785122 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 113402508 # number of times the CC registers were written
-system.cpu0.num_mem_refs 154715442 # number of memory refs
-system.cpu0.num_load_insts 81215665 # Number of load instructions
-system.cpu0.num_store_insts 73499777 # Number of store instructions
-system.cpu0.num_idle_cycles 93677942540.842026 # Number of idle cycles
-system.cpu0.num_busy_cycles 1057692607.157978 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.011165 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.988835 # Percentage of idle cycles
-system.cpu0.Branches 96525602 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 354149041 69.42% 69.42% # Class of executed instruction
-system.cpu0.op_class::IntMult 1173113 0.23% 69.65% # Class of executed instruction
-system.cpu0.op_class::IntDiv 59997 0.01% 69.67% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 23937 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::MemRead 81215665 15.92% 85.59% # Class of executed instruction
-system.cpu0.op_class::MemWrite 73499777 14.41% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 510121531 # Class of executed instruction
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 13974 # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements 5284481 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 474.292500 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 149186915 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 5284993 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 28.228404 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 4077089500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 474.292500 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.926353 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.926353 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 314708854 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 314708854 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 75740068 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 75740068 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 69444390 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 69444390 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177454 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 177454 # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 143100 # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total 143100 # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1662300 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 1662300 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1634095 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 1634095 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 145184458 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 145184458 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 145361912 # number of overall hits
-system.cpu0.dcache.overall_hits::total 145361912 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 2820396 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 2820396 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1320543 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1320543 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 635767 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 635767 # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 746024 # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total 746024 # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 156072 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 156072 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 182947 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 182947 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 4140939 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 4140939 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 4776706 # number of overall misses
-system.cpu0.dcache.overall_misses::total 4776706 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39561901741 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 39561901741 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24338572363 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 24338572363 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 30943018074 # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 30943018074 # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2147538753 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 2147538753 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3961701456 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 3961701456 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1248500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1248500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 63900474104 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 63900474104 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 63900474104 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 63900474104 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 78560464 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 78560464 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 70764933 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 70764933 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 813221 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 813221 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 889124 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total 889124 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1818372 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 1818372 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1817042 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 1817042 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 149325397 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 149325397 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 150138618 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 150138618 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.035901 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.035901 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018661 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.018661 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781789 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781789 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839055 # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839055 # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085831 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085831 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100684 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100684 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027731 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.027731 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031815 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.031815 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14027.073411 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14027.073411 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18430.730664 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 18430.730664 # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41477.242118 # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41477.242118 # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13759.923324 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13759.923324 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21654.913478 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21654.913478 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15431.397107 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 15431.397107 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13377.518755 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 13377.518755 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 3634622 # number of writebacks
-system.cpu0.dcache.writebacks::total 3634622 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28612 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 28612 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21357 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 21357 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 38145 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 38145 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 49969 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 49969 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 49969 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 49969 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2791784 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 2791784 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1299186 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 1299186 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 630147 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 630147 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 746024 # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 746024 # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 117927 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 117927 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 182947 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 182947 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 4090970 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 4090970 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 4721117 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 4721117 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 34314944268 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 34314944268 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 21777665637 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 21777665637 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12432309289 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12432309289 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29820271426 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 29820271426 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1422971246 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1422971246 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3676791544 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3676791544 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1208000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1208000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 56092609905 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 56092609905 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 68524919194 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 68524919194 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4525228998 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4525228998 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4129291250 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4129291250 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8654520248 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8654520248 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035537 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035537 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018359 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018359 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.774878 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.774878 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.839055 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.839055 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064853 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064853 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100684 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100684 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027396 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.027396 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031445 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.031445 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12291.403729 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12291.403729 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16762.546423 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16762.546423 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19729.220783 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19729.220783 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39972.268219 # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39972.268219 # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12066.543251 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12066.543251 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20097.577681 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20097.577681 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13711.322719 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13711.322719 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14514.556448 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14514.556448 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 4499955 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.899412 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 430353331 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 4500467 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 95.624150 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 33435593250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.899412 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999804 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 122 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 874208063 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 874208063 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 430353331 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 430353331 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 430353331 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 430353331 # number of demand (read+write) hits
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-system.cpu0.icache.overall_hits::total 430353331 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 4500467 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 4500467 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 4500467 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 4500467 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 4500467 # number of overall misses
-system.cpu0.icache.overall_misses::total 4500467 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 47768563979 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 47768563979 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 47768563979 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 47768563979 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 47768563979 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 47768563979 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 434853798 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 434853798 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 434853798 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 434853798 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 434853798 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 434853798 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010349 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.010349 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010349 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.010349 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010349 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.010349 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10614.134928 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10614.134928 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10614.134928 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10614.134928 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4500467 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 4500467 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 4500467 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 4500467 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 4500467 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 4500467 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 43254050535 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 43254050535 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 43254050535 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 43254050535 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 43254050535 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 43254050535 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3811870500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total 3811870500 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010349 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.010349 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.010349 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9611.013820 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 9611.013820 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 9611.013820 # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu0.l2cache.prefetcher.pfIdentified 7625539 # number of prefetch candidates identified
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-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
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-system.cpu0.l2cache.ReadExReq_mshr_misses::total 225262 # number of ReadExReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 8450 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 6821 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 510939 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1105434 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total 1631644 # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 8450 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 6821 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 510939 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1105434 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 635942 # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total 2267586 # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 157112514 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 11720586224 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 21558629277 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 33614638265 # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 23030840367 # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 23030840367 # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24220184845 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 24220184845 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2529730528 # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2529730528 # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2304861456 # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2304861456 # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1005500 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1005500 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 8691962659 # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 8691962659 # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 157112514 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 11720586224 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 30250591936 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total 42306600924 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 157112514 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 11720586224 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 30250591936 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 23030840367 # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 65337441291 # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4307274002 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7775525002 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3933705500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3933705500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 8240979502 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11709230502 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.248646 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.168188 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
-system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.766299 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.766299 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.553879 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.553879 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.832725 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.832725 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.205169 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.205169 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.172480 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.239706 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 24493.654964 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23901.499212 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 36215.315810 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 42441.441675 # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 42441.441675 # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20873.741897 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20873.741897 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15129.520789 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15129.520789 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 335166.666667 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 335166.666667 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38586.013882 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38586.013882 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25928.818372 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28813.655266 # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 10272423 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 8656546 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 26078 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 26078 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 3634622 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 896357 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1072966 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 744713 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 432357 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330872 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 471310 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1218200 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1108311 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9087184 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15490281 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 297199 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 469779 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 25344443 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 288202388 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 584369767 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1031640 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1541304 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 875145099 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 3727007 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 17787477 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 3.192426 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.394206 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 14364709 80.76% 80.76% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 3422768 19.24% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 17787477 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 11622970748 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 201159488 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 6810939722 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 7629819592 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 168326514 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 277196500 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 92509 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 92509 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6608 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 71644 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 92500 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 0.081081 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 24.659848 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-511 92499 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::7168-7679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 92500 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 78261 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 18926.409693 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 17150.140934 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 13619.258696 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 77412 98.92% 98.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 724 0.93% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.04% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 50 0.06% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 78261 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 2425306712 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.143168 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 2078081352 85.68% 85.68% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 347225360 14.32% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 2425306712 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 71644 91.56% 91.56% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 6608 8.44% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 78252 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92509 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92509 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 78252 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 78252 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 170761 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.inst_hits 0 # ITB inst hits
-system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 78277454 # DTB read hits
-system.cpu1.dtb.read_misses 68245 # DTB read misses
-system.cpu1.dtb.write_hits 71517077 # DTB write hits
-system.cpu1.dtb.write_misses 24264 # DTB write misses
-system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 32777 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 3876 # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 8314 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 78345699 # DTB read accesses
-system.cpu1.dtb.write_accesses 71541341 # DTB write accesses
-system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 149794531 # DTB hits
-system.cpu1.dtb.misses 92509 # DTB misses
-system.cpu1.dtb.accesses 149887040 # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 60524 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 60524 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 415 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54985 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 60524 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 60524 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 60524 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 55400 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 21598.519856 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 19393.747052 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 17485.706336 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767 51757 93.42% 93.42% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535 2619 4.73% 98.15% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303 338 0.61% 98.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071 537 0.97% 99.73% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.77% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.80% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375 37 0.07% 99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911 28 0.05% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::491520-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 55400 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 2054805852 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 2054805852 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 2054805852 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 54985 99.25% 99.25% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 415 0.75% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 55400 # Table walker page sizes translated
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60524 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60524 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55400 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55400 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 115924 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 409921957 # ITB inst hits
-system.cpu1.itb.inst_misses 60524 # ITB inst misses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 23091 # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 409982481 # ITB inst accesses
-system.cpu1.itb.hits 409921957 # DTB hits
-system.cpu1.itb.misses 60524 # DTB misses
-system.cpu1.itb.accesses 409982481 # DTB accesses
-system.cpu1.numCycles 94735635148 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 409652284 # Number of instructions committed
-system.cpu1.committedOps 483985535 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 446181756 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 565626 # Number of float alu accesses
-system.cpu1.num_func_calls 25682090 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 61510479 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 446181756 # number of integer instructions
-system.cpu1.num_fp_insts 565626 # number of float instructions
-system.cpu1.num_int_register_reads 638057436 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 352717621 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 886208 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 535956 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 102771786 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 102542500 # number of times the CC registers were written
-system.cpu1.num_mem_refs 149782083 # number of memory refs
-system.cpu1.num_load_insts 78271508 # Number of load instructions
-system.cpu1.num_store_insts 71510575 # Number of store instructions
-system.cpu1.num_idle_cycles 93767065494.048019 # Number of idle cycles
-system.cpu1.num_busy_cycles 968569653.951980 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.010224 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.989776 # Percentage of idle cycles
-system.cpu1.Branches 91673037 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 333338821 68.84% 68.84% # Class of executed instruction
-system.cpu1.op_class::IntMult 986884 0.20% 69.04% # Class of executed instruction
-system.cpu1.op_class::IntDiv 58271 0.01% 69.05% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 89216 0.02% 69.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.07% # Class of executed instruction
-system.cpu1.op_class::MemRead 78271508 16.16% 85.23% # Class of executed instruction
-system.cpu1.op_class::MemWrite 71510575 14.77% 100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 484255317 # Class of executed instruction
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 5204 # number of quiesce instructions executed
-system.cpu1.dcache.tags.replacements 4752540 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 455.880794 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 144856637 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 4753051 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 30.476559 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8382286333500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.880794 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890392 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.890392 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 304369060 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 304369060 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 73044937 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 73044937 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 67886662 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 67886662 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 184038 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 184038 # number of SoftPFReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 188938 # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total 188938 # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1611925 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 1611925 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1592857 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 1592857 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 140931599 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 140931599 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 141115637 # number of overall hits
-system.cpu1.dcache.overall_hits::total 141115637 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 2767627 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 2767627 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 1154762 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 1154762 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 498783 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 498783 # number of SoftPFReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 496292 # number of WriteInvalidateReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::total 496292 # number of WriteInvalidateReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158321 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 158321 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 176268 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 176268 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 3922389 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 3922389 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 4421172 # number of overall misses
-system.cpu1.dcache.overall_misses::total 4421172 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 37645623046 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 37645623046 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19534966036 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 19534966036 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11881656902 # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11881656902 # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2306877268 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 2306877268 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3770896575 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 3770896575 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1887000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1887000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 57180589082 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 57180589082 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 57180589082 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 57180589082 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 75812564 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 75812564 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 69041424 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 69041424 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 682821 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 682821 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 685230 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::total 685230 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1770246 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 1770246 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1769125 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 1769125 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 144853988 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 144853988 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 145536809 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 145536809 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036506 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.036506 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016726 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.016726 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.730474 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.730474 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.724271 # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.724271 # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089434 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089434 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099636 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099636 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027078 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.027078 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030378 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.030378 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13602.130289 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13602.130289 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16916.876409 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 16916.876409 # average WriteReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 23940.859216 # average WriteInvalidateReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 23940.859216 # average WriteInvalidateReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14570.886162 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14570.886162 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21392.973058 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21392.973058 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14578.000571 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14578.000571 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12933.355473 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 12933.355473 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 3063492 # number of writebacks
-system.cpu1.dcache.writebacks::total 3063492 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11545 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 11545 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 352 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 352 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46682 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46682 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 11897 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 11897 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 11897 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 11897 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2756082 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 2756082 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1154410 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 1154410 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 498783 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 498783 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 496292 # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 496292 # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 111639 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 111639 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 176268 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 176268 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 3910492 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 3910492 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 4409275 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 4409275 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 32859790378 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 32859790378 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 17743172214 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 17743172214 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9770846491 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 9770846491 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11134079098 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11134079098 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1396307998 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1396307998 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3498646925 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3498646925 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1819500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1819500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 50602962592 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 50602962592 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 60373809083 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 60373809083 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1936116751 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1936116751 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2164016499 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2164016499 # number of WriteReq MSHR uncacheable cycles
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-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4100133250 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036354 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036354 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016721 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016721 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.730474 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.730474 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.724271 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.724271 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063064 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063064 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099636 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099636 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026996 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.026996 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030297 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.030297 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11922.646125 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11922.646125 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15369.905158 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15369.905158 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19589.373517 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19589.373517 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22434.532690 # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22434.532690 # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12507.349564 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12507.349564 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19848.451931 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19848.451931 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12940.305873 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12940.305873 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13692.457169 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13692.457169 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
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-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements 5523110 # number of replacements
-system.cpu1.icache.tags.tagsinuse 496.341944 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 404398330 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 5523622 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 73.212528 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 8382258847250 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.341944 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969418 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.969418 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 825367541 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 825367541 # Number of data accesses
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-system.cpu1.icache.ReadReq_hits::total 404398330 # number of ReadReq hits
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-system.cpu1.icache.overall_hits::total 404398330 # number of overall hits
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-system.cpu1.icache.ReadReq_misses::total 5523627 # number of ReadReq misses
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-system.cpu1.icache.demand_misses::total 5523627 # number of demand (read+write) misses
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-system.cpu1.icache.overall_misses::total 5523627 # number of overall misses
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-system.cpu1.icache.ReadReq_miss_latency::total 54612807078 # number of ReadReq miss cycles
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-system.cpu1.icache.demand_miss_latency::total 54612807078 # number of demand (read+write) miss cycles
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-system.cpu1.icache.overall_miss_latency::total 54612807078 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 409921957 # number of ReadReq accesses(hits+misses)
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-system.cpu1.icache.demand_accesses::total 409921957 # number of demand (read+write) accesses
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-system.cpu1.icache.overall_accesses::total 409921957 # number of overall (read+write) accesses
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-system.cpu1.icache.ReadReq_miss_rate::total 0.013475 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013475 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.013475 # miss rate for demand accesses
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-system.cpu1.icache.overall_miss_rate::total 0.013475 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9887.127983 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 9887.127983 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 9887.127983 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 9887.127983 # average overall miss latency
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-system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu1.icache.ReadReq_mshr_misses::total 5523627 # number of ReadReq MSHR misses
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-system.cpu1.icache.overall_mshr_misses::total 5523627 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49075741422 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 49075741422 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49075741422 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 49075741422 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49075741422 # number of overall MSHR miss cycles
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-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9805750 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9805750 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 9805750 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013475 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.013475 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.013475 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8884.695042 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 8884.695042 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 8884.695042 # average overall mshr miss latency
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-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.cpu1.l2cache.prefetcher.pfIdentified 5870524 # number of prefetch candidates identified
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-system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage 773012 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements 1638473 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 13410.207774 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 10772955 # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs 1654198 # Sample count of references to valid blocks.
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-system.cpu1.l2cache.tags.warmup_cycle 10040948806000 # Cycle when the warmup percentage was hit.
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-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 70.626422 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 88.861590 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3789.090493 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3453.027216 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 821.871120 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks 0.316573 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004311 # Average percentage of cache occupancy
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-system.cpu1.l2cache.tags.occ_percent::total 0.818494 # Average percentage of cache occupancy
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-system.cpu1.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14027 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 271 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 744 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 601 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 43 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2440 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6290 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5121 # Occupied blocks per task id
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-system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id
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-system.cpu1.l2cache.ReadReq_hits::total 8016549 # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks 3063492 # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total 3063492 # number of Writeback hits
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-system.cpu1.l2cache.WriteInvalidateReq_hits::total 265137 # number of WriteInvalidateReq hits
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-system.cpu1.l2cache.UpgradeReq_hits::total 50742 # number of UpgradeReq hits
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-system.cpu1.l2cache.SCUpgradeReq_hits::total 28295 # number of SCUpgradeReq hits
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-system.cpu1.l2cache.demand_hits::cpu1.itb.walker 146711 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst 5082589 # number of demand (read+write) hits
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-system.cpu1.l2cache.demand_hits::total 8793955 # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 196843 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker 146711 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst 5082589 # number of overall hits
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-system.cpu1.l2cache.Writeback_accesses::total 3063492 # number of Writeback accesses(hits+misses)
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-system.cpu1.l2cache.SCUpgradeReq_accesses::total 176263 # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 30693.930732 # average ReadReq miss latency
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-system.cpu1.l2cache.demand_mshr_hits::total 2857 # number of demand (read+write) MSHR hits
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-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 775775 # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total 1233544 # number of ReadReq MSHR misses
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-system.cpu1.l2cache.HardPFReq_mshr_misses::total 524912 # number of HardPFReq MSHR misses
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-system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 229595 # number of WriteInvalidateReq MSHR misses
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-system.cpu1.l2cache.UpgradeReq_mshr_misses::total 120541 # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 147968 # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 147968 # number of SCUpgradeReq MSHR misses
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-system.cpu1.l2cache.demand_mshr_misses::cpu1.data 980792 # number of demand (read+write) MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7601 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 441038 # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data 980792 # number of overall MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::total 1963473 # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 224849501 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 10375497328 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 18713747169 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 29541935250 # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 17727784992 # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 17727784992 # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7402905507 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7402905507 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2380480811 # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2380480811 # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2176947075 # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2176947075 # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1480998 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1480998 # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6436785468 # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6436785468 # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 224849501 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 10375497328 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 25150532637 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total 35978720718 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 224849501 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 10375497328 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 25150532637 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 17727784992 # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total 53706505710 # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8938250 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1841380999 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1850319249 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2067303001 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2067303001 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8938250 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3908684000 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3917622250 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.230439 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.133350 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.464080 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.464080 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.703753 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.703753 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.839473 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.839473 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.208148 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.208148 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140548 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191832 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24122.647893 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23948.829754 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33772.870485 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32243.321967 # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32243.321967 # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19748.308136 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19748.308136 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14712.282892 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14712.282892 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296199.600000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296199.600000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31396.349903 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31396.349903 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25010.215568 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27352.810917 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 11346555 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 9442060 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 12895 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 12895 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 3063492 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 747367 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1164315 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 494732 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 387368 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 328581 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 412328 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1123330 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 992188 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11047474 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13661084 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 335346 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 476365 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 25520269 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353512568 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 512414548 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1234496 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1647784 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 868809396 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 4168573 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 18149089 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 3.215812 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.411385 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 14232289 78.42% 78.42% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 3916800 21.58% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 18149089 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 10693279996 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 176128990 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 8292291078 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 7012668647 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 181227501 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 270567252 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40336 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40336 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136623 # Transaction distribution
-system.iobus.trans_dist::WriteResp 29895 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122628 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
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-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155735 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7496677 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 36212000 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 607542087 # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 92736000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 148516061 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 115606 # number of replacements
-system.iocache.tags.tagsinuse 11.280528 # Cycle average of tags in use
-system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115622 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 9179145722000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 7.421794 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 3.858734 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.463862 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.241171 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.705033 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1040802 # Number of tag accesses
-system.iocache.tags.data_accesses 1040802 # Number of data accesses
-system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses
-system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses
-system.iocache.demand_misses::total 8917 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 8877 # number of overall misses
-system.iocache.overall_misses::total 8917 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 1629440754 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 1634636254 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19888935272 # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total 19888935272 # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide 1629440754 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 1635005254 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide 1629440754 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 1635005254 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
-system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 183557.593106 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 183378.534216 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186351.615996 # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 186351.615996 # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 183557.593106 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183358.220702 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 183557.593106 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183358.220702 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 110662 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 16220 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 6.822565 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks::writebacks 106699 # number of writebacks
-system.iocache.writebacks::total 106699 # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide 8877 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 8877 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 8917 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 8877 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 8917 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 1166654804 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 1169925304 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14339007344 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14339007344 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 1166654804 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 1170138304 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 1166654804 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 1170138304 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131424.445646 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 131245.827238 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134350.942058 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134350.942058 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 131424.445646 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 131225.558372 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 131424.445646 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 131225.558372 # average overall mshr miss latency
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 1063912 # number of replacements
-system.l2c.tags.tagsinuse 64178.177670 # Cycle average of tags in use
-system.l2c.tags.total_refs 3766892 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 1123413 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 3.353079 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 11093199000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 24092.358885 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 75.949373 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 107.097830 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 4212.805606 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 7550.293396 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7226.795277 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 149.211397 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 222.509709 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 4405.039325 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 7865.744621 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8270.372252 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.367620 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001159 # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu0.inst 0.064282 # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.110272 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002277 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker 0.003395 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.067216 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.120022 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.126196 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.979281 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022 9644 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023 191 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 49666 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3 226 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4 9286 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 191 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 1430 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 4883 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 43236 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022 0.147156 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023 0.002914 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.757843 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 50574940 # Number of tag accesses
-system.l2c.tags.data_accesses 50574940 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 5180 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 4259 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 469863 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 537542 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 313027 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 4490 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 3587 # number of ReadReq hits
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-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17872.145516 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17839.981482 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74622.680148 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69151.437191 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 72405.364770 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 622157 # Transaction distribution
-system.membus.trans_dist::ReadResp 622157 # Transaction distribution
-system.membus.trans_dist::WriteReq 38973 # Transaction distribution
-system.membus.trans_dist::WriteResp 38973 # Transaction distribution
-system.membus.trans_dist::Writeback 957695 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 636331 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 636331 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 382471 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 288753 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 111723 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution
-system.membus.trans_dist::ReadExReq 123220 # Transaction distribution
-system.membus.trans_dist::ReadExResp 104410 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122628 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28184 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4073596 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4224500 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4560403 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155735 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56368 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129167796 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 129380103 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096512 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 14096512 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 143476615 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 581158 # Total snoops (count)
-system.membus.snoop_fanout::samples 2928688 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 2928688 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2928688 # Request fanout histogram
-system.membus.reqLayer0.occupancy 100579500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 24544499 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 9168550783 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 4323654540 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 151928439 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.realview.ethernet.txBytes 966 # Bytes Transmitted
-system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets 3 # Total Packets
-system.realview.ethernet.totBytes 966 # Total Bytes
-system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 3783137 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 3775909 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38973 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38973 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 2047649 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 890925 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp 784014 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 429633 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 300246 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 729879 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 258637 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 258637 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 6917142 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4903000 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 11820142 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 229102843 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 151634764 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 380737607 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1518303 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 7628101 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.015184 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.122286 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 7512273 98.48% 98.48% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 115828 1.52% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 7628101 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 6924291534 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2530500 # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 3796276244 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 3095093071 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[ 0.000000] Initializing cgroup subsys cpu\r
-[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[ 0.000000] Memory limited to 256MB\r
-[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[ 0.000000] On node 0 totalpages: 65536\r
-[ 0.000000] DMA zone: 896 pages used for memmap\r
-[ 0.000000] DMA zone: 0 pages reserved\r
-[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
-[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
-[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[ 0.000000] Virtual kernel memory layout:\r
-[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
-[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
-[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
-[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
-[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
-[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
-[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[ 0.000000] Preemptible hierarchical RCU implementation.\r
-[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000024] Console: colour dummy device 80x25\r
-[ 0.000026] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000028] pid_max: default: 32768 minimum: 301\r
-[ 0.000041] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000043] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000177] hw perfevents: no hardware support available\r
-[ 0.060047] CPU1: Booted secondary processor\r
-[ 1.080090] CPU2: failed to come online\r
-[ 2.100176] CPU3: failed to come online\r
-[ 2.100179] Brought up 2 CPUs\r
-[ 2.100180] SMP: Total of 2 processors activated.\r
-[ 2.100246] devtmpfs: initialized\r
-[ 2.101156] atomic64_test: passed\r
-[ 2.101216] regulator-dummy: no parameters\r
-[ 2.101757] NET: Registered protocol family 16\r
-[ 2.101938] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 2.101944] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 2.102749] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 2.102752] Serial: AMBA PL011 UART driver\r
-[ 2.102985] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 2.103030] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 2.103571] console [ttyAMA0] enabled\r
-[ 2.103651] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 2.103687] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 2.103724] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 2.103758] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 2.130471] 3V3: 3300 mV \r
-[ 2.130527] vgaarb: loaded\r
-[ 2.130588] SCSI subsystem initialized\r
-[ 2.130625] libata version 3.00 loaded.\r
-[ 2.130697] usbcore: registered new interface driver usbfs\r
-[ 2.130719] usbcore: registered new interface driver hub\r
-[ 2.130747] usbcore: registered new device driver usb\r
-[ 2.130780] pps_core: LinuxPPS API ver. 1 registered\r
-[ 2.130789] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 2.130808] PTP clock support registered\r
-[ 2.130983] Switched to clocksource arch_sys_counter\r
-[ 2.132484] NET: Registered protocol family 2\r
-[ 2.132575] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 2.132593] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 2.132613] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 2.132639] TCP: reno registered\r
-[ 2.132646] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.132659] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.132700] NET: Registered protocol family 1\r
-[ 2.132760] RPC: Registered named UNIX socket transport module.\r
-[ 2.132769] RPC: Registered udp transport module.\r
-[ 2.132777] RPC: Registered tcp transport module.\r
-[ 2.132785] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 2.132797] PCI: CLS 0 bytes, default 64\r
-[ 2.133009] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 2.133115] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 2.136052] fuse init (API version 7.23)\r
-[ 2.136196] msgmni has been set to 469\r
-[ 2.136706] io scheduler noop registered\r
-[ 2.136791] io scheduler cfq registered (default)\r
-[ 2.137366] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 2.137378] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 2.137389] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 2.137401] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 2.137411] pci_bus 0000:00: scanning bus\r
-[ 2.137421] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 2.137433] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 2.137448] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.137496] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 2.137508] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 2.137518] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 2.137529] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 2.137540] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 2.137551] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 2.137562] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.137612] pci_bus 0000:00: fixups for bus\r
-[ 2.137620] pci_bus 0000:00: bus scan returning with max=00\r
-[ 2.137631] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 2.137651] pci 0000:00:00.0: fixup irq: got 33\r
-[ 2.137660] pci 0000:00:00.0: assigning IRQ 33\r
-[ 2.137670] pci 0000:00:01.0: fixup irq: got 34\r
-[ 2.137679] pci 0000:00:01.0: assigning IRQ 34\r
-[ 2.137690] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 2.137702] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 2.137715] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 2.137727] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 2.137739] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 2.137750] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 2.137761] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 2.137773] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 2.138657] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 2.139057] ata_piix 0000:00:01.0: version 2.13\r
-[ 2.139067] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 2.139093] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 2.139456] scsi0 : ata_piix\r
-[ 2.139567] scsi1 : ata_piix\r
-[ 2.139611] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 2.139623] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 2.139769] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 2.139781] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 2.139797] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 2.139808] e1000 0000:00:00.0: enabling bus mastering\r
-[ 2.291018] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 2.291027] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 2.291054] ata1.00: configured for UDMA/33\r
-[ 2.291104] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 2.291261] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 2.291294] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 2.291338] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 2.291347] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 2.291369] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 2.291545] sda: sda1\r
-[ 2.291741] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 2.411341] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 2.411354] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 2.411387] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 2.411399] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 2.411432] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 2.411446] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 2.411610] usbcore: registered new interface driver usb-storage\r
-[ 2.411699] mousedev: PS/2 mouse device common for all mice\r
-[ 2.412097] usbcore: registered new interface driver usbhid\r
-[ 2.412108] usbhid: USB HID core driver\r
-[ 2.412141] TCP: cubic registered\r
-[ 2.412149] NET: Registered protocol family 17\r
-\0[ 2.412566] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 2.412601] devtmpfs: mounted\r
-[ 2.412656] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[ 2.452574] udevd[608]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[ 2.544108] random: dd urandom read with 18 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 2.681213] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-done.\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
-Starting auto-serial-console:
\ No newline at end of file
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
-cache_line_size=64
-clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_generic_timer=false
-have_large_asid_64=false
-have_lpae=false
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=timing
-mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-num_work_ids=16
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
-reset_addr_64=0
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-delay=50000
-eventq_index=0
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu.dstage2_mmu
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-istage2_mmu=system.cpu.istage2_mmu
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.dtb
-
-[system.cpu.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu.toL2Bus.slave[3]
-
-[system.cpu.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=ArmISA
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu.itb
-
-[system.cpu.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu.istage2_mmu.stage2_tlb.walker
-
-[system.cpu.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.cpu.toL2Bus.slave[2]
-
-[system.cpu.l2cache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_top_level=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=4194304
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-response_latency=1
-snoop_filter=Null
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-response_latency=2
-use_default_range=true
-width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=BaseCache
-children=tags
-addr_ranges=2147483648:2415919103
-assoc=8
-clk_domain=system.clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=false
-hit_latency=50
-is_top_level=true
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.master[27]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-hit_latency=50
-sequential_access=false
-size=1024
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=0
-pio_latency=100000
-pio_size=8
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-page_policy=open_adaptive
-range=2147483648:2415919103
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470024192
-pio_latency=100000
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-disks=
-eventq_index=0
-io_shift=2
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-platform=system.realview
-system=system
-config=system.iobus.master[9]
-dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-pio_addr=470286336
-pio_latency=100000
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-platform=system.realview
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-config=system.iobus.master[26]
-dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_num=29
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-int_latency=10000
-it_lines=128
-msix_addr=0
-platform=system.realview
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-pio_addr=721420288
-pio_latency=10000
-pixel_clock=7299
-system=system
-vnc=system.vncserver
-dma=system.membus.slave[0]
-pio=system.iobus.master[5]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-disks=system.cf0
-eventq_index=0
-io_shift=0
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-platform=system.realview
-system=system
-config=system.iobus.master[24]
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-pio_addr=470155264
-pio_latency=100000
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[6]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-pio_addr=470220800
-pio_latency=100000
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-pio_addr=738721792
-pio_latency=100000
-system=system
-pio=system.membus.master[3]
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470089728
-pio_latency=100000
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:67108863
-port=system.membus.master[1]
-
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=0
-pio_latency=30000
-platform=system.realview
-size=268435456
-system=system
-pio=system.iobus.default
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-eventq_index=0
-idreg=35979264
-pio_addr=469827584
-pio_latency=100000
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-pio_addr=471269376
-pio_latency=100000
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=true
-pio_addr=469893120
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-pio_addr=470876160
-pio_latency=100000
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-pio_addr=470941696
-pio_latency=100000
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470417408
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470482944
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470548480
-pio_latency=100000
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-pio_delay=10000
-platform=system.realview
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[4]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=402653184:436207615
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470745088
-pio_latency=100000
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 29 2014 15:46:15
-gem5 started Oct 29 2014 16:01:52
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
- 0: system.cpu.isa: ISA system set to: 0x500ab00 0x500ab00
-info: Using bootloader at address 0x10
-info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 51781056074000 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 51.824462 # Number of seconds simulated
-sim_ticks 51824462100500 # Number of ticks simulated
-final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 723017 # Simulator instruction rate (inst/s)
-host_op_rate 849578 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 41937024652 # Simulator tick rate (ticks/s)
-host_mem_usage 712044 # Number of bytes of host memory used
-host_seconds 1235.77 # Real time elapsed on the host
-sim_insts 893481288 # Number of instructions simulated
-sim_ops 1049881338 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 266048 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 259456 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 5261620 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 50351624 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 398272 # Number of bytes read from this memory
-system.physmem.bytes_read::total 56537020 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 5261620 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5261620 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 77705792 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 77726372 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 4157 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 4054 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 122620 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 786757 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6223 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 923811 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1214153 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1216726 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 5134 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 5006 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 101528 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 971580 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 7685 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1090933 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 101528 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 101528 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1499404 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1499801 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1499404 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 5134 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 5006 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 101528 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 971977 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 7685 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2590734 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 923811 # Number of read requests accepted
-system.physmem.writeReqs 1833124 # Number of write requests accepted
-system.physmem.readBursts 923811 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1833124 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 59092736 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 31168 # Total number of bytes read from write queue
-system.physmem.bytesWritten 114062016 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 56537020 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 117175844 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 487 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 50880 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 36215 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 57129 # Per bank write bursts
-system.physmem.perBankRdBursts::1 60965 # Per bank write bursts
-system.physmem.perBankRdBursts::2 52485 # Per bank write bursts
-system.physmem.perBankRdBursts::3 50413 # Per bank write bursts
-system.physmem.perBankRdBursts::4 54002 # Per bank write bursts
-system.physmem.perBankRdBursts::5 59718 # Per bank write bursts
-system.physmem.perBankRdBursts::6 51713 # Per bank write bursts
-system.physmem.perBankRdBursts::7 51669 # Per bank write bursts
-system.physmem.perBankRdBursts::8 50247 # Per bank write bursts
-system.physmem.perBankRdBursts::9 101235 # Per bank write bursts
-system.physmem.perBankRdBursts::10 59848 # Per bank write bursts
-system.physmem.perBankRdBursts::11 58323 # Per bank write bursts
-system.physmem.perBankRdBursts::12 55369 # Per bank write bursts
-system.physmem.perBankRdBursts::13 55988 # Per bank write bursts
-system.physmem.perBankRdBursts::14 51743 # Per bank write bursts
-system.physmem.perBankRdBursts::15 52477 # Per bank write bursts
-system.physmem.perBankWrBursts::0 110630 # Per bank write bursts
-system.physmem.perBankWrBursts::1 112240 # Per bank write bursts
-system.physmem.perBankWrBursts::2 108805 # Per bank write bursts
-system.physmem.perBankWrBursts::3 108103 # Per bank write bursts
-system.physmem.perBankWrBursts::4 111102 # Per bank write bursts
-system.physmem.perBankWrBursts::5 113339 # Per bank write bursts
-system.physmem.perBankWrBursts::6 105567 # Per bank write bursts
-system.physmem.perBankWrBursts::7 107723 # Per bank write bursts
-system.physmem.perBankWrBursts::8 108849 # Per bank write bursts
-system.physmem.perBankWrBursts::9 115780 # Per bank write bursts
-system.physmem.perBankWrBursts::10 115663 # Per bank write bursts
-system.physmem.perBankWrBursts::11 113049 # Per bank write bursts
-system.physmem.perBankWrBursts::12 112494 # Per bank write bursts
-system.physmem.perBankWrBursts::13 116984 # Per bank write bursts
-system.physmem.perBankWrBursts::14 111502 # Per bank write bursts
-system.physmem.perBankWrBursts::15 110389 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 145 # Number of times write queue was full causing retry
-system.physmem.totGap 51824459475500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 43101 # Read request sizes (log2)
-system.physmem.readPktSize::3 13 # Read request sizes (log2)
-system.physmem.readPktSize::4 2 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 880695 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 1 # Write request sizes (log2)
-system.physmem.writePktSize::3 2572 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1830551 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 889155 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 28186 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 284 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 462 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 528 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 455 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 746 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 480 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1765 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 111 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 102 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 57524 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 60978 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 91825 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 117209 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 106855 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 97040 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 98714 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 93369 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 94185 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 92986 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 93402 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 98737 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 96397 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 94916 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 105152 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 97025 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 94048 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 92817 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 5441 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 5084 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 5738 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 7709 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 7730 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 6924 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 6738 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 7452 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 5737 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 5138 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 4676 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 5004 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 4547 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 3838 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 3903 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 3022 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 2209 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 1452 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 1128 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 847 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 643 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 513 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 524 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 509 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 510 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 478 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 419 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 286 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 162 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 329 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 603787 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 286.780656 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 164.845955 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 326.273004 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 251324 41.62% 41.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 149673 24.79% 66.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 51779 8.58% 74.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 28017 4.64% 79.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 19714 3.27% 82.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 13055 2.16% 85.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 9885 1.64% 86.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 8959 1.48% 88.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 71381 11.82% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 603787 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 89136 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 10.358104 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 107.922360 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 89134 100.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 89136 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 89136 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 19.994379 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.728374 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 17.051434 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31 87330 97.97% 97.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47 694 0.78% 98.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63 23 0.03% 98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79 47 0.05% 98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95 149 0.17% 99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111 187 0.21% 99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127 322 0.36% 99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143 118 0.13% 99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159 42 0.05% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191 62 0.07% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207 32 0.04% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223 11 0.01% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239 9 0.01% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255 3 0.00% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271 1 0.00% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287 2 0.00% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303 6 0.01% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335 10 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367 26 0.03% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383 5 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415 2 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431 2 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::432-447 2 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479 2 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495 5 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511 2 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543 3 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 89136 # Writes before turning the bus around for reads
-system.physmem.totQLat 12043609520 # Total ticks spent queuing
-system.physmem.totMemAccLat 29355934520 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 4616620000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 13043.75 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31793.75 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.20 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.26 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.03 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing
-system.physmem.readRowHits 694872 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1406883 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes
-system.physmem.avgGap 18797853.22 # Average gap between requests
-system.physmem.pageHitRate 77.68 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 2251693080 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1228602375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 3417133200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 5686258320 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1307306510865 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 29947912845000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 34652724495480 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.655841 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 49820369752426 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1730532440000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 273552725074 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 2312936640 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1262019000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 3784755000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 5862520800 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1309001038785 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 29946426417000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 34653571139865 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.672178 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 49817859630672 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1730532440000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 276069619328 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
-system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 211321 # Table walker walks requested
-system.cpu.dtb.walker.walksLong 211321 # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15784 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3 163511 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples 211307 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean 0.170368 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 58.877055 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-2047 211305 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 211307 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 179309 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 23338.389317 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 19372.996771 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 15325.519359 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535 177365 98.92% 98.92% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071 1663 0.93% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607 114 0.06% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143 88 0.05% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679 58 0.03% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 179309 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples -200578036 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean -2.729096 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0 -747974796 372.91% 372.91% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::1 547396760 -272.91% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total -200578036 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 163512 91.20% 91.20% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M 15784 8.80% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 179296 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 211321 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 211321 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 179296 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 179296 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 390617 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 167775531 # DTB read hits
-system.cpu.dtb.read_misses 155743 # DTB read misses
-system.cpu.dtb.write_hits 152648275 # DTB write hits
-system.cpu.dtb.write_misses 55578 # DTB write misses
-system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 75520 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 8371 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 19881 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 167931274 # DTB read accesses
-system.cpu.dtb.write_accesses 152703853 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 320423806 # DTB hits
-system.cpu.dtb.misses 211321 # DTB misses
-system.cpu.dtb.accesses 320635127 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 122916 # Table walker walks requested
-system.cpu.itb.walker.walksLong 122916 # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3 110644 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples 122916 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 122916 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 122916 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 111766 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 26583.507059 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 22687.613632 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 18325.329143 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-32767 56090 50.19% 50.19% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-65535 53429 47.80% 97.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-98303 753 0.67% 98.66% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::98304-131071 1184 1.06% 99.72% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-163839 19 0.02% 99.74% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::163840-196607 105 0.09% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::229376-262143 54 0.05% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-294911 30 0.03% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::294912-327679 11 0.01% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-360447 20 0.02% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::360448-393215 11 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-425983 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::491520-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 111766 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples -853761296 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 -853761296 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total -853761296 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 110644 99.00% 99.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M 1122 1.00% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 111766 # Table walker page sizes translated
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122916 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 122916 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111766 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 111766 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 234682 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 894030670 # ITB inst hits
-system.cpu.itb.inst_misses 122916 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 53866 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 894153586 # ITB inst accesses
-system.cpu.itb.hits 894030670 # DTB hits
-system.cpu.itb.misses 122916 # DTB misses
-system.cpu.itb.accesses 894153586 # DTB accesses
-system.cpu.numCycles 103648924201 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 893481288 # Number of instructions committed
-system.cpu.committedOps 1049881338 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 963989017 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 895873 # Number of float alu accesses
-system.cpu.num_func_calls 52999943 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 136446519 # number of instructions that are conditional controls
-system.cpu.num_int_insts 963989017 # number of integer instructions
-system.cpu.num_fp_insts 895873 # number of float instructions
-system.cpu.num_int_register_reads 1405913792 # number of times the integer registers were read
-system.cpu.num_int_register_writes 764688301 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 1443674 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 760516 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 234750393 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 234155899 # number of times the CC registers were written
-system.cpu.num_mem_refs 320407593 # number of memory refs
-system.cpu.num_load_insts 167768846 # Number of load instructions
-system.cpu.num_store_insts 152638747 # Number of store instructions
-system.cpu.num_idle_cycles 100474792122.552063 # Number of idle cycles
-system.cpu.num_busy_cycles 3174132078.447939 # Number of busy cycles
-system.cpu.not_idle_fraction 0.030624 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.969376 # Percentage of idle cycles
-system.cpu.Branches 199584978 # Number of branches fetched
-system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 727639004 69.27% 69.27% # Class of executed instruction
-system.cpu.op_class::IntMult 2217476 0.21% 69.48% # Class of executed instruction
-system.cpu.op_class::IntDiv 99175 0.01% 69.49% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 8 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 110553 0.01% 69.50% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction
-system.cpu.op_class::MemRead 167768846 15.97% 85.47% # Class of executed instruction
-system.cpu.op_class::MemWrite 152638747 14.53% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 1050473844 # Class of executed instruction
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 16327 # number of quiesce instructions executed
-system.cpu.dcache.tags.replacements 10213653 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.965664 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 310015199 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 10214165 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 30.351497 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 3500615250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.965664 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999933 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1291569953 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1291569953 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 156758765 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 156758765 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 144836105 # number of WriteReq hits
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-system.cpu.dcache.SoftPFReq_hits::total 393576 # number of SoftPFReq hits
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-system.cpu.dcache.WriteInvalidateReq_hits::total 334400 # number of WriteInvalidateReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 3672090 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 3672090 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 3974747 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 3974747 # number of StoreCondReq hits
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-system.cpu.dcache.demand_hits::total 301594870 # number of demand (read+write) hits
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-system.cpu.dcache.overall_hits::total 301988446 # number of overall hits
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-system.cpu.dcache.ReadReq_misses::total 5315823 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2219045 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2219045 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 1297249 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 1297249 # number of SoftPFReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1232796 # number of WriteInvalidateReq misses
-system.cpu.dcache.WriteInvalidateReq_misses::total 1232796 # number of WriteInvalidateReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 304342 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 304342 # number of LoadLockedReq misses
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-system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 7534868 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 7534868 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 8832117 # number of overall misses
-system.cpu.dcache.overall_misses::total 8832117 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 84066704475 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 84066704475 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 66382286210 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 66382286210 # number of WriteReq miss cycles
-system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 32849513005 # number of WriteInvalidateReq miss cycles
-system.cpu.dcache.WriteInvalidateReq_miss_latency::total 32849513005 # number of WriteInvalidateReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4463810234 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 4463810234 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 150448990685 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 150448990685 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 150448990685 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 150448990685 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 162074588 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 162074588 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 147055150 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 147055150 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 1690825 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 1690825 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1567196 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.WriteInvalidateReq_accesses::total 1567196 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3976432 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 3976432 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 3974749 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 3974749 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 309129738 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 309129738 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 310820563 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 310820563 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032799 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.032799 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015090 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.015090 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767228 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.767228 # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786625 # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786625 # miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076536 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076536 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.024374 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.024374 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.028415 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.028415 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15814.428824 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15814.428824 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29914.799479 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29914.799479 # average WriteReq miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 26646.349441 # average WriteInvalidateReq miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 26646.349441 # average WriteInvalidateReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14667.085825 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14667.085825 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19967.037337 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19967.037337 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17034.306802 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 17034.306802 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 7878976 # number of writebacks
-system.cpu.dcache.writebacks::total 7878976 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 16016 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 16016 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21118 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 21118 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70685 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 70685 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 37134 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 37134 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 37134 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 37134 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5299807 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 5299807 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2197927 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 2197927 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1295520 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 1295520 # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1232796 # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1232796 # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233657 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 233657 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 7497734 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 7497734 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 8793254 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 8793254 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75489557525 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 75489557525 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62224351540 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 62224351540 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20153084274 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20153084274 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 31000318995 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 31000318995 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2998156750 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2998156750 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137713909065 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 137713909065 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157866993339 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 157866993339 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5751194250 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5751194250 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5618584250 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5618584250 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11369778500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 11369778500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032700 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032700 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014946 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014946 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766206 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766206 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786625 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786625 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058760 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058760 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024254 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.024254 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028290 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.028290 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14243.831431 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14243.831431 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28310.472341 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28310.472341 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15555.980822 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15555.980822 # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 25146.349433 # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25146.349433 # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12831.444168 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12831.444168 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18367.403947 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 13753173 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.880059 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 880276980 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 13753685 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 64.002991 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 35133104250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.880059 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.999766 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.999766 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 907784360 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 907784360 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 880276980 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 880276980 # number of ReadReq hits
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-system.cpu.icache.demand_hits::total 880276980 # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total 880276980 # number of overall hits
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-system.cpu.icache.ReadReq_misses::total 13753690 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 13753690 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 13753690 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 13753690 # number of overall misses
-system.cpu.icache.overall_misses::total 13753690 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 184520052183 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 184520052183 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 184520052183 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 184520052183 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 184520052183 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 184520052183 # number of overall miss cycles
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-system.cpu.icache.ReadReq_accesses::total 894030670 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 894030670 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 894030670 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 894030670 # number of overall (read+write) accesses
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-system.cpu.icache.ReadReq_miss_rate::total 0.015384 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.015384 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.015384 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.015384 # miss rate for overall accesses
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-system.cpu.l2cache.demand_mshr_misses::cpu.data 787946 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 875689 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4157 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4054 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 79532 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 787946 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 875689 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 305614500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 305848750 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5531016720 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19548409701 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25690889671 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16058529504 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16058529504 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 625079648 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 625079648 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 135000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35188398563 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35188398563 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 305614500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 305848750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5531016720 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54736808264 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 60879288234 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 305614500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 305848750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5531016720 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54736808264 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 60879288234 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2585776000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5279091500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7864867500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5180093000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5180093000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2585776000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10459184500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13044960500 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.040274 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017101 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.413482 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.413482 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783297 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783297 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238298 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238298 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.037478 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.037478 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69544.544586 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71077.372290 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70818.086437 # average ReadReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 31503.496902 # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31503.496902 # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17533.299150 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17533.299150 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68604.603021 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68604.603021 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 7878976 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339565 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232795 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 45517 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 45519 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 2152414 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 2152414 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27593630 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28534080 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 622119 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 992785 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 57742614 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 880408660 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1158207750 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2038152 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 470306 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 32992382 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.003506 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.059104 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 32876724 99.65% 99.65% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 115658 0.35% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 32992382 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 20698021683 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 14320653166 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 367823750 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 617486750 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40333 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40333 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
-system.iobus.trans_dist::WriteResp 29907 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231024 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231024 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353808 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334528 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7492448 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 606968921 # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 148463571 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 115493 # number of replacements
-system.iocache.tags.tagsinuse 10.456626 # Cycle average of tags in use
-system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115509 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13157260299000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.510556 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 6.946069 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.219410 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.434129 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.653539 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1039965 # Number of tag accesses
-system.iocache.tags.data_accesses 1039965 # Number of data accesses
-system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8848 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8885 # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
-system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 8848 # number of demand (read+write) misses
-system.iocache.demand_misses::total 8888 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 8848 # number of overall misses
-system.iocache.overall_misses::total 8888 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 1591055254 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 1596127254 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19834612096 # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total 19834612096 # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide 1591055254 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 1596479754 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide 1591055254 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 1596479754 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8848 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8885 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 8848 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 8888 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 8848 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 8888 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
-system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 179820.892179 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 179642.909848 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185954.137253 # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 185954.137253 # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 179621.934518 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 179621.934518 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 109316 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 16121 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 6.780969 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks::writebacks 106630 # number of writebacks
-system.iocache.writebacks::total 106630 # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide 8848 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 8885 # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 8848 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 8888 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 8848 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 8888 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 1129796362 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 1132938362 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14288050130 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14288050130 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 1129796362 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 1133131862 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 1129796362 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 1133131862 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127689.462251 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 127511.351941 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133953.818814 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133953.818814 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 448489 # Transaction distribution
-system.membus.trans_dist::ReadResp 448489 # Transaction distribution
-system.membus.trans_dist::WriteReq 33710 # Transaction distribution
-system.membus.trans_dist::WriteResp 33710 # Transaction distribution
-system.membus.trans_dist::Writeback 1214153 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 616398 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 616398 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 36221 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 36223 # Transaction distribution
-system.membus.trans_dist::ReadExReq 512353 # Transaction distribution
-system.membus.trans_dist::ReadExResp 512353 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4040402 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4170106 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4505175 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 159663776 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 159833626 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 3324 # Total snoops (count)
-system.membus.snoop_fanout::samples 2750930 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 2750930 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2750930 # Request fanout histogram
-system.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 5171500 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 10418059043 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 5433894864 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 151694929 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.realview.ethernet.txBytes 966 # Bytes Transmitted
-system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets 3 # Total Packets
-system.realview.ethernet.totBytes 966 # Total Bytes
-system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[ 0.000000] Initializing cgroup subsys cpu\r
-[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[ 0.000000] Memory limited to 256MB\r
-[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[ 0.000000] On node 0 totalpages: 65536\r
-[ 0.000000] DMA zone: 896 pages used for memmap\r
-[ 0.000000] DMA zone: 0 pages reserved\r
-[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
-[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
-[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[ 0.000000] Virtual kernel memory layout:\r
-[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
-[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
-[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
-[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
-[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
-[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
-[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[ 0.000000] Preemptible hierarchical RCU implementation.\r
-[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000039] Console: colour dummy device 80x25\r
-[ 0.000042] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000045] pid_max: default: 32768 minimum: 301\r
-[ 0.000065] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000068] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000254] hw perfevents: no hardware support available\r
-[ 1.060134] CPU1: failed to come online\r
-[ 2.080264] CPU2: failed to come online\r
-[ 3.100395] CPU3: failed to come online\r
-[ 3.100400] Brought up 1 CPUs\r
-[ 3.100402] SMP: Total of 1 processors activated.\r
-[ 3.100500] devtmpfs: initialized\r
-[ 3.101762] atomic64_test: passed\r
-[ 3.101843] regulator-dummy: no parameters\r
-[ 3.102644] NET: Registered protocol family 16\r
-[ 3.102917] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.102927] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.103581] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.103585] Serial: AMBA PL011 UART driver\r
-[ 3.103931] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.103997] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.104547] console [ttyAMA0] enabled\r
-[ 3.104647] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.104695] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.104744] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.104789] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130966] 3V3: 3300 mV \r
-[ 3.131042] vgaarb: loaded\r
-[ 3.131134] SCSI subsystem initialized\r
-[ 3.131205] libata version 3.00 loaded.\r
-[ 3.131293] usbcore: registered new interface driver usbfs\r
-[ 3.131321] usbcore: registered new interface driver hub\r
-[ 3.131375] usbcore: registered new device driver usb\r
-[ 3.131420] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.131429] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.131451] PTP clock support registered\r
-[ 3.131688] Switched to clocksource arch_sys_counter\r
-[ 3.133862] NET: Registered protocol family 2\r
-[ 3.134013] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.134040] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.134072] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.134099] TCP: reno registered\r
-[ 3.134107] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.134124] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.134187] NET: Registered protocol family 1\r
-[ 3.134256] RPC: Registered named UNIX socket transport module.\r
-[ 3.134266] RPC: Registered udp transport module.\r
-[ 3.134274] RPC: Registered tcp transport module.\r
-[ 3.134283] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.134296] PCI: CLS 0 bytes, default 64\r
-[ 3.134626] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.134832] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.138917] fuse init (API version 7.23)\r
-[ 3.139097] msgmni has been set to 469\r
-[ 3.143447] io scheduler noop registered\r
-[ 3.143560] io scheduler cfq registered (default)\r
-[ 3.144375] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.144389] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.144401] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.144415] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.144425] pci_bus 0000:00: scanning bus\r
-[ 3.144438] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.144452] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.144469] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.144534] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.144547] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.144560] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.144572] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.144584] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.144596] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.144609] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.144672] pci_bus 0000:00: fixups for bus\r
-[ 3.144681] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.144694] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.144718] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.144728] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.144741] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.144750] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.144764] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.144778] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.144792] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.144806] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.144818] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.144831] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.144844] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.144856] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.145803] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.146345] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.146356] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.146386] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.146981] scsi0 : ata_piix\r
-[ 3.147177] scsi1 : ata_piix\r
-[ 3.147237] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.147249] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.147450] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.147462] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.147484] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.147496] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.301720] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.301730] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.301764] ata1.00: configured for UDMA/33\r
-[ 3.301835] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.302052] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.302087] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.302146] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.302156] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.302186] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.302399] sda: sda1\r
-[ 3.302620] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.422060] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.422074] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.422105] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.422115] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.422148] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.422160] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.422304] usbcore: registered new interface driver usb-storage\r
-[ 3.422400] mousedev: PS/2 mouse device common for all mice\r
-[ 3.422718] usbcore: registered new interface driver usbhid\r
-[ 3.422728] usbhid: USB HID core driver\r
-[ 3.422776] TCP: cubic registered\r
-[ 3.422785] NET: Registered protocol family 17\r
-\0[ 3.423371] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.423415] devtmpfs: mounted\r
-[ 3.423469] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[ 3.470498] udevd[607]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[ 3.596627] random: dd urandom read with 22 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.801922] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-done.\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-boot_release_addr=65528
-cache_line_size=64
-clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_generic_timer=false
-have_large_asid_64=false
-have_lpae=false
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=atomic
-mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-num_work_ids=16
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
-reset_addr_64=0
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-delay=50000
-eventq_index=0
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=AtomicSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu0.dstage2_mmu
-dtb=system.cpu0.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-istage2_mmu=system.cpu0.istage2_mmu
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-width=1
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu0.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.dtb
-
-[system.cpu0.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu0.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu0.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.toL2Bus.slave[3]
-
-[system.cpu0.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=ArmISA
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu0.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.itb
-
-[system.cpu0.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.istage2_mmu.stage2_tlb.walker
-
-[system.cpu0.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu0.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-port=system.toL2Bus.slave[2]
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=AtomicSimpleCPU
-children=dstage2_mmu dtb isa istage2_mmu itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu1.dstage2_mmu
-dtb=system.cpu1.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=Null
-isa=system.cpu1.isa
-istage2_mmu=system.cpu1.istage2_mmu
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=true
-system=system
-tracer=system.cpu1.tracer
-width=1
-workload=
-
-[system.cpu1.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.dtb
-
-[system.cpu1.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu1.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu1.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu1.isa]
-type=ArmISA
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu1.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.itb
-
-[system.cpu1.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.istage2_mmu.stage2_tlb.walker
-
-[system.cpu1.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-sys=system
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-response_latency=2
-use_default_range=true
-width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=BaseCache
-children=tags
-addr_ranges=2147483648:2415919103
-assoc=8
-clk_domain=system.clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=false
-hit_latency=50
-is_top_level=true
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.master[27]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-hit_latency=50
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_top_level=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=0
-pio_latency=100000
-pio_size=8
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=2147483648:2415919103
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470024192
-pio_latency=100000
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-disks=
-eventq_index=0
-io_shift=2
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-platform=system.realview
-system=system
-config=system.iobus.master[9]
-dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-pio_addr=470286336
-pio_latency=100000
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-platform=system.realview
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-config=system.iobus.master[26]
-dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_num=29
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-int_latency=10000
-it_lines=128
-msix_addr=0
-platform=system.realview
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-pio_addr=721420288
-pio_latency=10000
-pixel_clock=7299
-system=system
-vnc=system.vncserver
-dma=system.membus.slave[0]
-pio=system.iobus.master[5]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-disks=system.cf0
-eventq_index=0
-io_shift=0
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-platform=system.realview
-system=system
-config=system.iobus.master[24]
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-pio_addr=470155264
-pio_latency=100000
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[6]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-pio_addr=470220800
-pio_latency=100000
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-pio_addr=738721792
-pio_latency=100000
-system=system
-pio=system.membus.master[3]
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470089728
-pio_latency=100000
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:67108863
-port=system.membus.master[1]
-
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=0
-pio_latency=30000
-platform=system.realview
-size=268435456
-system=system
-pio=system.iobus.default
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-eventq_index=0
-idreg=35979264
-pio_addr=469827584
-pio_latency=100000
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-pio_addr=471269376
-pio_latency=100000
-system=system
-time=Thu Jan 1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=true
-pio_addr=469893120
-pio_latency=100000
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-pio_addr=470876160
-pio_latency=100000
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-pio_addr=470941696
-pio_latency=100000
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470417408
-pio_latency=100000
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470482944
-pio_latency=100000
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470548480
-pio_latency=100000
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-pio_delay=10000
-platform=system.realview
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[4]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=402653184:436207615
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-eventq_index=0
-ignore_access=false
-pio_addr=470745088
-pio_latency=100000
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-response_latency=1
-snoop_filter=Null
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
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-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 29 2014 15:46:15
-gem5 started Oct 29 2014 16:13:02
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
- 0: system.cpu0.isa: ISA system set to: 0x5318b00 0x5318b00
- 0: system.cpu1.isa: ISA system set to: 0x5318b00 0x5318b00
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 51.111153 # Number of seconds simulated
-sim_ticks 51111152682000 # Number of ticks simulated
-final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1095499 # Simulator instruction rate (inst/s)
-host_op_rate 1287391 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 56869697369 # Simulator tick rate (ticks/s)
-host_mem_usage 728040 # Number of bytes of host memory used
-host_seconds 898.74 # Real time elapsed on the host
-sim_insts 984570519 # Number of instructions simulated
-sim_ops 1157031967 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 203392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 187968 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 3328564 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 37865864 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 208384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 188288 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 2234176 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 36967936 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory
-system.physmem.bytes_read::total 81626364 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 3328564 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 2234176 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 103043072 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 103063652 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 3178 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2937 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 92416 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 591667 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 3256 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 2942 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 34909 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 577624 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1315832 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1610048 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1612621 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 3979 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 3678 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 65124 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 740853 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 4077 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 3684 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 43712 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 723285 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1597036 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 65124 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 43712 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2016058 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2016461 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2016058 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 3979 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 65124 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 741256 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 4077 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 3684 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 43712 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 723285 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3613497 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
-system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 144734 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 144734 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples 144734 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 144734 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 144734 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 107995 85.62% 85.62% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 18140 14.38% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 126135 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144734 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144734 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126135 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126135 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 270869 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.inst_hits 0 # ITB inst hits
-system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 91873100 # DTB read hits
-system.cpu0.dtb.read_misses 107254 # DTB read misses
-system.cpu0.dtb.write_hits 84300346 # DTB write hits
-system.cpu0.dtb.write_misses 37480 # DTB write misses
-system.cpu0.dtb.flush_tlb 51121 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 56998 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 5021 # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 11101 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 91980354 # DTB read accesses
-system.cpu0.dtb.write_accesses 84337826 # DTB write accesses
-system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 176173446 # DTB hits
-system.cpu0.dtb.misses 144734 # DTB misses
-system.cpu0.dtb.accesses 176318180 # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 70623 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 70623 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples 70623 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 70623 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 70623 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 62003 96.05% 96.05% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 2552 3.95% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 64555 # Table walker page sizes translated
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70623 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70623 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64555 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64555 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 135178 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 493558289 # ITB inst hits
-system.cpu0.itb.inst_misses 70623 # ITB inst misses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 51121 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 40618 # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 493628912 # ITB inst accesses
-system.cpu0.itb.hits 493558289 # DTB hits
-system.cpu0.itb.misses 70623 # DTB misses
-system.cpu0.itb.accesses 493628912 # DTB accesses
-system.cpu0.numCycles 98036732821 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 493343054 # Number of instructions committed
-system.cpu0.committedOps 579320783 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 530703417 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 453665 # Number of float alu accesses
-system.cpu0.num_func_calls 28504103 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 76145406 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 530703417 # number of integer instructions
-system.cpu0.num_fp_insts 453665 # number of float instructions
-system.cpu0.num_int_register_reads 784985742 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 421507499 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 741739 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 362084 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 133043946 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 132723498 # number of times the CC registers were written
-system.cpu0.num_mem_refs 176296730 # number of memory refs
-system.cpu0.num_load_insts 91967123 # Number of load instructions
-system.cpu0.num_store_insts 84329607 # Number of store instructions
-system.cpu0.num_idle_cycles 96926191341.047134 # Number of idle cycles
-system.cpu0.num_busy_cycles 1110541479.952863 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.011328 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.988672 # Percentage of idle cycles
-system.cpu0.Branches 110281342 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 402074699 69.37% 69.37% # Class of executed instruction
-system.cpu0.op_class::IntMult 1168928 0.20% 69.57% # Class of executed instruction
-system.cpu0.op_class::IntDiv 50558 0.01% 69.58% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 52783 0.01% 69.59% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction
-system.cpu0.op_class::MemRead 91967123 15.87% 85.45% # Class of executed instruction
-system.cpu0.op_class::MemWrite 84329607 14.55% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 579643698 # Class of executed instruction
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 16775 # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements 11612141 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 340775537 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 29.345192 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 264.268132 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 247.731587 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.516149 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data 0.483851 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 1421165468 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 1421165468 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 85681160 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 85885886 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 171567046 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 79835128 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 79687740 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 159522868 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 208530 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data 215328 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 423858 # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 146037 # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 191672 # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total 337709 # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2127418 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2183031 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 4310449 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2250403 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2312061 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 165516288 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 165573626 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 331089914 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 165724818 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 165788954 # number of overall hits
-system.cpu0.dcache.overall_hits::total 331513772 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 3015225 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 2995068 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 6010293 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1305618 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 1264641 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 2570259 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 792908 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data 791180 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 1584088 # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 765143 # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 480206 # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total 1245349 # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 123898 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 129919 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 253817 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 4320843 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data 4259709 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 8580552 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 5113751 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data 5050889 # number of overall misses
-system.cpu0.dcache.overall_misses::total 10164640 # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 88696385 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data 88880954 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 81140746 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data 80952381 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1001438 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 1006508 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 2007946 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 911180 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 671878 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total 1583058 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2251316 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2312950 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2250403 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2312062 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 169837131 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data 169833335 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 170838569 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data 170839843 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 341678412 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033995 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033698 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.033846 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016091 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015622 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.791769 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.786064 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788910 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839728 # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.714722 # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055034 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056170 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055610 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000000 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025441 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025082 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029933 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029565 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 8921315 # number of writebacks
-system.cpu0.dcache.writebacks::total 8921315 # number of writebacks
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 14295641 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 970865862 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 268.250565 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 243.734034 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.523927 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.476043 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 999458178 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 999458178 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 486466334 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 484399528 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 970865862 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 486466334 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 484399528 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 970865862 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 486466334 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 484399528 # number of overall hits
-system.cpu0.icache.overall_hits::total 970865862 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 7156510 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 7139648 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 14296158 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 7156510 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 7139648 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 14296158 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 7156510 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 7139648 # number of overall misses
-system.cpu0.icache.overall_misses::total 14296158 # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 493622844 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 491539176 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 493622844 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 491539176 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 493622844 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 491539176 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014498 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014525 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014498 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014525 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014498 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014525 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 143589 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 143589 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walkWaitTime::samples 143589 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 143589 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 143589 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walksPending::samples 1000001000 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 1000001000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 1000001000 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 106707 85.51% 85.51% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 18085 14.49% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 124792 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143589 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143589 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124792 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124792 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 268381 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.inst_hits 0 # ITB inst hits
-system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 92120843 # DTB read hits
-system.cpu1.dtb.read_misses 106565 # DTB read misses
-system.cpu1.dtb.write_hits 83929435 # DTB write hits
-system.cpu1.dtb.write_misses 37024 # DTB write misses
-system.cpu1.dtb.flush_tlb 51112 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 56458 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 4753 # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 10550 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 92227408 # DTB read accesses
-system.cpu1.dtb.write_accesses 83966459 # DTB write accesses
-system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 176050278 # DTB hits
-system.cpu1.dtb.misses 143589 # DTB misses
-system.cpu1.dtb.accesses 176193867 # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 69863 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 69863 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walkWaitTime::samples 69863 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 69863 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 69863 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 61226 95.98% 95.98% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 2567 4.02% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 63793 # Table walker page sizes translated
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69863 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69863 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63793 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63793 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 133656 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 491475383 # ITB inst hits
-system.cpu1.itb.inst_misses 69863 # ITB inst misses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 51112 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 40934 # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 491545246 # ITB inst accesses
-system.cpu1.itb.hits 491475383 # DTB hits
-system.cpu1.itb.misses 69863 # DTB misses
-system.cpu1.itb.accesses 491545246 # DTB accesses
-system.cpu1.numCycles 97463064529 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 491227465 # Number of instructions committed
-system.cpu1.committedOps 577711184 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 529752049 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 427140 # Number of float alu accesses
-system.cpu1.num_func_calls 28552264 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 75795428 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 529752049 # number of integer instructions
-system.cpu1.num_fp_insts 427140 # number of float instructions
-system.cpu1.num_int_register_reads 779016428 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 420937292 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 677260 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 385836 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 131363112 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 131105905 # number of times the CC registers were written
-system.cpu1.num_mem_refs 176168876 # number of memory refs
-system.cpu1.num_load_insts 92213308 # Number of load instructions
-system.cpu1.num_store_insts 83955568 # Number of store instructions
-system.cpu1.num_idle_cycles 96357044010.669601 # Number of idle cycles
-system.cpu1.num_busy_cycles 1106020518.330400 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.011348 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.988652 # Percentage of idle cycles
-system.cpu1.Branches 109807220 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 400561917 69.30% 69.30% # Class of executed instruction
-system.cpu1.op_class::IntMult 1185819 0.21% 69.50% # Class of executed instruction
-system.cpu1.op_class::IntDiv 51201 0.01% 69.51% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 55039 0.01% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::MemRead 92213308 15.95% 85.48% # Class of executed instruction
-system.cpu1.op_class::MemWrite 83955568 14.52% 100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 578022895 # Class of executed instruction
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
-system.iobus.trans_dist::WriteResp 29851 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.replacements 115463 # number of replacements
-system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use
-system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1039686 # Number of tag accesses
-system.iocache.tags.data_accesses 1039686 # Number of data accesses
-system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
-system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
-system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses
-system.iocache.demand_misses::total 8857 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 8817 # number of overall misses
-system.iocache.overall_misses::total 8857 # number of overall misses
-system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses
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-system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
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-system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
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-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
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-system.l2c.tags.tagsinuse 65341.862498 # Cycle average of tags in use
-system.l2c.tags.total_refs 30065488 # Total number of references to valid blocks.
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-system.l2c.tags.occ_blocks::cpu0.itb.walker 243.495240 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 3601.604762 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 9619.799415 # Average occupied blocks per requestor
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-system.l2c.tags.occ_blocks::cpu1.itb.walker 201.240500 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 2659.657984 # Average occupied blocks per requestor
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-system.l2c.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 2715 # Occupied blocks per task id
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-system.l2c.ReadReq_hits::cpu1.itb.walker 142760 # number of ReadReq hits
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-system.l2c.ReadReq_hits::total 22560458 # number of ReadReq hits
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-system.l2c.Writeback_hits::total 8921315 # number of Writeback hits
-system.l2c.WriteInvalidateReq_hits::cpu0.data 345123 # number of WriteInvalidateReq hits
-system.l2c.WriteInvalidateReq_hits::cpu1.data 349209 # number of WriteInvalidateReq hits
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-system.l2c.UpgradeReq_hits::cpu1.data 5536 # number of UpgradeReq hits
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-system.l2c.demand_hits::cpu1.inst 7104726 # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu0.inst 7107195 # number of overall hits
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-system.l2c.overall_hits::cpu1.dtb.walker 276854 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 142760 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 7104726 # number of overall hits
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-system.l2c.overall_hits::total 24253067 # number of overall hits
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-system.l2c.ReadReq_misses::cpu0.inst 49315 # number of ReadReq misses
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-system.l2c.ReadReq_misses::cpu1.itb.walker 2942 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 34922 # number of ReadReq misses
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-system.l2c.ReadExReq_misses::total 826508 # number of ReadExReq misses
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-system.l2c.demand_misses::cpu0.data 592123 # number of demand (read+write) misses
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-system.l2c.overall_misses::cpu0.inst 49315 # number of overall misses
-system.l2c.overall_misses::cpu0.data 592123 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 3256 # number of overall misses
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-system.l2c.overall_misses::cpu1.inst 34922 # number of overall misses
-system.l2c.overall_misses::cpu1.data 578352 # number of overall misses
-system.l2c.overall_misses::total 1267025 # number of overall misses
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-system.l2c.ReadReq_accesses::cpu0.data 3932031 # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_accesses::total 23000975 # number of ReadReq accesses(hits+misses)
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-system.l2c.Writeback_accesses::total 8921315 # number of Writeback accesses(hits+misses)
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-system.l2c.WriteInvalidateReq_accesses::cpu1.data 480206 # number of WriteInvalidateReq accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu1.data 25461 # number of UpgradeReq accesses(hits+misses)
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-system.l2c.demand_accesses::cpu0.inst 7156510 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 5211968 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 280110 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 145702 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 7139648 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 5155347 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 25520092 # number of demand (read+write) accesses
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-system.l2c.overall_accesses::cpu0.itb.walker 148194 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 7156510 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 5211968 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 280110 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 145702 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 7139648 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 5155347 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 25520092 # number of overall (read+write) accesses
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-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019819 # miss rate for ReadReq accesses
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-system.l2c.ReadReq_miss_rate::cpu0.data 0.045030 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.020192 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.004891 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.042620 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses
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-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782569 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.780552 # miss rate for UpgradeReq accesses
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-system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
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-system.l2c.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses
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-system.l2c.demand_miss_rate::cpu1.inst 0.004891 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.112185 # miss rate for demand accesses
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-system.membus.trans_dist::WriteResp 33606 # Transaction distribution
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-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
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-system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 227116986 # Cumulative packet size per connected master and slave (bytes)
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-system.membus.snoop_fanout::mean 1 # Request fanout histogram
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-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3583531 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
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-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3583531 # Request fanout histogram
-system.realview.ethernet.txBytes 966 # Bytes Transmitted
-system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets 3 # Total Packets
-system.realview.ethernet.totBytes 966 # Total Bytes
-system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 23464706 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 23464706 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 51142 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 51143 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28678566 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32383249 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832126 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655216 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 63549157 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3328504 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 2239440306 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 116338 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 36240472 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 3.003188 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.056369 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 36124951 99.68% 99.68% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 36240472 # Request fanout histogram
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[ 0.000000] Initializing cgroup subsys cpu\r
-[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[ 0.000000] Memory limited to 256MB\r
-[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[ 0.000000] On node 0 totalpages: 65536\r
-[ 0.000000] DMA zone: 896 pages used for memmap\r
-[ 0.000000] DMA zone: 0 pages reserved\r
-[ 0.000000] DMA zone: 65536 pages, LIFO batch:15\r
-[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640\r
-[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[ 0.000000] Virtual kernel memory layout:\r
-[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)\r
-[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)\r
-[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)\r
-[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)\r
-[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)\r
-[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)\r
-[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)\r
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[ 0.000000] Preemptible hierarchical RCU implementation.\r
-[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000013] Console: colour dummy device 80x25\r
-[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000015] pid_max: default: 32768 minimum: 301\r
-[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000066] hw perfevents: no hardware support available\r
-[ 1.060049] CPU1: failed to come online\r
-[ 2.080098] CPU2: failed to come online\r
-[ 3.100148] CPU3: failed to come online\r
-[ 3.100150] Brought up 1 CPUs\r
-[ 3.100151] SMP: Total of 1 processors activated.\r
-[ 3.100177] devtmpfs: initialized\r
-[ 3.100579] atomic64_test: passed\r
-[ 3.100603] regulator-dummy: no parameters\r
-[ 3.100844] NET: Registered protocol family 16\r
-[ 3.100938] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.100941] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.100980] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.100981] Serial: AMBA PL011 UART driver\r
-[ 3.101103] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.101125] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.101160] console [ttyAMA0] enabled\r
-[ 3.101194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.101208] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.101222] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.101235] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130356] 3V3: 3300 mV \r
-[ 3.130377] vgaarb: loaded\r
-[ 3.130406] SCSI subsystem initialized\r
-[ 3.130425] libata version 3.00 loaded.\r
-[ 3.130450] usbcore: registered new interface driver usbfs\r
-[ 3.130457] usbcore: registered new interface driver hub\r
-[ 3.130471] usbcore: registered new device driver usb\r
-[ 3.130482] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.130483] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.130487] PTP clock support registered\r
-[ 3.130559] Switched to clocksource arch_sys_counter\r
-[ 3.131204] NET: Registered protocol family 2\r
-[ 3.131250] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.131255] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.131259] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.131263] TCP: reno registered\r
-[ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131281] NET: Registered protocol family 1\r
-[ 3.131310] RPC: Registered named UNIX socket transport module.\r
-[ 3.131311] RPC: Registered udp transport module.\r
-[ 3.131312] RPC: Registered tcp transport module.\r
-[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.131315] PCI: CLS 0 bytes, default 64\r
-[ 3.131413] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.131456] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.132687] fuse init (API version 7.23)\r
-[ 3.132738] msgmni has been set to 469\r
-[ 3.133992] io scheduler noop registered\r
-[ 3.134024] io scheduler cfq registered (default)\r
-[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.134301] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.134302] pci_bus 0000:00: scanning bus\r
-[ 3.134304] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.134306] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.134329] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.134336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.134354] pci_bus 0000:00: fixups for bus\r
-[ 3.134355] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.134361] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.134363] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.134365] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.134367] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.134372] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.134377] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.134813] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.134815] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.134820] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.135009] scsi0 : ata_piix\r
-[ 3.135063] scsi1 : ata_piix\r
-[ 3.135081] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.135082] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.135143] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.135144] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.135148] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.135150] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.290565] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.290566] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.290572] ata1.00: configured for UDMA/33\r
-[ 3.290589] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.290650] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.290658] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.290672] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.290673] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.290680] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.290733] sda: sda1\r
-[ 3.290795] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.410824] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.410825] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.410832] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.410833] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.410841] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.410842] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.410886] usbcore: registered new interface driver usb-storage\r
-[ 3.410912] mousedev: PS/2 mouse device common for all mice\r
-[ 3.411009] usbcore: registered new interface driver usbhid\r
-[ 3.411010] usbhid: USB HID core driver\r
-[ 3.411025] TCP: cubic registered\r
-[ 3.411026] NET: Registered protocol family 17\r
-\0[ 3.411204] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.411214] devtmpfs: mounted\r
-[ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[ 3.446950] udevd[607]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[ 3.532262] random: dd urandom read with 19 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.640780] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-done.\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=atomic
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+eventq_index=0
+size=64
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=AlphaISA
+eventq_index=0
+system=system
+
+[system.cpu.itb]
+type=AlphaTLB
+eventq_index=0
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:27:58
+gem5 executing on u200540-lin
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 44221003000 because target called exit()
--- /dev/null
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := True
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 8
+ sizeof(longaddr ) = 8
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 8
+ sizeof(char * ) = 8
+ ALLOC CORE_1 :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 4005c800
+
+ OPEN File ./input/lendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
--- /dev/null
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.044221 # Number of seconds simulated
+sim_ticks 44221003000 # Number of ticks simulated
+final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 2813944 # Simulator instruction rate (inst/s)
+host_op_rate 2813942 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1408584494 # Simulator tick rate (ticks/s)
+host_mem_usage 287952 # Number of bytes of host memory used
+host_seconds 31.39 # Real time elapsed on the host
+sim_insts 88340673 # Number of instructions simulated
+sim_ops 88340673 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory
+system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 353752292 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 353752292 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data 91652896 # Number of bytes written to this memory
+system.physmem.bytes_written::total 91652896 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 88438073 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 20276638 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 108714711 # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data 14613377 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 14613377 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 7999644241 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2865214229 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 10864858470 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7999644241 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7999644241 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 2072610067 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2072610067 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 108714711 # Transaction distribution
+system.membus.trans_dist::ReadResp 108714711 # Transaction distribution
+system.membus.trans_dist::WriteReq 14613377 # Transaction distribution
+system.membus.trans_dist::WriteResp 14613377 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 123328088 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram
+system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 123328088 # Request fanout histogram
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 20276638 # DTB read hits
+system.cpu.dtb.read_misses 90148 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 20366786 # DTB read accesses
+system.cpu.dtb.write_hits 14613377 # DTB write hits
+system.cpu.dtb.write_misses 7252 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 14620629 # DTB write accesses
+system.cpu.dtb.data_hits 34890015 # DTB hits
+system.cpu.dtb.data_misses 97400 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 34987415 # DTB accesses
+system.cpu.itb.fetch_hits 88438073 # ITB hits
+system.cpu.itb.fetch_misses 3934 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 88442007 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 4583 # Number of system calls
+system.cpu.numCycles 88442007 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 88340673 # Number of instructions committed
+system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
+system.cpu.num_func_calls 3321606 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
+system.cpu.num_int_insts 78039444 # number of integer instructions
+system.cpu.num_fp_insts 267757 # number of float instructions
+system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
+system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
+system.cpu.num_mem_refs 34987415 # number of memory refs
+system.cpu.num_load_insts 20366786 # Number of load instructions
+system.cpu.num_store_insts 14620629 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 88442007 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.Branches 13754477 # Number of branches fetched
+system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction
+system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction
+system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction
+system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction
+system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction
+system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction
+system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction
+system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction
+system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 88438073 # Class of executed instruction
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=262144
+
+[system.cpu.dtb]
+type=AlphaTLB
+eventq_index=0
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=131072
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=AlphaISA
+eventq_index=0
+system=system
+
+[system.cpu.itb]
+type=AlphaTLB
+eventq_index=0
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=2097152
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:28:33
+gem5 executing on u200540-lin
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 133634727000 because target called exit()
--- /dev/null
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := True
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 8
+ sizeof(longaddr ) = 8
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 8
+ sizeof(char * ) = 8
+ ALLOC CORE_1 :: 16
+ BHOOLE NATH
+
+ OPEN File ./input/lendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 4005c800
+
+ OPEN File ./input/lendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
--- /dev/null
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.133634 # Number of seconds simulated
+sim_ticks 133634149500 # Number of ticks simulated
+final_tick 133634149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1329181 # Simulator instruction rate (inst/s)
+host_op_rate 1329181 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2010669405 # Simulator tick rate (ticks/s)
+host_mem_usage 301232 # Number of bytes of host memory used
+host_seconds 66.46 # Real time elapsed on the host
+sim_insts 88340673 # Number of instructions simulated
+sim_ops 88340673 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10136896 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10569792 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 432896 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 432896 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7294848 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7294848 # Number of bytes written to this memory
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+system.physmem.num_reads::cpu.data 158389 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 165153 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 113982 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 113982 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 3239411 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 75855581 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 79094992 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 3239411 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 3239411 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 54588202 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 54588202 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 54588202 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 3239411 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 75855581 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 133683195 # Total bandwidth to/from this memory (bytes/s)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 20276638 # DTB read hits
+system.cpu.dtb.read_misses 90148 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 20366786 # DTB read accesses
+system.cpu.dtb.write_hits 14613377 # DTB write hits
+system.cpu.dtb.write_misses 7252 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 14620629 # DTB write accesses
+system.cpu.dtb.data_hits 34890015 # DTB hits
+system.cpu.dtb.data_misses 97400 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 34987415 # DTB accesses
+system.cpu.itb.fetch_hits 88438074 # ITB hits
+system.cpu.itb.fetch_misses 3934 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 88442008 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 4583 # Number of system calls
+system.cpu.numCycles 267268299 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 88340673 # Number of instructions committed
+system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
+system.cpu.num_func_calls 3321606 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls
+system.cpu.num_int_insts 78039444 # number of integer instructions
+system.cpu.num_fp_insts 267757 # number of float instructions
+system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read
+system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written
+system.cpu.num_mem_refs 34987415 # number of memory refs
+system.cpu.num_load_insts 20366786 # Number of load instructions
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+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 267268299 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.Branches 13754477 # Number of branches fetched
+system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction
+system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction
+system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction
+system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction
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+system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction
+system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction
+system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction
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+system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction
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+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction
+system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction
+system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 88438073 # Class of executed instruction
+system.cpu.dcache.tags.replacements 200248 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4078.863526 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 936464000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863526 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
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+system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses
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+system.cpu.dcache.overall_misses::total 204344 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945427000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 1945427000 # number of ReadReq miss cycles
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+system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses
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+system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32015.057763 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32015.057763 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51285.900347 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 51285.900347 # average WriteReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 45555.308695 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 45555.308695 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
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+system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks
+system.cpu.dcache.writebacks::total 168375 # number of writebacks
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+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9002438000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 9002438000 # number of demand (read+write) MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total 9002438000 # number of overall MSHR miss cycles
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30515.057763 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30515.057763 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49785.900347 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49785.900347 # average WriteReq mshr miss latency
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+system.cpu.dcache.demand_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.icache.tags.tagsinuse 1871.686268 # Cycle average of tags in use
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+system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 176952584 # Number of tag accesses
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+system.cpu.icache.ReadReq_miss_latency::total 1277887500 # number of ReadReq miss cycles
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+system.cpu.icache.overall_miss_latency::cpu.inst 1277887500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 1277887500 # number of overall miss cycles
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+system.cpu.icache.ReadReq_miss_rate::total 0.000864 # miss rate for ReadReq accesses
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+system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16718.398399 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16718.398399 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16718.398399 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16718.398399 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 76436 # number of ReadReq MSHR misses
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+system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1163233500 # number of ReadReq MSHR miss cycles
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+system.cpu.icache.demand_mshr_miss_latency::total 1163233500 # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total 1163233500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15218.398399 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15218.398399 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15218.398399 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 15218.398399 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15218.398399 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 15218.398399 # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.tags.replacements 131235 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 30728.805700 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 27298.442194 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.509533 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853974 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.833082 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 32056 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 654 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9977 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21193 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 117 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978271 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 3900109 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 3900109 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 69672 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 33258 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 102930 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 168375 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 168375 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 12697 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 12697 # number of ReadExReq hits
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+system.cpu.l2cache.demand_hits::cpu.data 45955 # number of demand (read+write) hits
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+system.cpu.l2cache.overall_hits::cpu.data 45955 # number of overall hits
+system.cpu.l2cache.overall_hits::total 115627 # number of overall hits
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+system.cpu.l2cache.Writeback_accesses::writebacks 168375 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 168375 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088492 # miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadExReq_miss_rate::total 0.911567 # miss rate for ReadExReq accesses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.441159 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.834957 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52507.717670 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.084046 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.084046 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52501.668150 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52501.668150 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks 113982 # number of writebacks
+system.cpu.l2cache.writebacks::total 113982 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 6764 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27508 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 34272 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130881 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 130881 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 6764 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 158389 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 165153 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 158389 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 165153 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 274073000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1114207000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1388280000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5300691500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5300691500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 274073000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6414898500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 6688971500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 274073000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6414898500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 6688971500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.452687 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.249792 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911567 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911567 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.588194 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.588194 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.367238 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40504.834957 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40507.703081 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.084046 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.084046 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152872 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577063 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 729935 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 449155 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 449155 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 449155 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 34272 # Transaction distribution
+system.membus.trans_dist::ReadResp 34272 # Transaction distribution
+system.membus.trans_dist::Writeback 113982 # Transaction distribution
+system.membus.trans_dist::ReadExReq 130881 # Transaction distribution
+system.membus.trans_dist::ReadExResp 130881 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 279135 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 279135 # Request fanout histogram
+system.membus.reqLayer0.occupancy 748161500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
+system.membus.respLayer1.occupancy 825765500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=atomic
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
+dtb=system.cpu.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.membus.slave[6]
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.membus.slave[4]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.membus.slave[5]
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.membus.slave[3]
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2014 12:08:08
+gem5 started Jan 23 2014 18:03:38
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+ 0: system.cpu.isa: ISA system set to: 0 0x49b6380
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 53932157000 because target called exit()
--- /dev/null
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.048960 # Number of seconds simulated
+sim_ticks 48960011000 # Number of ticks simulated
+final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1566427 # Simulator instruction rate (inst/s)
+host_op_rate 2003243 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1081494789 # Simulator tick rate (ticks/s)
+host_mem_usage 308080 # Number of bytes of host memory used
+host_seconds 45.27 # Real time elapsed on the host
+sim_insts 70913181 # Number of instructions simulated
+sim_ops 90688136 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory
+system.physmem.bytes_read::total 419153617 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 312580272 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 312580272 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory
+system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 78145068 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 101064798 # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 6384399546 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2176742669 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 8561142215 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 6384399546 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 6384399546 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1606621596 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1606621596 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 6384399546 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3783364264 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 10167763810 # Total bandwidth to/from this memory (bytes/s)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.walks 0 # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.walks 0 # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.numCycles 97920023 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 70913181 # Number of instructions committed
+system.cpu.committedOps 90688136 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
+system.cpu.num_func_calls 3311620 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls
+system.cpu.num_int_insts 81528488 # number of integer instructions
+system.cpu.num_fp_insts 56 # number of float instructions
+system.cpu.num_int_register_reads 141479310 # number of times the integer registers were read
+system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
+system.cpu.num_cc_register_reads 266608028 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written
+system.cpu.num_mem_refs 43422001 # number of memory refs
+system.cpu.num_load_insts 22866262 # Number of load instructions
+system.cpu.num_store_insts 20555739 # Number of store instructions
+system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
+system.cpu.num_busy_cycles 97920022.998000 # Number of busy cycles
+system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
+system.cpu.Branches 13741485 # Number of branches fetched
+system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction
+system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction
+system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 90690083 # Class of executed instruction
+system.membus.trans_dist::ReadReq 100925135 # Transaction distribution
+system.membus.trans_dist::ReadResp 100941054 # Transaction distribution
+system.membus.trans_dist::WriteReq 19849901 # Transaction distribution
+system.membus.trans_dist::WriteResp 19849901 # Transaction distribution
+system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution
+system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution
+system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution
+system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution
+system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290136 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 241861236 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580272 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 120930618 # Request fanout histogram
+system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram
+system.membus.snoop_fanout::3 78145068 64.62% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 2 # Request fanout histogram
+system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::total 120930618 # Request fanout histogram
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
+dtb=system.cpu.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=262144
+
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[5]
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[3]
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=131072
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[4]
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=2097152
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2014 12:08:08
+gem5 started Jan 23 2014 18:04:30
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+ 0: system.cpu.isa: ISA system set to: 0 0x5604d00
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 132689045000 because target called exit()
--- /dev/null
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.127293 # Number of seconds simulated
+sim_ticks 127293405500 # Number of ticks simulated
+final_tick 127293405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 802256 # Simulator instruction rate (inst/s)
+host_op_rate 1024256 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1451138855 # Simulator tick rate (ticks/s)
+host_mem_usage 317568 # Number of bytes of host memory used
+host_seconds 87.72 # Real time elapsed on the host
+sim_insts 70373628 # Number of instructions simulated
+sim_ops 89847362 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory
+system.physmem.bytes_read::total 8179968 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 255488 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 255488 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5370176 # Number of bytes written to this memory
+system.physmem.bytes_written::total 5370176 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3992 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2007080 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 62253657 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 64260737 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2007080 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2007080 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 42187386 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 42187386 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 42187386 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2007080 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 62253657 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 106448122 # Total bandwidth to/from this memory (bytes/s)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.walks 0 # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.walks 0 # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.numCycles 254586811 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 70373628 # Number of instructions committed
+system.cpu.committedOps 89847362 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
+system.cpu.num_func_calls 3311620 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls
+system.cpu.num_int_insts 81528488 # number of integer instructions
+system.cpu.num_fp_insts 56 # number of float instructions
+system.cpu.num_int_register_reads 141328474 # number of times the integer registers were read
+system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
+system.cpu.num_cc_register_reads 334802003 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written
+system.cpu.num_mem_refs 43422001 # number of memory refs
+system.cpu.num_load_insts 22866262 # Number of load instructions
+system.cpu.num_store_insts 20555739 # Number of store instructions
+system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
+system.cpu.num_busy_cycles 254586810.998000 # Number of busy cycles
+system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
+system.cpu.Branches 13741485 # Number of branches fetched
+system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction
+system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction
+system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction
+system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 90690083 # Class of executed instruction
+system.cpu.dcache.tags.replacements 155902 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4076.389361 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 42608169 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 266.304385 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 1061070000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389361 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
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+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1133331500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1343378500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371640000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 5371640000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 210047000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 6504971500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 6715018500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 210047000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 6504971500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 6715018500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 128239 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 128239 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.211128 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.406676 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.355233 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955602 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.955602 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.211128 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.773885 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.714409 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.714409 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52616.983968 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52615.204271 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52615.482532 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52518.967540 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52518.967540 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52538.247582 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52538.247582 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks 83909 # number of writebacks
+system.cpu.l2cache.writebacks::total 83909 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3992 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21540 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 25532 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3992 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 123820 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 127812 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 161778000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 873989500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1035767500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4142346500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4142346500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161778000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5016336000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 5178114000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161778000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5016336000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 5178114000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955602 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40525.551102 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40575.185701 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40567.425192 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.063551 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.063551 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37816 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 448235 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 486051 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 307145 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 25532 # Transaction distribution
+system.membus.trans_dist::ReadResp 25532 # Transaction distribution
+system.membus.trans_dist::Writeback 83909 # Transaction distribution
+system.membus.trans_dist::ReadExReq 102280 # Transaction distribution
+system.membus.trans_dist::ReadExResp 102280 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 214640 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 214640 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 214640 # Request fanout histogram
+system.membus.reqLayer0.occupancy 566253984 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
+system.membus.respLayer1.occupancy 642220500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=atomic
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.dtb]
+type=SparcTLB
+eventq_index=0
+size=64
+
+[system.cpu.interrupts]
+type=SparcInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=SparcISA
+eventq_index=0
+
+[system.cpu.itb]
+type=SparcTLB
+eventq_index=0
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex bendian.raw
+cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: ignoring syscall time(4026528248, 4026527848, ...)
+warn: ignoring syscall time(1375098, 4026527400, ...)
+warn: ignoring syscall time(1, 4026527312, ...)
+warn: ignoring syscall time(413, 4026527048, ...)
+warn: ignoring syscall time(414, 4026527048, ...)
+warn: ignoring syscall time(4026527688, 4026527288, ...)
+warn: ignoring syscall time(1375098, 4026526840, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026526960, ...)
+warn: ignoring syscall time(409, 4026527040, ...)
+warn: ignoring syscall time(409, 4026527000, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(19045, 4026526312, ...)
+warn: ignoring syscall time(409, 4026526832, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
+warn: ignoring syscall time(409, 4026526840, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
+warn: ignoring syscall time(409, 4026526936, ...)
+warn: ignoring syscall time(4026527408, 4026527008, ...)
+warn: ignoring syscall time(1375098, 4026526560, ...)
+warn: ignoring syscall time(18732, 4026527184, ...)
+warn: ignoring syscall time(409, 4026526632, ...)
+warn: ignoring syscall time(0, 4026526736, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
+warn: ignoring syscall time(225, 4026527744, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(4026527496, 4026527096, ...)
+warn: ignoring syscall time(1375098, 4026526648, ...)
+warn: ignoring syscall time(0, 4026526824, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
+warn: ignoring syscall time(1879089152, 4026527184, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
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+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall time(1595768, 4026527472, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
+warn: ignoring syscall time(20500, 4026525968, ...)
+warn: ignoring syscall time(4026526436, 4026525968, ...)
+warn: ignoring syscall time(7004192, 4026526056, ...)
+warn: ignoring syscall time(4, 4026527512, ...)
+warn: ignoring syscall time(0, 4026525760, ...)
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:46:20
+gem5 executing on u200540-lin
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 68148672000 because target called exit()
--- /dev/null
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := False
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 4
+ sizeof(longaddr ) = 4
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 4
+ sizeof(char * ) = 4
+ ALLOC CORE_1 :: 8
+ BHOOLE NATH
+
+ OPEN File ./input/bendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 1b4750
+
+ OPEN File ./input/bendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
--- /dev/null
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.068149 # Number of seconds simulated
+sim_ticks 68148672000 # Number of ticks simulated
+final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 2078407 # Simulator instruction rate (inst/s)
+host_op_rate 2105318 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1053881878 # Simulator tick rate (ticks/s)
+host_mem_usage 288492 # Number of bytes of host memory used
+host_seconds 64.66 # Real time elapsed on the host
+sim_insts 134398962 # Number of instructions simulated
+sim_ops 136139190 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 538214280 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory
+system.physmem.bytes_read::total 685773640 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 538214280 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 538214280 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory
+system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 134553570 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 171784870 # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory
+system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory
+system.physmem.num_other::total 15916 # Number of other requests responded to by this memory
+system.physmem.bw_read::cpu.inst 7897648835 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2165256573 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 10062905408 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7897648835 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7897648835 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1318924454 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1318924454 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 171784870 # Transaction distribution
+system.membus.trans_dist::ReadResp 171784870 # Transaction distribution
+system.membus.trans_dist::WriteReq 20864304 # Transaction distribution
+system.membus.trans_dist::WriteResp 20864304 # Transaction distribution
+system.membus.trans_dist::SwapReq 15916 # Transaction distribution
+system.membus.trans_dist::SwapResp 15916 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107140 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 385330180 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214280 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 775783918 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 192665090 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram
+system.membus.snoop_fanout::1 134553570 69.84% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 192665090 # Request fanout histogram
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.numCycles 136297345 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 134398962 # Number of instructions committed
+system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses
+system.cpu.num_func_calls 1709332 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls
+system.cpu.num_int_insts 115187746 # number of integer instructions
+system.cpu.num_fp_insts 2326977 # number of float instructions
+system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read
+system.cpu.num_int_register_writes 113147734 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
+system.cpu.num_mem_refs 58160248 # number of memory refs
+system.cpu.num_load_insts 37275867 # Number of load instructions
+system.cpu.num_store_insts 20884381 # Number of store instructions
+system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
+system.cpu.num_busy_cycles 136297344.998000 # Number of busy cycles
+system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
+system.cpu.Branches 12719095 # Number of branches fetched
+system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction
+system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction
+system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction
+system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction
+system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction
+system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 136293798 # Class of executed instruction
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=262144
+
+[system.cpu.dtb]
+type=SparcTLB
+eventq_index=0
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=131072
+
+[system.cpu.interrupts]
+type=SparcInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=SparcISA
+eventq_index=0
+
+[system.cpu.itb]
+type=SparcTLB
+eventq_index=0
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=2097152
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex bendian.raw
+cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: ignoring syscall time(4026528248, 4026527848, ...)
+warn: ignoring syscall time(1375098, 4026527400, ...)
+warn: ignoring syscall time(1, 4026527312, ...)
+warn: ignoring syscall time(413, 4026527048, ...)
+warn: ignoring syscall time(414, 4026527048, ...)
+warn: ignoring syscall time(4026527688, 4026527288, ...)
+warn: ignoring syscall time(1375098, 4026526840, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026526960, ...)
+warn: ignoring syscall time(409, 4026527040, ...)
+warn: ignoring syscall time(409, 4026527000, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
+warn: ignoring syscall time(409, 4026526984, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(19045, 4026526312, ...)
+warn: ignoring syscall time(409, 4026526832, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
+warn: ignoring syscall time(409, 4026526840, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
+warn: ignoring syscall time(409, 4026526848, ...)
+warn: ignoring syscall time(409, 4026526936, ...)
+warn: ignoring syscall time(4026527408, 4026527008, ...)
+warn: ignoring syscall time(1375098, 4026526560, ...)
+warn: ignoring syscall time(18732, 4026527184, ...)
+warn: ignoring syscall time(409, 4026526632, ...)
+warn: ignoring syscall time(0, 4026526736, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
+warn: ignoring syscall time(225, 4026527744, ...)
+warn: ignoring syscall time(409, 4026527048, ...)
+warn: ignoring syscall time(409, 4026526856, ...)
+warn: ignoring syscall time(409, 4026526872, ...)
+warn: ignoring syscall time(4026527496, 4026527096, ...)
+warn: ignoring syscall time(1375098, 4026526648, ...)
+warn: ignoring syscall time(0, 4026526824, ...)
+warn: ignoring syscall time(0, 4026527320, ...)
+warn: ignoring syscall time(1879089152, 4026527184, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall times(246, 4026527728, ...)
+warn: ignoring syscall time(1595768, 4026527472, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(0, 4026527472, ...)
+warn: ignoring syscall time(19045, 4026526912, ...)
+warn: ignoring syscall time(17300, 4026526912, ...)
+warn: ignoring syscall time(20500, 4026525968, ...)
+warn: ignoring syscall time(4026526436, 4026525968, ...)
+warn: ignoring syscall time(7004192, 4026526056, ...)
+warn: ignoring syscall time(4, 4026527512, ...)
+warn: ignoring syscall time(0, 4026525760, ...)
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:47:13
+gem5 executing on u200540-lin
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 202242260000 because target called exit()
--- /dev/null
+
+ SYSTEM TYPE...
+ __ZTC__ := False
+ __UNIX__ := True
+ __RISC__ := True
+ SPEC_CPU2000_LP64 := False
+ __MAC__ := False
+ __BCC__ := False
+ __BORLANDC__ := False
+ __GUI__ := False
+ __WTC__ := False
+ __HP__ := False
+
+ CODE OPTIONS...
+ __MACROIZE_HM__ := True
+ __MACROIZE_MEM__ := True
+ ENV01 := True
+ USE_HPP_STYPE_HDRS := False
+ USE_H_STYPE_HDRS := False
+
+ CODE INCLUSION PARAMETERS...
+ INCLUDE_ALL_CODE := False
+ INCLUDE_DELETE_CODE := True
+ __SWAP_GRP_POS__ := True
+ __INCLUDE_MTRX__ := False
+ __BAD_CODE__ := False
+ API_INCLUDE := False
+ BE_CAREFUL := False
+ OLDWAY := False
+ NOTUSED := False
+
+ SYSTEM PARAMETERS...
+ EXT_ENUM := 999999999L
+ CHUNK_CONSTANT := 55555555
+ CORE_CONSTANT := 55555555
+ CORE_LIMIT := 20971520
+ CorePage_Size := 384000
+ ALIGN_BYTES := True
+ CORE_BLOCK_ALIGN := 8
+ FAR_MEM := False
+
+ MEMORY MANAGEMENT PARAMETERS...
+ SYSTEM_ALLOC := True
+ SYSTEM_FREESTORE := True
+ __NO_DISKCACHE__ := False
+ __FREEZE_VCHUNKS__ := True
+ __FREEZE_GRP_PACKETS__ := True
+ __MINIMIZE_TREE_CACHE__:= True
+
+ SYSTEM STD PARAMETERS...
+ __STDOUT__ := False
+ NULL := 0
+ LPTR := False
+ False_Status := 1
+ True_Status := 0
+ LARGE := True
+ TWOBYTE_BOOL := False
+ __NOSTR__ := False
+
+ MEMORY VALIDATION PARAMETERS...
+ CORE_CRC_CHECK := False
+ VALIDATE_MEM_CHUNKS := False
+
+ SYSTEM DEBUG OPTIONS...
+ DEBUG := False
+ MCSTAT := False
+ TRACKBACK := False
+ FLUSH_FILES := False
+ DEBUG_CORE0 := False
+ DEBUG_RISC := False
+ __TREE_BUG__ := False
+ __TRACK_FILE_READS__ := False
+ PAGE_SPACE := False
+ LEAVE_NO_TRACE := True
+ NULL_TRACE_STRS := False
+
+ TIME PARAMETERS...
+ CLOCK_IS_LONG := False
+ __DISPLAY_TIME__ := False
+ __TREE_TIME__ := False
+ __DISPLAY_ERRORS__ := False
+
+ API MACROS...
+ __BMT01__ := True
+ OPTIMIZE := True
+
+ END OF DEFINES.
+
+
+
+ ... IMPLODE MEMORY ...
+
+ SWAP to DiskCache := False
+
+ FREEZE_GRP_PACKETS:= True
+
+ QueBug := 1000
+
+ sizeof(boolean) = 4
+ sizeof(sizetype) = 4
+ sizeof(chunkstruc) = 32
+
+ sizeof(shorttype ) = 2
+ sizeof(idtype ) = 2
+ sizeof(sizetype ) = 4
+ sizeof(indextype ) = 4
+ sizeof(numtype ) = 4
+ sizeof(handletype) = 4
+ sizeof(tokentype ) = 8
+
+ sizeof(short ) = 2
+ sizeof(int ) = 4
+
+ sizeof(lt64 ) = 4
+ sizeof(farlongtype) = 4
+ sizeof(long ) = 4
+ sizeof(longaddr ) = 4
+
+ sizeof(float ) = 4
+ sizeof(double ) = 8
+
+ sizeof(addrtype ) = 4
+ sizeof(char * ) = 4
+ ALLOC CORE_1 :: 8
+ BHOOLE NATH
+
+ OPEN File ./input/bendian.rnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 2030c0
+ DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
+ DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
+ DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+ DB[ 1] LOADED; Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 1b4750
+
+ OPEN File ./input/bendian.wnv
+ *Status = 0
+ DB HDR restored from FileVbn[ 0]
+ DB BlkDirOffset : @ 21c40
+ DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
+ DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
+ DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+ DB[ 2] LOADED; Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+ BE HERE NOW !!!
+
+
+
+ ... VORTEx ON LINE ...
+
+
+ ... END OF SESSION ...
--- /dev/null
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+ MESSAGE FileName: smred.msg
+ OUTPUT FileName: smred.out
+ DISK CACHE FileName: NULL
+ PART DB FileName: parts.db
+ DRAW DB FileName: draw.db
+ PERSON DB FileName: emp.db
+ PERSONS Data FileName: ./input/persons.250
+ PARTS Count : 100
+ OUTER Loops : 1
+ INNER Loops : 1
+ LOOKUP Parts : 25
+ DELETE Parts : 10
+ STUFF Parts : 10
+ DEPTH Traverse: 5
+ % DECREASE Parts : 0
+ % INCREASE LookUps : 0
+ % INCREASE Deletes : 0
+ % INCREASE Stuffs : 0
+ FREEZE_PACKETS : 1
+ ALLOC_CHUNKS : 10000
+ EXTEND_CHUNKS : 5000
+ DELETE Draw objects : True
+ DELETE Part objects : False
+ QUE_BUG : 1000
+ VOID_BOUNDARY : 67108864
+ VOID_RESERVE : 1048576
+
+ COMMIT_DBS : False
+
+
+
+ BMT TEST :: files...
+ EdbName := PartLib
+ EdbFileName := parts.db
+ DrwName := DrawLib
+ DrwFileName := draw.db
+ EmpName := PersonLib
+ EmpFileName := emp.db
+
+ Swap to DiskCache := False
+ Freeze the cache := True
+
+
+ BMT TEST :: parms...
+ DeBug modulo := 1000
+ Create Parts count:= 100
+ Outer Loops := 1
+ Inner Loops := 1
+ Look Ups := 25
+ Delete Parts := 10
+ Stuff Parts := 10
+ Traverse Limit := 5
+ Delete Draws := True
+ Delete Parts := False
+ Delete ALL Parts := after every <mod 0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 4] Created.
+ PartLibCreate:: Db[ 4]; VpartsDir= 1
+
+ Part Count= 1
+
+ Initialize the Class maps
+ LIST HEADS loaded ... DbListHead_Class = 207
+ DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 5] Created.
+ DrawLibCreate:: Db[ 5]; VpartsDir= 1
+
+ Initialize the Class maps of this schema.
+ Primal_CreateDb Accessed !!!
+ CREATE Db Header and Db Primal ...
+ NEW DB [ 6] Created.
+
+ ***NOTE*** Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
+
+ LAST Person Read::
+ ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
+
+ BUILD <Query0> for <Part2> class::
+
+ if (link[1].length >= 5) ::
+
+ Build Query2 for <Address> class::
+
+ if (State == CA || State == T*)
+
+ Build Query1 for <Person> class::
+
+ if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj> class::
+
+ if (Id >= 3000
+ && (Id >= 3000 && Id <= 3001)
+ && Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj> class::
+
+ if (Nam == Pre*
+ || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
+ || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
+ && Id <= 7)
+ SEED := 1008; Swap = False; RgnEntries = 135
+
+ OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part 1. Token[ 4: 2].
+
+ < 100> Parts Created. CurrentId= 100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part 1. Token[ 4: 2]
+ Connect Part 25. Token[ 4: 26] FromList= 26.
+ Connect Part 12. Token[ 4: 13] FromList= 13.
+ Connect Part 59. Token[ 4: 60] FromList= 60.
+
+ SET <DrawObjs> entries::
+ 1. [ 5: 5] := <1 >; @[: 6]
+ Iteration count = 100
+
+ SET <NamedDrawObjs> entries::
+ 1. [ 5: 39] := <14 >;
+ Iteration count = 12
+
+ SET <LibRectangles> entries::
+ 1. [ 5: 23] := <8 >; @[: 24]
+ Iteration count = 12
+
+ LIST <DbRectangles> entries::
+ 1. [ 5: 23]
+ Iteration count = 12
+
+ SET <PersonNames > entries::
+ Iteration count = 250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ < 100> Part images' Committed.
+ < 0> are Named.
+ < 50> Point images' Committed.
+ < 81> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. TestObj Committed.
+ < 0> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
+ < 0> CartesianPoint images' Committed.
+
+ BEGIN Inner Loop Sequence::.
+
+ INNER LOOP [ 1: 1] :
+
+ LOOK UP 25 Random Parts and Export each Part.
+
+ LookUp for 26 parts; Asserts = 8
+ <Part2 > Asserts = 2; NULL Asserts = 3.
+ <DrawObj > Asserts = 0; NULL Asserts = 5.
+ <NamedObj > Asserts = 0; NULL Asserts = 0.
+ <Person > Asserts = 0; NULL Asserts = 5.
+ <TestObj > Asserts = 60; NULL Asserts = 0.
+
+ DELETE 10 Random Parts.
+
+ PartDelete :: Token[ 4: 91].
+ PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
+ DisConnect link [ 0]:= 50; PartToken[ 51: 51].
+ DisConnect link [ 1]:= 17; PartToken[ 18: 18].
+ DisConnect link [ 2]:= 72; PartToken[ 73: 73].
+ DeleteFromList:: Vchunk[ 4: 91]. (* 1)
+ DisConnect FromList[ 0]:= 56; Token[ 57: 57].
+ Vlists[ 89] := 100;
+
+ Delete for 11 parts;
+
+ Traverse Count= 0
+
+ TRAVERSE PartId[ 6] and all Connections to 5 Levels
+ SEED In Traverse Part [ 4: 65] @ Level = 4.
+
+ Traverse Count= 357
+ Traverse Asserts = 5. True Tests = 1
+ < 5> DrawObj objects DELETED.
+ < 2> are Named.
+ < 2> Point objects DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part 101. Token[ 4: 102].
+
+ < 10> Parts Created. CurrentId= 110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ < 81> Part images' Committed.
+ < 0> are Named.
+ < 38> Point images' Committed.
+ < 31> Person images' Committed.
+
+ COMMIT Parts(* 100)
+
+ Commit TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Committed.
+ < 15> TestObj images' Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
+ < 16> CartesianPoint images' Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 4]. TestObj Deleted.
+ < 15> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
+ < 16> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+
+ END INNER LOOP [ 1: 1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class in <Primal> DB.
+ < 0> TestObj objects Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ < 0> CartesianPoint objects Deleted.
+
+ DELETE TestObj and Point objects...
+ STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.202242 # Number of seconds simulated
+sim_ticks 202242028500 # Number of ticks simulated
+final_tick 202242028500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1201078 # Simulator instruction rate (inst/s)
+host_op_rate 1216630 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1807368744 # Simulator tick rate (ticks/s)
+host_mem_usage 300888 # Number of bytes of host memory used
+host_seconds 111.90 # Real time elapsed on the host
+sim_insts 134398962 # Number of instructions simulated
+sim_ops 136139190 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 7826624 # Number of bytes read from this memory
+system.physmem.bytes_read::total 8418112 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 591488 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 591488 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5303552 # Number of bytes written to this memory
+system.physmem.bytes_written::total 5303552 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 9242 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 122291 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 131533 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 82868 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 82868 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2924654 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 38699295 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 41623950 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2924654 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2924654 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 26223788 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 26223788 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 26223788 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2924654 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 38699295 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 67847737 # Total bandwidth to/from this memory (bytes/s)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.workload.num_syscalls 1946 # Number of system calls
+system.cpu.numCycles 404484057 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 134398962 # Number of instructions committed
+system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses
+system.cpu.num_func_calls 1709332 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls
+system.cpu.num_int_insts 115187746 # number of integer instructions
+system.cpu.num_fp_insts 2326977 # number of float instructions
+system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read
+system.cpu.num_int_register_writes 113147733 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
+system.cpu.num_mem_refs 58160248 # number of memory refs
+system.cpu.num_load_insts 37275867 # Number of load instructions
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+system.cpu.num_busy_cycles 404484056.998000 # Number of busy cycles
+system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
+system.cpu.Branches 12719095 # Number of branches fetched
+system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction
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+system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction
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+system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction
+system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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+system.cpu.op_class::total 136293798 # Class of executed instruction
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+system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks.
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+system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
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+system.cpu.dcache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 3530 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses
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+system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses
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+system.cpu.dcache.overall_misses::total 150663 # number of overall misses
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+system.cpu.dcache.overall_avg_miss_latency::total 47089.690236 # average overall miss latency
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+system.cpu.icache.tags.tagsinuse 2004.815289 # Cycle average of tags in use
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency
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+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses
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+system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2539025500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 2539025500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2539025500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 2539025500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2539025500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 2539025500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13575.934105 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13575.934105 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13575.934105 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13575.934105 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13575.934105 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13575.934105 # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.tags.replacements 98540 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 30850.758845 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 26245.549112 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.945467 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264265 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.941490 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 30994 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 533 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12212 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17536 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 585 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945862 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 3928089 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 3928089 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 177782 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 24464 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 202246 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 123970 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 123970 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 3923 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 3923 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 177782 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 28387 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 206169 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 177782 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 28387 # number of overall hits
+system.cpu.l2cache.overall_hits::total 206169 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 9242 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 21035 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 30277 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 101256 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 101256 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 9242 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 122291 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 131533 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 9242 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 122291 # number of overall misses
+system.cpu.l2cache.overall_misses::total 131533 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 485290500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1104380500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1589671000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5315940000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 5315940000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 485290500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 6420320500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 6905611000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 485290500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 6420320500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 6905611000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 123970 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 123970 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 150678 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 337702 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.049416 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.462318 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.130211 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962702 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.962702 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.049416 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.811605 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.389494 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.049416 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.811605 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.389494 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52509.251244 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52502.044212 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52504.244146 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52509.251244 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.351620 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52500.976941 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52509.251244 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.351620 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52500.976941 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks 82868 # number of writebacks
+system.cpu.l2cache.writebacks::total 82868 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9242 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21035 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 30277 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101256 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 101256 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 9242 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 122291 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 131533 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 9242 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 122291 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 131533 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 374386000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 851960500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1226346500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4100868000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4100868000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 374386000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4952828500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 5327214500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 374386000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4952828500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 5327214500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.462318 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.130211 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962702 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962702 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.389494 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.389494 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40509.197143 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40502.044212 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40504.227632 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40509.197143 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.351620 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.973140 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40509.197143 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.351620 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.973140 # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374048 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 425326 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 799374 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17577472 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 461672 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 461672 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 461672 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 30277 # Transaction distribution
+system.membus.trans_dist::ReadResp 30277 # Transaction distribution
+system.membus.trans_dist::Writeback 82868 # Transaction distribution
+system.membus.trans_dist::ReadExReq 101256 # Transaction distribution
+system.membus.trans_dist::ReadExResp 101256 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 214401 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 214401 # Request fanout histogram
+system.membus.reqLayer0.occupancy 558284500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
+system.membus.respLayer1.occupancy 657665500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
+
+---------- End Simulation Statistics ----------
--- /dev/null
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Korey Sewell
+
+m5.util.addToPath('../configs/common')
+from cpu2000 import vortex
+
+workload = vortex(isa, opsys, 'smred')
+root.system.cpu[0].workload = workload.makeLiveProcess()
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=atomic
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+eventq_index=0
+size=64
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=AlphaISA
+eventq_index=0
+system=system
+
+[system.cpu.itb]
+type=AlphaTLB
+eventq_index=0
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(1, ...)
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 19:22:57
+gem5 executing on u200540-lin
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sav
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 Exiting @ tick 45951567500 because target called exit()
--- /dev/null
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84 block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0 MISSING_ROWS:-46
+
+bdxlen:86 bdylen:78
+l:0 t:78 r:86 b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+ tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
+ tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
+ tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
+ tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
+
+ I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
+ 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
+ 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
+ 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46
+ 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
+ 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
+ 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
+ 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
+ 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
+ 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
+ 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
+ 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
+ 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
+ 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
+ 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
+ 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
+ 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
+ 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
+ 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
+ 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
+ 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
+ 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
+ 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
+ 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
+ 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
+ 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
+ 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
+ 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
+ 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
+ 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
+ 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
+ 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
+ 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
+ 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
+ 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
+ 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
+ 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
+ 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
+ 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
+ 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
+ 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48
+ 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
+ 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
+ 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
+ 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
+ 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
+ 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
+ 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
+ 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
+ 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
+ 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
+ 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
+ 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
+ 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
+ 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
+ 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
+ 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
+ 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
+ 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
+ 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
+ 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
+ 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
+ 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
+ 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
+ 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
+ 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
+ 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
+ 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
+ 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
+ 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
+ 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
+ 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
+ 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
+ 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
+ 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
+ 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
+ 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
+ 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
+ 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
+ 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
+ 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
+ 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
+ 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
+ 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
+ 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
+ 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
+ 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
+ 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
+ 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
+ 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
+ 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
+ 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
+ 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
+ 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
+ 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
+ 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
+ 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
+ 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
+ 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
+ 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
+100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
+101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
+102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
+103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
+104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
+105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
+106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
+107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
+108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
+109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
+110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
+111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
+112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
+113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
+114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
+115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
+116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
+117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
+118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
+119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
+120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
+121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
+
+Initial Wiring Cost: 645 Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645 Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216 Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429 Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 82 -20
+ 2 86 -16
+
+LONGEST Block is:2 Its length is:86
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 86 -16
+ 2 86 -16
+
+LONGEST Block is:1 Its length is:86
+Added: 1 feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl: 1.650
+finalRowControl: 0.300
+iter T Wire accept
+ 122 0.001 976 16%
+ 123 0.001 971 0%
+ 124 0.001 971 0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL: 1 is: 0
+MAX OF CHANNEL: 2 is: 4
+MAX OF CHANNEL: 3 is: 1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0
+Number of Nets: 15
+Number of Pins: 46
+Usage statistics not available
--- /dev/null
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
--- /dev/null
+$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
+$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
+ACOUNT_1 14 0 18 26 2 1
+twfeed1 18 0 22 26 0 1
+$COUNT_1/$FJK3_1 22 0 86 26 0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
+$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
+$COUNT_1/$FJK3_2 22 52 86 78 0 2
--- /dev/null
+1 0 0 86 26 0 0
+2 0 52 86 78 0 0
--- /dev/null
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
--- /dev/null
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
--- /dev/null
+net 1
+segment channel 2
+ pin1 1 pin2 7 0 0
+net 2
+segment channel 3
+pin1 41 pin2 42 0 0
+segment channel 2
+pin1 12 pin2 3 0 0
+net 3
+segment channel 2
+pin1 35 pin2 36 0 0
+segment channel 2
+pin1 19 pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5 pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14 pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23 pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25 pin2 31 0 0
+net 14
+net 15
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.045952 # Number of seconds simulated
+sim_ticks 45951567500 # Number of ticks simulated
+final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 2845952 # Simulator instruction rate (inst/s)
+host_op_rate 2845951 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1422976169 # Simulator tick rate (ticks/s)
+host_mem_usage 283520 # Number of bytes of host memory used
+host_seconds 32.29 # Real time elapsed on the host
+sim_insts 91903056 # Number of instructions simulated
+sim_ops 91903056 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 108337521 # Number of bytes read from this memory
+system.physmem.bytes_read::total 475949877 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 367612356 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 367612356 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data 30920974 # Number of bytes written to this memory
+system.physmem.bytes_written::total 30920974 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 91903089 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 19996198 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 111899287 # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data 6501103 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 6501103 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 7999995996 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2357645819 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 10357641815 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7999995996 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7999995996 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 672903574 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 672903574 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 111899287 # Transaction distribution
+system.membus.trans_dist::ReadResp 111899287 # Transaction distribution
+system.membus.trans_dist::WriteReq 6501103 # Transaction distribution
+system.membus.trans_dist::WriteResp 6501103 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 183806178 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 52994602 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 236800780 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 367612356 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 139258495 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 506870851 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 118400390 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.776206 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.416786 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 26497301 22.38% 22.38% # Request fanout histogram
+system.membus.snoop_fanout::1 91903089 77.62% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 118400390 # Request fanout histogram
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 19996198 # DTB read hits
+system.cpu.dtb.read_misses 10 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 19996208 # DTB read accesses
+system.cpu.dtb.write_hits 6501103 # DTB write hits
+system.cpu.dtb.write_misses 23 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 6501126 # DTB write accesses
+system.cpu.dtb.data_hits 26497301 # DTB hits
+system.cpu.dtb.data_misses 33 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 26497334 # DTB accesses
+system.cpu.itb.fetch_hits 91903089 # ITB hits
+system.cpu.itb.fetch_misses 47 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 91903136 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 389 # Number of system calls
+system.cpu.numCycles 91903136 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 91903056 # Number of instructions committed
+system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
+system.cpu.num_func_calls 2059216 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
+system.cpu.num_int_insts 79581109 # number of integer instructions
+system.cpu.num_fp_insts 6862064 # number of float instructions
+system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
+system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
+system.cpu.num_mem_refs 26497334 # number of memory refs
+system.cpu.num_load_insts 19996208 # Number of load instructions
+system.cpu.num_store_insts 6501126 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 91903136 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.Branches 10240685 # Number of branches fetched
+system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction
+system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction
+system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction
+system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction
+system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction
+system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction
+system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction
+system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 91903089 # Class of executed instruction
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=262144
+
+[system.cpu.dtb]
+type=AlphaTLB
+eventq_index=0
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=131072
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=AlphaISA
+eventq_index=0
+system=system
+
+[system.cpu.itb]
+type=AlphaTLB
+eventq_index=0
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=2097152
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
+drivers=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+gid=100
+input=cin
+kvmInSE=false
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+warn: ignoring syscall sigprocmask(1, ...)
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 19:23:43
+gem5 executing on u200540-lin
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 Exiting @ tick 118729316000 because target called exit()
--- /dev/null
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84 block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0 MISSING_ROWS:-46
+
+bdxlen:86 bdylen:78
+l:0 t:78 r:86 b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+ tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
+ tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
+ tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
+ tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
+
+ I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
+ 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
+ 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
+ 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46
+ 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
+ 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
+ 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
+ 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
+ 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
+ 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
+ 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
+ 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
+ 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
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+ 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
+ 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
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+ 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
+ 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
+ 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
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+ 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
+ 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
+ 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
+ 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
+ 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
+ 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
+ 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
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+ 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
+ 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
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+ 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
+ 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
+ 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
+ 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
+ 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48
+ 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
+ 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
+ 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
+ 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
+ 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
+ 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
+ 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
+ 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
+ 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
+ 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
+ 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
+ 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
+ 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
+ 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
+ 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
+ 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
+ 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
+ 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
+ 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
+ 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
+ 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
+ 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
+ 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
+ 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
+ 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
+ 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
+ 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
+ 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
+ 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
+ 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
+ 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
+ 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
+ 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
+ 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
+ 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
+ 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
+ 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
+ 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
+ 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
+ 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
+ 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
+ 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
+ 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
+ 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
+ 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
+ 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
+ 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
+ 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
+ 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
+ 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
+ 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
+ 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
+ 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
+ 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
+ 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
+ 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
+ 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
+ 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
+ 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
+100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
+101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
+102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
+103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
+104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
+105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
+106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
+107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
+108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
+109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
+110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
+111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
+112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
+113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
+114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
+115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
+116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
+117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
+118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
+119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
+120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
+121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
+
+Initial Wiring Cost: 645 Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645 Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216 Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429 Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 82 -20
+ 2 86 -16
+
+LONGEST Block is:2 Its length is:86
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 86 -16
+ 2 86 -16
+
+LONGEST Block is:1 Its length is:86
+Added: 1 feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl: 1.650
+finalRowControl: 0.300
+iter T Wire accept
+ 122 0.001 976 16%
+ 123 0.001 971 0%
+ 124 0.001 971 0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL: 1 is: 0
+MAX OF CHANNEL: 2 is: 4
+MAX OF CHANNEL: 3 is: 1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0
+Number of Nets: 15
+Number of Pins: 46
+Usage statistics not available
--- /dev/null
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
--- /dev/null
+$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
+$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
+ACOUNT_1 14 0 18 26 2 1
+twfeed1 18 0 22 26 0 1
+$COUNT_1/$FJK3_1 22 0 86 26 0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
+$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
+$COUNT_1/$FJK3_2 22 52 86 78 0 2
--- /dev/null
+1 0 0 86 26 0 0
+2 0 52 86 78 0 0
--- /dev/null
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
--- /dev/null
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
--- /dev/null
+net 1
+segment channel 2
+ pin1 1 pin2 7 0 0
+net 2
+segment channel 3
+pin1 41 pin2 42 0 0
+segment channel 2
+pin1 12 pin2 3 0 0
+net 3
+segment channel 2
+pin1 35 pin2 36 0 0
+segment channel 2
+pin1 19 pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5 pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14 pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23 pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25 pin2 31 0 0
+net 14
+net 15
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.118729 # Number of seconds simulated
+sim_ticks 118729316500 # Number of ticks simulated
+final_tick 118729316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1507080 # Simulator instruction rate (inst/s)
+host_op_rate 1507080 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1946992285 # Simulator tick rate (ticks/s)
+host_mem_usage 297820 # Number of bytes of host memory used
+host_seconds 60.98 # Real time elapsed on the host
+sim_insts 91903056 # Number of instructions simulated
+sim_ops 91903056 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory
+system.physmem.bytes_read::total 304960 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 167744 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 167744 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1412827 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1155704 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2568532 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1412827 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1412827 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 19996198 # DTB read hits
+system.cpu.dtb.read_misses 10 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 19996208 # DTB read accesses
+system.cpu.dtb.write_hits 6501103 # DTB write hits
+system.cpu.dtb.write_misses 23 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 6501126 # DTB write accesses
+system.cpu.dtb.data_hits 26497301 # DTB hits
+system.cpu.dtb.data_misses 33 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 26497334 # DTB accesses
+system.cpu.itb.fetch_hits 91903090 # ITB hits
+system.cpu.itb.fetch_misses 47 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 91903137 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 389 # Number of system calls
+system.cpu.numCycles 237458633 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 91903056 # Number of instructions committed
+system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
+system.cpu.num_func_calls 2059216 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
+system.cpu.num_int_insts 79581109 # number of integer instructions
+system.cpu.num_fp_insts 6862064 # number of float instructions
+system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
+system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
+system.cpu.num_mem_refs 26497334 # number of memory refs
+system.cpu.num_load_insts 19996208 # Number of load instructions
+system.cpu.num_store_insts 6501126 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 237458633 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.Branches 10240685 # Number of branches fetched
+system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction
+system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction
+system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction
+system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction
+system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction
+system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction
+system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction
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+system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 8510 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 10733 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 8510 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.338676 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.443958 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.190767 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.164312 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52500.104932 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52500.104932 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2621 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 3043 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2621 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 4765 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106150500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17091000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 123241500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69741000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69741000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106150500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86832000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 192982500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106150500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86832000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 192982500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.338676 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17020 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 21573 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 544640 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 10840 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 10840 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 10840 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 3043 # Transaction distribution
+system.membus.trans_dist::ReadResp 3043 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 4765 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 4765 # Request fanout histogram
+system.membus.reqLayer0.occupancy 4765500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 23825500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=atomic
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
+dtb=system.cpu.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.membus.slave[6]
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.membus.slave[4]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.membus.slave[5]
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.membus.slave[3]
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2014 12:08:08
+gem5 started Jan 23 2014 18:37:39
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+ 0: system.cpu.isa: ISA system set to: 0 0x5fbc6c0
+info: Entering event queue @ 0. Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+info: Increasing stack size by one page.
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 Exiting @ tick 103106766000 because target called exit()
--- /dev/null
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84 block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0 MISSING_ROWS:-46
+
+bdxlen:86 bdylen:78
+l:0 t:78 r:86 b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+ tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
+ tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
+ tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
+ tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
+
+ I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
+ 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
+ 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
+ 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
+ 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
+ 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
+ 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
+ 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
+ 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
+ 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
+ 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
+ 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
+ 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
+ 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
+ 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
+ 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
+ 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
+ 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
+ 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
+ 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
+ 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
+ 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
+ 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
+ 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
+ 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
+ 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
+ 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
+ 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
+ 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
+ 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
+ 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
+ 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
+ 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
+ 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
+ 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
+ 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
+ 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
+ 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
+ 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
+ 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
+ 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
+ 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
+ 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
+ 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
+ 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
+ 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
+ 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
+ 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
+ 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
+ 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
+ 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
+ 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
+ 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
+ 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
+ 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
+ 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
+ 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
+ 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
+ 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
+ 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
+ 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
+ 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
+ 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
+ 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
+ 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
+ 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
+ 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
+ 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
+ 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
+ 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
+ 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
+ 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
+ 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
+ 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
+ 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
+ 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
+ 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
+ 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
+ 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
+ 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
+ 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
+ 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
+ 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
+ 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
+ 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
+ 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
+ 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
+ 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
+ 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
+ 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
+ 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
+ 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
+ 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
+ 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
+ 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
+ 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
+ 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
+ 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
+ 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
+ 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
+100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
+101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
+102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
+103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
+104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
+105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
+106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
+107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
+108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
+109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
+110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
+111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
+112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
+113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
+114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
+115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
+116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
+117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
+118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
+119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
+120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
+121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
+
+Initial Wiring Cost: 645 Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645 Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216 Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429 Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 82 -20
+ 2 86 -16
+
+LONGEST Block is:2 Its length is:86
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 86 -16
+ 2 86 -16
+
+LONGEST Block is:1 Its length is:86
+Added: 1 feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl: 1.650
+finalRowControl: 0.300
+iter T Wire accept
+ 122 0.001 976 16%
+ 123 0.001 971 0%
+ 124 0.001 971 0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL: 1 is: 0
+MAX OF CHANNEL: 2 is: 4
+MAX OF CHANNEL: 3 is: 1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0
+Number of Nets: 15
+Number of Pins: 46
+Usage statistics not available
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.099596 # Number of seconds simulated
+sim_ticks 99596491000 # Number of ticks simulated
+final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1940320 # Simulator instruction rate (inst/s)
+host_op_rate 2045410 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1121471108 # Simulator tick rate (ticks/s)
+host_mem_usage 304628 # Number of bytes of host memory used
+host_seconds 88.81 # Real time elapsed on the host
+sim_insts 172317409 # Number of instructions simulated
+sim_ops 181650341 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory
+system.physmem.bytes_read::total 869973865 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 759440204 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 759440204 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory
+system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 189860051 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 27777721 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 217637772 # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 7625170288 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1109814813 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 8734985101 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7625170288 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7625170288 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 454362795 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 454362795 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7625170288 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1564177607 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 9189347896 # Total bandwidth to/from this memory (bytes/s)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.walks 0 # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.walks 0 # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.numCycles 199192983 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 172317409 # Number of instructions committed
+system.cpu.committedOps 181650341 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
+system.cpu.num_func_calls 3545028 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls
+system.cpu.num_int_insts 143085668 # number of integer instructions
+system.cpu.num_fp_insts 1752310 # number of float instructions
+system.cpu.num_int_register_reads 241970171 # number of times the integer registers were read
+system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
+system.cpu.num_cc_register_reads 543309967 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written
+system.cpu.num_mem_refs 40540779 # number of memory refs
+system.cpu.num_load_insts 27896144 # Number of load instructions
+system.cpu.num_store_insts 12644635 # Number of store instructions
+system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
+system.cpu.num_busy_cycles 199192982.998000 # Number of busy cycles
+system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
+system.cpu.Branches 40300311 # Number of branches fetched
+system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction
+system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction
+system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction
+system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 181650742 # Class of executed instruction
+system.membus.trans_dist::ReadReq 217614902 # Transaction distribution
+system.membus.trans_dist::ReadResp 217637309 # Transaction distribution
+system.membus.trans_dist::WriteReq 12364287 # Transaction distribution
+system.membus.trans_dist::WriteResp 12364287 # Transaction distribution
+system.membus.trans_dist::SoftPFReq 463 # Transaction distribution
+system.membus.trans_dist::SoftPFResp 463 # Transaction distribution
+system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution
+system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution
+system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720102 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 460048932 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440204 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 230024466 # Request fanout histogram
+system.membus.snoop_fanout::mean 2.825391 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 40164415 17.46% 17.46% # Request fanout histogram
+system.membus.snoop_fanout::3 189860051 82.54% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 2 # Request fanout histogram
+system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::total 230024466 # Request fanout histogram
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dstage2_mmu=system.cpu.dstage2_mmu
+dtb=system.cpu.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+istage2_mmu=system.cpu.istage2_mmu
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=262144
+
+[system.cpu.dstage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+tlb=system.cpu.dtb
+
+[system.cpu.dstage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.dstage2_mmu.stage2_tlb.walker
+
+[system.cpu.dstage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[5]
+
+[system.cpu.dtb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[3]
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=131072
+
+[system.cpu.interrupts]
+type=ArmInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=ArmISA
+eventq_index=0
+fpsid=1090793632
+id_aa64afr0_el1=0
+id_aa64afr1_el1=0
+id_aa64dfr0_el1=1052678
+id_aa64dfr1_el1=0
+id_aa64isar0_el1=0
+id_aa64isar1_el1=0
+id_aa64mmfr0_el1=15728642
+id_aa64mmfr1_el1=0
+id_aa64pfr0_el1=17
+id_aa64pfr1_el1=0
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=270536963
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=34611729
+id_pfr0=49
+id_pfr1=4113
+midr=1091551472
+system=system
+
+[system.cpu.istage2_mmu]
+type=ArmStage2MMU
+children=stage2_tlb
+eventq_index=0
+stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+tlb=system.cpu.itb
+
+[system.cpu.istage2_mmu.stage2_tlb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=true
+size=32
+walker=system.cpu.istage2_mmu.stage2_tlb.walker
+
+[system.cpu.istage2_mmu.stage2_tlb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=true
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[4]
+
+[system.cpu.itb]
+type=ArmTLB
+children=walker
+eventq_index=0
+is_stage2=false
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+is_stage2=false
+num_squash_per_cycle=2
+sys=system
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=2097152
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2014 12:08:08
+gem5 started Jan 23 2014 18:39:21
+gem5 executing on u200540-lin
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+ 0: system.cpu.isa: ISA system set to: 0 0x5d0ed00
+info: Entering event queue @ 0. Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+info: Increasing stack size by one page.
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 Exiting @ tick 232072304000 because target called exit()
--- /dev/null
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84 block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0 MISSING_ROWS:-46
+
+bdxlen:86 bdylen:78
+l:0 t:78 r:86 b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+ tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
+ tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
+ tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
+ tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
+
+ I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
+ 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
+ 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
+ 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
+ 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
+ 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
+ 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
+ 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
+ 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
+ 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
+ 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
+ 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
+ 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
+ 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
+ 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
+ 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
+ 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
+ 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
+ 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
+ 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
+ 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
+ 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
+ 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
+ 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
+ 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
+ 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
+ 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
+ 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
+ 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
+ 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
+ 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
+ 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
+ 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
+ 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
+ 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
+ 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
+ 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
+ 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
+ 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
+ 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
+ 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
+ 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
+ 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
+ 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
+ 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
+ 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
+ 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
+ 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
+ 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
+ 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
+ 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
+ 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
+ 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
+ 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
+ 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
+ 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
+ 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
+ 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
+ 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
+ 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
+ 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
+ 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
+ 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
+ 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
+ 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
+ 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
+ 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
+ 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
+ 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
+ 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
+ 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
+ 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
+ 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
+ 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
+ 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
+ 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
+ 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
+ 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
+ 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
+ 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
+ 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
+ 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
+ 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
+ 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
+ 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
+ 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
+ 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
+ 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
+ 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
+ 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
+ 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
+ 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
+ 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
+ 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
+ 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
+ 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
+ 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
+ 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
+ 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
+ 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
+100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
+101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
+102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
+103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
+104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
+105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
+106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
+107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
+108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
+109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
+110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
+111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
+112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
+113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
+114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
+115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
+116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
+117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
+118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
+119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
+120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
+121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
+
+Initial Wiring Cost: 645 Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645 Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216 Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429 Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 82 -20
+ 2 86 -16
+
+LONGEST Block is:2 Its length is:86
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 86 -16
+ 2 86 -16
+
+LONGEST Block is:1 Its length is:86
+Added: 1 feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl: 1.650
+finalRowControl: 0.300
+iter T Wire accept
+ 122 0.001 976 16%
+ 123 0.001 971 0%
+ 124 0.001 971 0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL: 1 is: 0
+MAX OF CHANNEL: 2 is: 4
+MAX OF CHANNEL: 3 is: 1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0
+Number of Nets: 15
+Number of Pins: 46
+Usage statistics not available
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.230173 # Number of seconds simulated
+sim_ticks 230173357500 # Number of ticks simulated
+final_tick 230173357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1098511 # Simulator instruction rate (inst/s)
+host_op_rate 1158108 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1471393960 # Simulator tick rate (ticks/s)
+host_mem_usage 313104 # Number of bytes of host memory used
+host_seconds 156.43 # Real time elapsed on the host
+sim_insts 171842483 # Number of instructions simulated
+sim_ops 181165370 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory
+system.physmem.bytes_read::total 220992 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 480751 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 479360 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 960111 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 480751 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 480751 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.walks 0 # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.walks 0 # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.numCycles 460346715 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 171842483 # Number of instructions committed
+system.cpu.committedOps 181165370 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
+system.cpu.num_func_calls 3545028 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls
+system.cpu.num_int_insts 143085668 # number of integer instructions
+system.cpu.num_fp_insts 1752310 # number of float instructions
+system.cpu.num_int_register_reads 242291225 # number of times the integer registers were read
+system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
+system.cpu.num_cc_register_reads 626384527 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written
+system.cpu.num_mem_refs 40540779 # number of memory refs
+system.cpu.num_load_insts 27896144 # Number of load instructions
+system.cpu.num_store_insts 12644635 # Number of store instructions
+system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
+system.cpu.num_busy_cycles 460346714.998000 # Number of busy cycles
+system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
+system.cpu.Branches 40300311 # Number of branches fetched
+system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction
+system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction
+system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction
+system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 181650742 # Class of executed instruction
+system.cpu.dcache.tags.replacements 40 # number of replacements
+system.cpu.dcache.tags.tagsinuse 1363.619277 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619277 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits
+system.cpu.dcache.overall_hits::total 40117812 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
+system.cpu.dcache.overall_misses::total 1789 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
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+system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
+system.cpu.dcache.writebacks::total 16 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses
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+system.cpu.dcache.ReadReq_mshr_miss_latency::total 34437000 # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92981500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 92981500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93035000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 93035000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50053.779070 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50053.779070 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53222.272727 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53222.272727 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52003.076063 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52003.076063 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52003.912800 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52003.912800 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements 1506 # number of replacements
+system.cpu.icache.tags.tagsinuse 1147.992598 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992598 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 379723155 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 379723155 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::cpu.inst 189857001 # number of overall hits
+system.cpu.icache.overall_hits::total 189857001 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses
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+system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses
+system.cpu.icache.overall_misses::total 3051 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 112371000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 112371000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 112371000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 189860052 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 189860052 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 189860052 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.875123 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 36830.875123 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 36830.875123 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.icache.fast_writes 0 # number of fast writes performed
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+system.cpu.icache.overall_mshr_miss_latency::total 107794500 # number of overall MSHR miss cycles
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+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
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+system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.tags.replacements 0 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 1675.663349 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036753 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588818 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 42317 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 42317 # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
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+system.cpu.l2cache.overall_hits::cpu.inst 1322 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 65 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1387 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 1729 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses
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+system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses
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+system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses)
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+system.cpu.l2cache.overall_accesses::cpu.data 1789 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.917271 # miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadExReq_miss_rate::total 0.992727 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52552.053210 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52536.392405 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52547.861076 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52527.930403 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52527.930403 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52541.558065 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52541.558065 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1729 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 632 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 2361 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70024500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25596000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 95620500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44226000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44226000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70024500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 69822000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 139846500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70024500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 69822000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 139846500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6102 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3594 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 9696 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 4856 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 2361 # Transaction distribution
+system.membus.trans_dist::ReadResp 2361 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1092 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1092 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 3453 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 3453 # Request fanout histogram
+system.membus.reqLayer0.occupancy 3596500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 17408500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=atomic
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.dtb]
+type=SparcTLB
+eventq_index=0
+size=64
+
+[system.cpu.interrupts]
+type=SparcInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=SparcISA
+eventq_index=0
+
+[system.cpu.itb]
+type=SparcTLB
+eventq_index=0
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:48:57
+gem5 executing on u200540-lin
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
+Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav
+Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+info: Increasing stack size by one page.
+122 123 124 Exiting @ tick 96722945000 because target called exit()
--- /dev/null
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84 block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0 MISSING_ROWS:-46
+
+bdxlen:86 bdylen:78
+l:0 t:78 r:86 b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+ tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
+ tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
+ tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
+ tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
+
+ I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
+ 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
+ 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
+ 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
+ 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
+ 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
+ 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
+ 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
+ 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
+ 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
+ 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
+ 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
+ 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
+ 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
+ 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
+ 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
+ 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
+ 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
+ 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
+ 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
+ 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
+ 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
+ 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
+ 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
+ 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
+ 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
+ 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
+ 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
+ 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
+ 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
+ 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
+ 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
+ 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
+ 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
+ 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
+ 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
+ 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
+ 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
+ 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
+ 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
+ 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
+ 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
+ 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
+ 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
+ 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
+ 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
+ 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
+ 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
+ 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
+ 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
+ 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
+ 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
+ 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
+ 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
+ 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
+ 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
+ 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
+ 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
+ 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
+ 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
+ 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
+ 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
+ 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
+ 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
+ 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
+ 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
+ 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
+ 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
+ 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
+ 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
+ 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
+ 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
+ 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
+ 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
+ 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
+ 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
+ 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
+ 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
+ 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
+ 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
+ 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
+ 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
+ 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
+ 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
+ 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
+ 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
+ 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
+ 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
+ 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
+ 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
+ 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
+ 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
+ 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
+ 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
+ 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
+ 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
+ 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
+ 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
+ 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
+ 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
+100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
+101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
+102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
+103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
+104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
+105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
+106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
+107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
+108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
+109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
+110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
+111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
+112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
+113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
+114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
+115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
+116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
+117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
+118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
+119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
+120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
+121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
+
+Initial Wiring Cost: 645 Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645 Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216 Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429 Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 82 -20
+ 2 86 -16
+
+LONGEST Block is:2 Its length is:86
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 86 -16
+ 2 86 -16
+
+LONGEST Block is:1 Its length is:86
+Added: 1 feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl: 1.650
+finalRowControl: 0.300
+iter T Wire accept
+ 122 0.001 976 16%
+ 123 0.001 971 0%
+ 124 0.001 971 0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL: 1 is: 0
+MAX OF CHANNEL: 2 is: 4
+MAX OF CHANNEL: 3 is: 1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0
+Number of Nets: 15
+Number of Pins: 46
+Usage statistics not available
--- /dev/null
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
--- /dev/null
+$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
+$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
+ACOUNT_1 14 0 18 26 2 1
+twfeed1 18 0 22 26 0 1
+$COUNT_1/$FJK3_1 22 0 86 26 0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
+$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
+$COUNT_1/$FJK3_2 22 52 86 78 0 2
--- /dev/null
+1 0 0 86 26 0 0
+2 0 52 86 78 0 0
--- /dev/null
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
--- /dev/null
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
--- /dev/null
+net 1
+segment channel 2
+ pin1 1 pin2 7 0 0
+net 2
+segment channel 3
+pin1 41 pin2 42 0 0
+segment channel 2
+pin1 12 pin2 3 0 0
+net 3
+segment channel 2
+pin1 35 pin2 36 0 0
+segment channel 2
+pin1 19 pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5 pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14 pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23 pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25 pin2 31 0 0
+net 14
+net 15
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.096723 # Number of seconds simulated
+sim_ticks 96722945000 # Number of ticks simulated
+final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 2119754 # Simulator instruction rate (inst/s)
+host_op_rate 2119756 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1059884256 # Simulator tick rate (ticks/s)
+host_mem_usage 284956 # Number of bytes of host memory used
+host_seconds 91.26 # Real time elapsed on the host
+sim_insts 193444518 # Number of instructions simulated
+sim_ops 193444756 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory
+system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 773782140 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 773782140 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data 72065412 # Number of bytes written to this memory
+system.physmem.bytes_written::total 72065412 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 193445535 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 57735068 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 251180603 # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data 18976439 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 18976439 # Number of write requests responded to by this memory
+system.physmem.num_other::cpu.data 22406 # Number of other requests responded to by this memory
+system.physmem.num_other::total 22406 # Number of other requests responded to by this memory
+system.physmem.bw_read::cpu.inst 7999985319 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2310345420 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 10310330739 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7999985319 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7999985319 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 745070490 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 745070490 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 251180603 # Transaction distribution
+system.membus.trans_dist::ReadResp 251180603 # Transaction distribution
+system.membus.trans_dist::WriteReq 18976439 # Transaction distribution
+system.membus.trans_dist::WriteResp 18976439 # Transaction distribution
+system.membus.trans_dist::SwapReq 22406 # Transaction distribution
+system.membus.trans_dist::SwapResp 22406 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 386891070 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 153467826 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 540358896 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 773782140 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 295708073 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1069490213 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 270179448 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.715989 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.450942 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 76733913 28.40% 28.40% # Request fanout histogram
+system.membus.snoop_fanout::1 193445535 71.60% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 270179448 # Request fanout histogram
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.workload.num_syscalls 401 # Number of system calls
+system.cpu.numCycles 193445891 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 193444518 # Number of instructions committed
+system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses
+system.cpu.num_func_calls 1957920 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls
+system.cpu.num_int_insts 167974806 # number of integer instructions
+system.cpu.num_fp_insts 1970372 # number of float instructions
+system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read
+system.cpu.num_int_register_writes 163060124 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written
+system.cpu.num_mem_refs 76733958 # number of memory refs
+system.cpu.num_load_insts 57735091 # Number of load instructions
+system.cpu.num_store_insts 18998867 # Number of store instructions
+system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
+system.cpu.num_busy_cycles 193445890.998000 # Number of busy cycles
+system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
+system.cpu.Branches 15132745 # Number of branches fetched
+system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction
+system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction
+system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction
+system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction
+system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 193445773 # Class of executed instruction
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=262144
+
+[system.cpu.dtb]
+type=SparcTLB
+eventq_index=0
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=131072
+
+[system.cpu.interrupts]
+type=SparcInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=SparcISA
+eventq_index=0
+
+[system.cpu.itb]
+type=SparcTLB
+eventq_index=0
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=2097152
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:50:23
+gem5 executing on u200540-lin
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
+Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
+Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+info: Increasing stack size by one page.
+122 123 124 Exiting @ tick 270563082000 because target called exit()
--- /dev/null
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84 block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0 MISSING_ROWS:-46
+
+bdxlen:86 bdylen:78
+l:0 t:78 r:86 b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+ tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
+ tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
+ tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
+ tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
+
+ I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
+ 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
+ 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
+ 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
+ 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
+ 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
+ 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
+ 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
+ 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
+ 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
+ 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
+ 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
+ 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
+ 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
+ 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
+ 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
+ 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
+ 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
+ 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
+ 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
+ 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
+ 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
+ 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
+ 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
+ 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
+ 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
+ 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
+ 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
+ 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
+ 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
+ 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
+ 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
+ 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
+ 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
+ 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
+ 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
+ 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
+ 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
+ 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
+ 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
+ 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
+ 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
+ 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
+ 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
+ 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
+ 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
+ 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
+ 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
+ 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
+ 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
+ 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
+ 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
+ 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
+ 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
+ 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
+ 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
+ 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
+ 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
+ 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
+ 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
+ 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
+ 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
+ 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
+ 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
+ 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
+ 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
+ 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
+ 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
+ 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
+ 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
+ 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
+ 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
+ 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
+ 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
+ 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
+ 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
+ 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
+ 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
+ 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
+ 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
+ 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
+ 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
+ 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
+ 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
+ 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
+ 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
+ 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
+ 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
+ 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
+ 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
+ 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
+ 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
+ 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
+ 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
+ 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
+ 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
+ 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
+ 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
+ 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
+ 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
+100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
+101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
+102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
+103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
+104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
+105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
+106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
+107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
+108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
+109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
+110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
+111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
+112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
+113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
+114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
+115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
+116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
+117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
+118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
+119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
+120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
+121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
+
+Initial Wiring Cost: 645 Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645 Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216 Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429 Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 82 -20
+ 2 86 -16
+
+LONGEST Block is:2 Its length is:86
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 86 -16
+ 2 86 -16
+
+LONGEST Block is:1 Its length is:86
+Added: 1 feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl: 1.650
+finalRowControl: 0.300
+iter T Wire accept
+ 122 0.001 976 16%
+ 123 0.001 971 0%
+ 124 0.001 971 0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL: 1 is: 0
+MAX OF CHANNEL: 2 is: 4
+MAX OF CHANNEL: 3 is: 1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0
+Number of Nets: 15
+Number of Pins: 46
+Usage statistics not available
--- /dev/null
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
--- /dev/null
+$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
+$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
+ACOUNT_1 14 0 18 26 2 1
+twfeed1 18 0 22 26 0 1
+$COUNT_1/$FJK3_1 22 0 86 26 0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
+$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
+$COUNT_1/$FJK3_2 22 52 86 78 0 2
--- /dev/null
+1 0 0 86 26 0 0
+2 0 52 86 78 0 0
--- /dev/null
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
--- /dev/null
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
--- /dev/null
+net 1
+segment channel 2
+ pin1 1 pin2 7 0 0
+net 2
+segment channel 3
+pin1 41 pin2 42 0 0
+segment channel 2
+pin1 12 pin2 3 0 0
+net 3
+segment channel 2
+pin1 35 pin2 36 0 0
+segment channel 2
+pin1 19 pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5 pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14 pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23 pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25 pin2 31 0 0
+net 14
+net 15
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.270563 # Number of seconds simulated
+sim_ticks 270563082500 # Number of ticks simulated
+final_tick 270563082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1283602 # Simulator instruction rate (inst/s)
+host_op_rate 1283603 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1795321724 # Simulator tick rate (ticks/s)
+host_mem_usage 297332 # Number of bytes of host memory used
+host_seconds 150.70 # Real time elapsed on the host
+sim_insts 193444518 # Number of instructions simulated
+sim_ops 193444756 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory
+system.physmem.bytes_read::total 331072 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 850848 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 372793 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1223641 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 850848 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 850848 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.workload.num_syscalls 401 # Number of system calls
+system.cpu.numCycles 541126165 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 193444518 # Number of instructions committed
+system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses
+system.cpu.num_func_calls 1957920 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls
+system.cpu.num_int_insts 167974806 # number of integer instructions
+system.cpu.num_fp_insts 1970372 # number of float instructions
+system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read
+system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written
+system.cpu.num_mem_refs 76733958 # number of memory refs
+system.cpu.num_load_insts 57735091 # Number of load instructions
+system.cpu.num_store_insts 18998867 # Number of store instructions
+system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
+system.cpu.num_busy_cycles 541126164.998000 # Number of busy cycles
+system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
+system.cpu.Branches 15132745 # Number of branches fetched
+system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction
+system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction
+system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction
+system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction
+system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction
+system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 193445773 # Class of executed instruction
+system.cpu.dcache.tags.replacements 2 # number of replacements
+system.cpu.dcache.tags.tagsinuse 1237.203936 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203936 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits
+system.cpu.dcache.overall_hits::total 76709932 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses
+system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses
+system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses
+system.cpu.dcache.overall_misses::total 1575 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles
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+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 4095 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145678500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20169000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 165847500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43659000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43659000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145678500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63828000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 209506500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145678500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63828000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 209506500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24576 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 27730 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 13866 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 13866 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 13866 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 4095 # Transaction distribution
+system.membus.trans_dist::ReadResp 4095 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1078 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1078 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 5173 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 5173 # Request fanout histogram
+system.membus.reqLayer0.occupancy 5173500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 25865500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=atomic
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=apic_clk_domain dtb interrupts isa itb tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+
+[system.cpu.dtb]
+type=X86TLB
+children=walker
+eventq_index=0
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+num_squash_per_cycle=4
+system=system
+port=system.membus.slave[4]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=100000
+system=system
+int_master=system.membus.slave[5]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
+
+[system.cpu.isa]
+type=X86ISA
+eventq_index=0
+
+[system.cpu.itb]
+type=X86TLB
+children=walker
+eventq_index=0
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+num_squash_per_cycle=4
+system=system
+port=system.membus.slave[3]
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
+drivers=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+gid=100
+input=cin
+kvmInSE=false
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 22:11:10
+gem5 executing on u200540-lin
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
+Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
+Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 Exiting @ tick 131393279000 because target called exit()
--- /dev/null
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84 block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0 MISSING_ROWS:-46
+
+bdxlen:86 bdylen:78
+l:0 t:78 r:86 b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+ tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
+ tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
+ tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
+ tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
+
+ I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
+ 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
+ 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
+ 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
+ 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
+ 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
+ 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
+ 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
+ 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
+ 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
+ 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
+ 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
+ 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
+ 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
+ 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
+ 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
+ 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
+ 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
+ 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
+ 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
+ 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
+ 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
+ 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
+ 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
+ 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
+ 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
+ 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
+ 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
+ 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
+ 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
+ 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
+ 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
+ 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
+ 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
+ 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
+ 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
+ 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
+ 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
+ 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
+ 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
+ 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
+ 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
+ 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
+ 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
+ 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
+ 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
+ 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
+ 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
+ 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
+ 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
+ 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
+ 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
+ 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
+ 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
+ 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
+ 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
+ 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
+ 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
+ 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
+ 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
+ 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
+ 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
+ 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
+ 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
+ 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
+ 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
+ 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
+ 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
+ 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
+ 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
+ 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
+ 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
+ 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
+ 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
+ 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
+ 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
+ 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
+ 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
+ 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
+ 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
+ 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
+ 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
+ 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
+ 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
+ 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
+ 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
+ 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
+ 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
+ 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
+ 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
+ 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
+ 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
+ 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
+ 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
+ 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
+ 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
+ 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
+ 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
+ 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
+ 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
+100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
+101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
+102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
+103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
+104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
+105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
+106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
+107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
+108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
+109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
+110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
+111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
+112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
+113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
+114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
+115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
+116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
+117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
+118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
+119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
+120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
+121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
+
+Initial Wiring Cost: 645 Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645 Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216 Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429 Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 82 -20
+ 2 86 -16
+
+LONGEST Block is:2 Its length is:86
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 86 -16
+ 2 86 -16
+
+LONGEST Block is:1 Its length is:86
+Added: 1 feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl: 1.650
+finalRowControl: 0.300
+iter T Wire accept
+ 122 0.001 976 16%
+ 123 0.001 971 0%
+ 124 0.001 971 0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL: 1 is: 0
+MAX OF CHANNEL: 2 is: 4
+MAX OF CHANNEL: 3 is: 1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0
+Number of Nets: 15
+Number of Pins: 46
+Usage statistics not available
--- /dev/null
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
--- /dev/null
+$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
+$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
+ACOUNT_1 14 0 18 26 2 1
+twfeed1 18 0 22 26 0 1
+$COUNT_1/$FJK3_1 22 0 86 26 0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
+$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
+$COUNT_1/$FJK3_2 22 52 86 78 0 2
--- /dev/null
+1 0 0 86 26 0 0
+2 0 52 86 78 0 0
--- /dev/null
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
--- /dev/null
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
--- /dev/null
+net 1
+segment channel 2
+ pin1 1 pin2 7 0 0
+net 2
+segment channel 3
+pin1 41 pin2 42 0 0
+segment channel 2
+pin1 12 pin2 3 0 0
+net 3
+segment channel 2
+pin1 35 pin2 36 0 0
+segment channel 2
+pin1 19 pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5 pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14 pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23 pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25 pin2 31 0 0
+net 14
+net 15
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.131393 # Number of seconds simulated
+sim_ticks 131393279000 # Number of ticks simulated
+final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1264426 # Simulator instruction rate (inst/s)
+host_op_rate 2119294 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1257935779 # Simulator tick rate (ticks/s)
+host_mem_usage 324376 # Number of bytes of host memory used
+host_seconds 104.45 # Real time elapsed on the host
+sim_insts 132071193 # Number of instructions simulated
+sim_ops 221363385 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 310423752 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1698378688 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1387954936 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1387954936 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data 99822191 # Number of bytes written to this memory
+system.physmem.bytes_written::total 99822191 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 173494367 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 56682005 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 230176372 # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data 20515731 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 20515731 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 10563363260 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2362554267 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 12925917527 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 10563363260 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 10563363260 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 759720678 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 759720678 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s)
+system.membus.trans_dist::ReadReq 230176372 # Transaction distribution
+system.membus.trans_dist::ReadResp 230176372 # Transaction distribution
+system.membus.trans_dist::WriteReq 20515731 # Transaction distribution
+system.membus.trans_dist::WriteResp 20515731 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 250692103 # Request fanout histogram
+system.membus.snoop_fanout::mean 2.692062 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::2 77197736 30.79% 30.79% # Request fanout histogram
+system.membus.snoop_fanout::3 173494367 69.21% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 2 # Request fanout histogram
+system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::total 250692103 # Request fanout histogram
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.numCycles 262786559 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 132071193 # Number of instructions committed
+system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
+system.cpu.num_func_calls 1595632 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
+system.cpu.num_int_insts 219019986 # number of integer instructions
+system.cpu.num_fp_insts 2162459 # number of float instructions
+system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read
+system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
+system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written
+system.cpu.num_mem_refs 77165304 # number of memory refs
+system.cpu.num_load_insts 56649587 # Number of load instructions
+system.cpu.num_store_insts 20515717 # Number of store instructions
+system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
+system.cpu.num_busy_cycles 262786558.998000 # Number of busy cycles
+system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
+system.cpu.Branches 12326938 # Number of branches fetched
+system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction
+system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction
+system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction
+system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction
+system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction
+system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 221363385 # Class of executed instruction
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TimingSimpleCPU
+children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+
+[system.cpu.dcache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=262144
+
+[system.cpu.dtb]
+type=X86TLB
+children=walker
+eventq_index=0
+size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+num_squash_per_cycle=4
+system=system
+port=system.cpu.toL2Bus.slave[3]
+
+[system.cpu.icache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=2
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=131072
+
+[system.cpu.interrupts]
+type=X86LocalApic
+clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=100000
+system=system
+int_master=system.membus.slave[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
+
+[system.cpu.isa]
+type=X86ISA
+eventq_index=0
+
+[system.cpu.itb]
+type=X86TLB
+children=walker
+eventq_index=0
+size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+num_squash_per_cycle=4
+system=system
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=2097152
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
+drivers=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+gid=100
+input=cin
+kvmInSE=false
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=Null
+system=system
+use_default_range=false
+width=8
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 22:12:53
+gem5 executing on u200540-lin
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
+Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
+Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 Exiting @ tick 250953957000 because target called exit()
--- /dev/null
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84 block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0 MISSING_ROWS:-46
+
+bdxlen:86 bdylen:78
+l:0 t:78 r:86 b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+ tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
+ tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
+ tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
+ tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
+
+ I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
+ 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
+ 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
+ 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
+ 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
+ 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
+ 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
+ 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
+ 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
+ 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
+ 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
+ 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
+ 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
+ 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
+ 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
+ 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
+ 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
+ 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
+ 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
+ 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
+ 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
+ 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
+ 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
+ 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
+ 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
+ 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
+ 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
+ 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
+ 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
+ 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
+ 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
+ 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
+ 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
+ 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
+ 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
+ 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
+ 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
+ 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
+ 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
+ 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
+ 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
+ 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
+ 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
+ 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
+ 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
+ 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
+ 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
+ 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
+ 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
+ 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
+ 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
+ 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
+ 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
+ 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
+ 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
+ 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
+ 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
+ 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
+ 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
+ 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
+ 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
+ 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
+ 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
+ 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
+ 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
+ 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
+ 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
+ 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
+ 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
+ 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
+ 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
+ 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
+ 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
+ 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
+ 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
+ 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
+ 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
+ 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
+ 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
+ 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
+ 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
+ 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
+ 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
+ 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
+ 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
+ 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
+ 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
+ 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
+ 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
+ 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
+ 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
+ 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
+ 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
+ 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
+ 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
+ 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
+ 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
+ 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
+ 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
+ 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
+100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
+101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
+102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
+103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
+104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
+105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
+106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
+107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
+108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
+109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
+110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
+111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
+112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
+113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
+114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
+115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
+116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
+117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
+118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
+119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
+120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
+121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
+
+Initial Wiring Cost: 645 Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645 Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216 Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429 Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 82 -20
+ 2 86 -16
+
+LONGEST Block is:2 Its length is:86
+BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
+ 1 86 -16
+ 2 86 -16
+
+LONGEST Block is:1 Its length is:86
+Added: 1 feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl: 1.650
+finalRowControl: 0.300
+iter T Wire accept
+ 122 0.001 976 16%
+ 123 0.001 971 0%
+ 124 0.001 971 0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL: 1 is: 0
+MAX OF CHANNEL: 2 is: 4
+MAX OF CHANNEL: 3 is: 1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0
+Number of Nets: 15
+Number of Pins: 46
+Usage statistics not available
--- /dev/null
+$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
+$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
+B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
+B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
+B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
+B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
+B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
+$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
+$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
+$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
+$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
--- /dev/null
+$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
+$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
+$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
+ACOUNT_1 14 0 18 26 2 1
+twfeed1 18 0 22 26 0 1
+$COUNT_1/$FJK3_1 22 0 86 26 0 1
+$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
+$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
+$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
+$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
+$COUNT_1/$FJK3_2 22 52 86 78 0 2
--- /dev/null
+1 0 0 86 26 0 0
+2 0 52 86 78 0 0
--- /dev/null
+0.009592
+121
+0
+1
+0.000000
+0.500000
+3.906156
+1
+1 1 2 37 13
+2 2 0 34 65
+3 2 2 63 65
+4 1 0 59 13
+5 1 2 32 13
+6 2 0 23 65
+7 1 2 12 13
+8 2 0 6 65
+9 1 0 70 13
+10 2 0 70 65
--- /dev/null
+0.001000
+123
+0
+2
+0.000000
+0.500000
+3.906156
+1
+1 1 2 16 13
+2 2 2 19 65
+3 2 2 14 65
+4 1 0 11 13
+5 1 2 6 13
+6 2 0 3 65
+7 1 0 2 13
+8 2 2 9 65
+9 1 0 50 13
+10 2 0 54 65
+11 1 0 84 13
--- /dev/null
+net 1
+segment channel 2
+ pin1 1 pin2 7 0 0
+net 2
+segment channel 3
+pin1 41 pin2 42 0 0
+segment channel 2
+pin1 12 pin2 3 0 0
+net 3
+segment channel 2
+pin1 35 pin2 36 0 0
+segment channel 2
+pin1 19 pin2 35 0 0
+net 4
+segment channel 2
+ pin1 5 pin2 38 0 0
+net 5
+net 7
+segment channel 2
+ pin1 14 pin2 43 0 0
+net 8
+segment channel 2
+ pin1 23 pin2 17 0 0
+net 9
+net 11
+segment channel 2
+ pin1 25 pin2 31 0 0
+net 14
+net 15
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.250954 # Number of seconds simulated
+sim_ticks 250953957500 # Number of ticks simulated
+final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 722726 # Simulator instruction rate (inst/s)
+host_op_rate 1211354 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1373280924 # Simulator tick rate (ticks/s)
+host_mem_usage 338728 # Number of bytes of host memory used
+host_seconds 182.74 # Real time elapsed on the host
+sim_insts 132071193 # Number of instructions simulated
+sim_ops 221363385 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory
+system.physmem.bytes_read::total 303040 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 724276 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 483276 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1207552 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 724276 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 724276 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
+system.cpu.workload.num_syscalls 400 # Number of system calls
+system.cpu.numCycles 501907915 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 132071193 # Number of instructions committed
+system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
+system.cpu.num_func_calls 1595632 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
+system.cpu.num_int_insts 219019986 # number of integer instructions
+system.cpu.num_fp_insts 2162459 # number of float instructions
+system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read
+system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
+system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written
+system.cpu.num_mem_refs 77165304 # number of memory refs
+system.cpu.num_load_insts 56649587 # Number of load instructions
+system.cpu.num_store_insts 20515717 # Number of store instructions
+system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
+system.cpu.num_busy_cycles 501907914.998000 # Number of busy cycles
+system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
+system.cpu.Branches 12326938 # Number of branches fetched
+system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction
+system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction
+system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction
+system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction
+system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction
+system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction
+system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 221363385 # Class of executed instruction
+system.cpu.dcache.tags.replacements 41 # number of replacements
+system.cpu.dcache.tags.tagsinuse 1363.457564 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457564 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits
+system.cpu.dcache.overall_hits::total 77195831 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses
+system.cpu.dcache.overall_misses::total 1905 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 7 # number of writebacks
+system.cpu.dcache.writebacks::total 7 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17202000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 17202000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84297000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 84297000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 101499000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 101499000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 101499000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 101499000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.504587 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.504587 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53420.152091 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53420.152091 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.tags.replacements 2836 # number of replacements
+system.cpu.icache.tags.tagsinuse 1455.296636 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296636 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 394 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits
+system.cpu.icache.overall_hits::total 173489673 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses
+system.cpu.icache.overall_misses::total 4694 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 180319500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 180319500 # number of demand (read+write) miss cycles
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+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9388 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3817 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 13205 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 6606 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 6606 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 6606 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 3160 # Transaction distribution
+system.membus.trans_dist::ReadResp 3160 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1575 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 4735 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 4735 # Request fanout histogram
+system.membus.reqLayer0.occupancy 4754000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 23694000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
+
+---------- End Simulation Statistics ----------
--- /dev/null
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Korey Sewell
+
+m5.util.addToPath('../configs/common')
+from cpu2000 import twolf
+import os
+
+workload = twolf(isa, opsys, 'smred')
+root.system.cpu[0].workload = workload.makeLiveProcess()
+cwd = root.system.cpu[0].workload[0].cwd
+
+#Remove two files who's presence or absence affects execution
+sav_file = os.path.join(cwd, workload.input_set + '.sav')
+sv2_file = os.path.join(cwd, workload.input_set + '.sv2')
+try:
+ os.unlink(sav_file)
+except:
+ print "Couldn't unlink ", sav_file
+try:
+ os.unlink(sv2_file)
+except:
+ print "Couldn't unlink ", sv2_file
projects / gem5.git / commitdiff