Fix expected misa register value for RV32

diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S
index 2eeb14cdb6247f977ee2d79a8606fbbb09e2b6ac..4bb04454c0808ec3c0c0e91ea2877a1520c73e93 100644 (file)
--- a/isa/rv64mi/mcsr.S
+++ b/isa/rv64mi/mcsr.S
@@ -17,7 +17,7 @@ RVTEST_CODE_BEGIN
 #ifdef __riscv64
   TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62)
 #else
-  TEST_CASE(2, a0, 0x0, csrr a0, misa; srl a0, a0, 30)
+  TEST_CASE(2, a0, 0x1, csrr a0, misa; srl a0, a0, 30)
 #endif
 
   # Check that mhartid reports 0