targets/minispartan6/crg: only keep S6PLL code

diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py
index aaea92a51b2748834d87830b804cfe698abd4efa..807adba4e5dd1d4a836b520fb0ee27e7463351aa 100755 (executable)
--- a/litex/boards/targets/minispartan6.py
+++ b/litex/boards/targets/minispartan6.py
@@ -23,7 +23,7 @@ from litedram.phy import GENSDRPHY
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
-    def __init__(self, platform, clk_freq, use_s6pll=False):
+    def __init__(self, platform, clk_freq):
         self.clock_domains.cd_sys = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain()
 
@@ -32,56 +32,17 @@ class _CRG(Module):
         self.cd_sys.clk.attr.add("keep")
         self.cd_sys_ps.clk.attr.add("keep")
 
-        if use_s6pll:
-            self.submodules.pll = pll = S6PLL(speedgrade=-1)
-            pll.register_clkin(platform.request("clk32"), 32e6)
-            pll.create_clkout(self.cd_sys, clk_freq)
-            pll.create_clkout(self.cd_sys_ps, clk_freq, phase=270)
-        else:
-            f0 = 32*1000000
-            clk32 = platform.request("clk32")
-            clk32a = Signal()
-            self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
-            clk32b = Signal()
-            self.specials += Instance("BUFIO2", p_DIVIDE=1,
-                                      p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
-                                      i_I=clk32a, o_DIVCLK=clk32b)
-            f = Fraction(int(clk_freq), int(f0))
-            n, m, p = f.denominator, f.numerator, 8
-            assert f0/n*m == clk_freq
-            pll_lckd = Signal()
-            pll_fb = Signal()
-            pll = Signal(6)
-            self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
-                                         p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
-                                         p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
-                                         i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
-                                         p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
-                                         i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
-                                         p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
-                                         i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
-                                         o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
-                                         o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
-                                         o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
-                                         o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
-                                         o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
-                                         o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
-                                         p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//1,
-                                         p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
-                                         p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
-                                         p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
-                                         p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1,  # sys
-                                         p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1,  # sys_ps
-            )
-            self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
-            self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
-            self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd)
-
-        self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
-                                  p_INIT=0, p_SRTYPE="SYNC",
-                                  i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
-                                  i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
-                                  o_Q=platform.request("sdram_clock"))
+        self.submodules.pll = pll = S6PLL(speedgrade=-1)
+        pll.register_clkin(platform.request("clk32"), 32e6)
+        pll.create_clkout(self.cd_sys, clk_freq)
+        pll.create_clkout(self.cd_sys_ps, clk_freq, phase=270)
+
+        self.specials += Instance("ODDR2",
+            p_DDR_ALIGNMENT="NONE",
+            p_INIT=0, p_SRTYPE="SYNC",
+            i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
+            i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
+            o_Q=platform.request("sdram_clock"))
 
 # BaseSoC ------------------------------------------------------------------------------------------