PATCH [2/10] arm: add 'pacbti' instruction for Armv8.1-M pacbti extension

gas/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* config/tc-arm.c
	(enum operand_parse_code): Add OP_SP and OP_R12.
	(parse_operands): Add switch cases for OP_SP and OP_R12.
	(T16_32_TAB): Add '_pacbti'.
	(do_t_pacbti): New function.
	(insns): Add 'pacbti'.
	* testsuite/gas/arm/armv8_1-m-pacbti-bad.d: New file.
	* testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Likewise.
	* testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise.
	* testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'pacbti' to testcase.
	* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.

opcodes/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* arm-dis.c (thumb32_opcodes): Add 'pacbti' instruction.

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index d7f8fca803ba479344c37650a38d4a532b8ae634..ed870f01aee7cd1fdbba87a40db27833c242be2e 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7115,6 +7115,8 @@ enum operand_parse_code
 
   /* New operands for Armv8.1-M Mainline.  */
   OP_LR,       /* ARM LR register */
+  OP_SP,       /* ARM SP register */
+  OP_R12,
   OP_RRe,      /* ARM register, only even numbered.  */
   OP_RRo,      /* ARM register, only odd numbered, not r13 or r15.  */
   OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
@@ -7425,6 +7427,8 @@ parse_operands (char *str, const unsigned int *pattern, bool thumb)
        case OP_RRo:
        case OP_LR:
        case OP_oLR:
+       case OP_SP:
+       case OP_R12:
        case OP_RR:    po_reg_or_fail (REG_TYPE_RN);      break;
        case OP_RCP:   po_reg_or_fail (REG_TYPE_CP);      break;
        case OP_RCN:   po_reg_or_fail (REG_TYPE_CN);      break;
@@ -8122,6 +8126,16 @@ parse_operands (char *str, const unsigned int *pattern, bool thumb)
            inst.error = _("operand must be LR register");
          break;
 
+       case OP_SP:
+         if (inst.operands[i].reg != REG_SP)
+           inst.error = _("operand must be SP register");
+         break;
+
+       case OP_R12:
+         if (inst.operands[i].reg != REG_R12)
+           inst.error = _("operand must be r12");
+         break;
+
        case OP_RMQRZ:
        case OP_oRMQRZ:
        case OP_RR_ZR:
@@ -11491,6 +11505,7 @@ encode_thumb32_addr_mode (int i, bool is_t, bool is_d)
   X(_negs,  4240, f1d00000), /* rsbs #0 */     \
   X(_orr,   4300, ea400000),                   \
   X(_orrs,  4300, ea500000),                   \
+  X(_pacbti, 0000, f3af800d),                  \
   X(_pop,   bc00, e8bd0000), /* ldmia sp!,... */       \
   X(_push,  b400, e92d0000), /* stmdb sp!,... */       \
   X(_rev,   ba00, fa90f080),                   \
@@ -22317,6 +22332,12 @@ do_vmmla (void)
   neon_three_args (1);
 }
 
+static void
+do_t_pacbti (void)
+{
+  inst.instruction = THUMB_OP32 (inst.instruction);
+}
+
 \f
 /* Overall per-instruction processing. */
 
@@ -26306,6 +26327,7 @@ static const struct asm_opcode insns[] =
 #undef  THUMB_VARIANT
 #define THUMB_VARIANT & arm_ext_v8_1m_main
  ToU("bti",   f3af800f, 0, (), noargs),
+ toU("pacbti", _pacbti, 3, (R12, LR, SP), t_pacbti),
  toU("cinc",  _cinc,  3, (RRnpcsp, RR_ZR, COND),       t_cond),
  toU("cinv",  _cinv,  3, (RRnpcsp, RR_ZR, COND),       t_cond),
  toU("cneg",  _cneg,  3, (RRnpcsp, RR_ZR, COND),       t_cond),

diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.d b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.d
new file mode 100644 (file)
index 0000000..77638ee
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.d
@@ -0,0 +1,5 @@
+#name: Invalid Armv8.1-M pointer authentication and branch target identification extention
+#skip: *-*-pe
+#source: armv8_1-m-pacbti-bad.s
+#as: -march=armv8.1-m.main
+#error_output: armv8_1-m-pacbti-bad.l

diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l
new file mode 100644 (file)
index 0000000..a812603
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l
@@ -0,0 +1,4 @@
+.*: Assembler messages:
+.*:6: Error: operand must be r12 -- `pacbti r11,lr,sp'
+.*:7: Error: operand must be LR register -- `pacbti r12,r10,sp'
+.*:8: Error: operand must be SP register -- `pacbti r12,lr,r10'

diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s
new file mode 100644 (file)
index 0000000..64e71e7
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s
@@ -0,0 +1,8 @@
+       .syntax unified
+       .text
+       .thumb
+.Lstart:
+       bti
+       pacbti  r11, lr, sp
+       pacbti  r12, r10, sp
+       pacbti  r12, lr, r10

diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
index 3c6937284681fa43728c16554cb75332655f687d..593ac34ed49872c58c9763f186a132c5dedc577b 100644 (file)
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
@@ -7,4 +7,5 @@
 
 Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> f3af 800f   bti
+0[0-9a-f]+ <[^>]+> f3af 800d   pacbti  r12, lr, sp
 #...

diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
index 38929e3dd02e62de27635fa368578963dba2def4..39db4542e39612fe7dc6fb43cf2b24587e14890d 100644 (file)
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
@@ -3,3 +3,4 @@
        .thumb
 .Lstart:
        bti
+       pacbti  r12, lr, sp

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 1e0969975438e8f9b4af99781a885178325dfc21..34b0ace58bc4842bc8b7cf7ebddd56d5b87beda5 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -4656,6 +4656,8 @@ static const struct opcode32 thumb32_opcodes[] =
      Identification Extension.  */
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
    0xf3af800f, 0xffffffff, "bti"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+   0xf3af800d, 0xffffffff, "pacbti\tr12, lr, sp"},
 
   /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
      instructions.  */