back.rtlil: more consistent prefixing for subfragment port wires.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 370b42ca0ddccc6748db2e36e053fae799a352db..c2b8809da4ff0364e918cf92c546a8b0033f0fc9 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -645,11 +645,9 @@ def convert_fragment(builder, fragment, name, top):
 
             sub_ports = OrderedDict()
             for port, value in sub_port_map.items():
-                if isinstance(value, ast.Signal):
-                    sigspec = compiler_state.resolve_curr(value, prefix=sub_name)
-                else:
-                    sigspec = rhs_compiler(value)
-                sub_ports[port] = sigspec
+                for signal in value._rhs_signals():
+                    compiler_state.resolve_curr(signal, prefix=sub_name)
+                sub_ports[port] = rhs_compiler(value)
 
             module.cell(sub_type, name=sub_name, ports=sub_ports, params=sub_params)