platforms/kc705: use jtaghs1_fast cable

diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py
index 696055f8ec7bf6cf0737ec2b5f2d01a0884dfd57..a9ad4933bd33c88b0aabe5ba2d0a8af1d7d07320 100644 (file)
--- a/mibuild/platforms/kc705.py
+++ b/mibuild/platforms/kc705.py
@@ -139,7 +139,7 @@ def Platform(*args, toolchain="vivado", **kwargs):
                        xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
 
                def create_programmer(self):
-                       return XC3SProg("jtaghs1", "bscan_spi_kc705.bit")
+                       return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit")
 
                def do_finalize(self, fragment):
                        try: