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Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.
author
Alberto Gonzalez
<boqwxp@airmail.cc>
Mon, 20 Apr 2020 04:46:09 +0000
(
04:46
+0000)
committer
Alberto Gonzalez
<boqwxp@airmail.cc>
Thu, 14 May 2020 20:06:54 +0000
(20:06 +0000)
passes/techmap/techmap.cc
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diff --git
a/passes/techmap/techmap.cc
b/passes/techmap/techmap.cc
index 17d98847ebbc3b039be127ce799f7e27d8669141..ab719cbaab349c823f9cad9e58ff0ed3d2fee6c3 100644
(file)
--- a/
passes/techmap/techmap.cc
+++ b/
passes/techmap/techmap.cc
@@
-490,8
+490,8
@@
struct TechmapWorker
}
TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
- dict<RTLIL::Cell*,
std::set
<RTLIL::SigBit>> cell_to_inbit;
- dict<RTLIL::SigBit,
std::set
<RTLIL::Cell*>> outbit_to_cell;
+ dict<RTLIL::Cell*,
pool
<RTLIL::SigBit>> cell_to_inbit;
+ dict<RTLIL::SigBit,
pool
<RTLIL::Cell*>> outbit_to_cell;
for (auto cell : module->selected_cells())
{