log_debug() for abc9_{arrival,required} times

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index cde53ff63a7f33457a3a97923aa0edc64760504f..359d951b9b7bb96f46db1adcba6cbc88856e4261 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -254,6 +254,14 @@ struct XAigerWriter
                                                        log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
                                                                        GetSize(port_wire), log_signal(it->second), GetSize(arrivals));
                                                auto jt = arrivals.begin();
+
+#ifndef NDEBUG
+                                               if (ys_debug(1)) {
+                                                       static std::set<std::pair<IdString,IdString>> seen;
+                                                       if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt);
+                                               }
+#endif
+
                                                for (auto bit : sigmap(conn.second)) {
                                                        arrival_times[bit] = *jt;
                                                        if (arrivals.size() > 1)

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 918afd284a5176b6014f393dfd7afbcae81e71b5..eac1ff2b6318d0dbb279c50f4286568a83062d0a 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -512,7 +512,7 @@ void prep_times(RTLIL::Design *design)
                requireds.clear();
                for (auto cell : boxes) {
                        RTLIL::Module* inst_module = module->design->module(cell->type);
-
+                       log_assert(inst_module);
                        for (auto &conn : cell->connections_) {
                                auto port_wire = inst_module->wire(conn.first);
                                if (!port_wire->port_input)
@@ -537,6 +537,12 @@ void prep_times(RTLIL::Design *design)
 
                                SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
                                for (const auto &i : requireds) {
+#ifndef NDEBUG
+                                       if (ys_debug(1)) {
+                                               static std::set<std::pair<IdString,IdString>> seen;
+                                               if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), i.first);
+                                       }
+#endif
                                        delays.insert(i.first);
                                        for (auto offset : i.second) {
                                                auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));