Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance
or increased latency in some implementations due to lane-crossing.
-# Mode
+## Mode
Mode is an augmentation of SV behaviour. Different types of instructions
have different needs, similar to Power ISA v3.1 64 bit prefix 8LS and MTRR
* For Branch modes, see [[sv/branches]]
* For arithmetic and logical, see [[sv/normal]]
-# ELWIDTH Encoding
+## ELWIDTH Encoding
Default behaviour is set to 0b00 so that zeros follow the convention
of `scalar identity behaviour`. In this case it means that elwidth
Only when elwidth is nonzero is the element width overridden to the
explicitly required value.
-## Elwidth for Integers:
+### Elwidth for Integers:
| Value | Mnemonic | Description |
|-------|----------------|------------------------------------|
This encoding is chosen such that the byte width may be computed as
`8<<(3-ew)`
-## Elwidth for FP Registers:
+### Elwidth for FP Registers:
| Value | Mnemonic | Description |
|-------|----------------|------------------------------------|
or ELWIDTH=bf16 is reserved and must raise an illegal instruction
(IEEE754 FP8 or BF8 are not defined).
-## Elwidth for CRs:
+### Elwidth for CRs (no meaning)
Element-width overrides for CR Fields has no meaning. The bits
are therefore used for other purposes, or when Rc=1, the Elwidth
applies to the result being tested (a GPR or FPR), but not to the
Vector of CR Fields.
-# SUBVL Encoding
+## SUBVL Encoding
The default for SUBVL is 1 and its encoding is 0b00 to indicate that
SUBVL is effectively disabled (a SUBVL for-loop of only one element). this
sub-vector. SUBVL=2 represents a vec2, its encoding is 0b01, therefore
this may be considered to be elements 0b00 to 0b01 inclusive.
-# MASK/MASK_SRC & MASKMODE Encoding
+## MASK/MASK_SRC & MASKMODE Encoding
One bit (`MASKMODE`) indicates the mode: CR or Int predication. The two
types may not be mixed.
issued a Vector Instruction where previous elements could have overwritten
(destroyed) not-yet-executed CR-Predicated element operations.
-## Integer Predication (MASKMODE=0)
+### Integer Predication (MASKMODE=0)
When the predicate mode bit is zero the 3 bits are interpreted as below.
Twin predication has an identical 3 bit field similarly encoded.
r10 and r30 are at the high end of temporary and unused registers,
so as not to interfere with register allocation from ABIs.
-## CR-based Predication (MASKMODE=1)
+### CR-based Predication (MASKMODE=1)
When the predicate mode bit is one the 3 bits are interpreted as below.
Twin predication has an identical 3 bit field similarly encoded.
points to multiples of 8 (CR0, CR8, CR16...) both Vectorised Rc=1 and
CR Predicate Masks have to be adapted to fit on these boundaries as well.
-# Extra Remapped Encoding <a name="extra_remap"> </a>
+#
# Extra Remapped Encoding <a name="extra_remap"> </a>
Shows all instruction-specific fields in the Remapped Encoding
`RM[10:18]` for all instruction variants. Note that due to the very
* `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
* `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
-## RM-1P-3S1D
+### RM-1P-3S1D
| Field Name | Field bits | Description |
|------------|------------|----------------------------------------|
such as `maddedu` have an implicit second destination, RS, the
selection of which is determined by bit 18.
-## RM-1P-2S1D
+### RM-1P-2S1D
| Field Name | Field bits | Description |
|------------|------------|-------------------------------------------|
each may be *independently* made vector or scalar, and be independently
augmented to 7 bits in length.
-## RM-2P-1S1D/2S
+### RM-2P-1S1D/2S
| Field Name | Field bits | Description |
|------------|------------|----------------------------|
`RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2.
-## RM-1P-2S1D
+### RM-1P-2S1D
single-predicate, three registers (2 read, 1 write)
| Rsrc1_EXTRA3 | `13:15` | extends Rsrc1 |
| Rsrc2_EXTRA3 | `16:18` | extends Rsrc2 |
-## RM-2P-2S1D/1S2D/3S
+### RM-2P-2S1D/1S2D/3S
The primary purpose for this encoding is for Twin Predication on LOAD
and STORE operations. see [[sv/ldst]] for detailed anslysis.
Note that if ELWIDTH != ELWIDTH_SRC this may result in reduced performance
or increased latency in some implementations due to lane-crossing.
-# R\*\_EXTRA2/3
+## R\*\_EXTRA2/3
EXTRA is the means by which two things are achieved:
Note that in some cases the range of starting points for Vectors
is limited.
-## INT/FP EXTRA3
+### INT/FP EXTRA3
If EXTRA3 is zero, maps to "scalar identity" (scalar Power ISA field
naming).
| 110 | Vector | `r2-r126`/4 | `RA 0b10` |
| 111 | Vector | `r3-r127`/4 | `RA 0b11` |
-## INT/FP EXTRA2
+### INT/FP EXTRA2
If EXTRA2 is zero will map to
"scalar identity behaviour" i.e Scalar Power ISA register naming:
as there is insufficient bits to cover the full range.
-## CR Field EXTRA3
+### CR Field EXTRA3
CR Field encoding is essentially the same but made more complex due to CRs
being bit-based, because the application of SVP64 element-numbering applies
| 110 | Vector | `CR8-CR120`/16 | BFA 1 | 0b000 |
| 111 | Vector | `CR12-CR124`/16 | BFA 1 | 0b100 |
-## CR EXTRA2
+### CR EXTRA2
CR encoding is essentially the same but made more complex due to CRs
being bit-based, because the application of SVP64 element-numbering applies
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