Merge branch 'eddie/abc9_refactor' into eddie/abc9_required

diff --cc backends/aiger/xaiger.cc
Simple merge

diff --cc passes/techmap/abc9.cc
Simple merge

diff --cc passes/techmap/abc9_exe.cc
Simple merge

diff --cc passes/techmap/abc9_ops.cc
index 13340f311a4e28202f3e2fb21d01e7de465f764d,9ad29a8f646c74b3a92415d4007b2da543cb7087..0fc4de3bb34f6669f80ab6f12d1cda5e4e661d32
--- 1/passes/techmap/abc9_ops.cc
--- 2/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@@ -246,13 -165,17 +254,15 @@@ void prep_xaiger(RTLIL::Module *module
        for (auto cell : module->cells()) {
                if (cell->type == "$__ABC9_FF_")
                        continue;
+               if (cell->has_keep_attr())
+                       continue;
  
                auto inst_module = module->design->module(cell->type);
 -              bool abc9_box = inst_module && inst_module->attributes.count("\\abc9_box_id");
 -              bool abc9_flop = false;
 -              if (abc9_box) {
 -                      abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
 -                      if (abc9_flop && !dff)
 -                              continue;
 +              bool abc9_flop = inst_module && inst_module->get_bool_attribute("\\abc9_flop");
 +              if (abc9_flop && !dff)
 +                      continue;
  
 +              if ((inst_module && inst_module->attributes.count("\\abc9_box_id")) || abc9_flop) {
                        auto r = box_ports.insert(cell->type);
                        if (r.second) {
                                // Make carry in the last PI, and carry out the last PO
@@@ -589,6 -356,47 +599,39 @@@ void reintegrate(RTLIL::Module *module
        for (auto w : mapped_mod->wires())
                module->addWire(remap_name(w->name), GetSize(w));
  
 -              if (r.second) {
 -                      // Make carry in the last PI, and carry out the last PO
 -                      //   since ABC requires it this way
 -                      IdString carry_in, carry_out;
 -                      for (const auto &port_name : m->ports) {
 -                              auto w = m->wire(port_name);
 -                              log_assert(w);
 -                              if (w->get_bool_attribute("\\abc9_carry")) {
 -                                      if (w->port_input) {
 -                                              if (carry_in != IdString())
 -                                                      log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
 -                                              carry_in = port_name;
 -                                      }
 -                                      if (w->port_output) {
 -                                              if (carry_out != IdString())
 -                                                      log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(m));
 -                                              carry_out = port_name;
 -                                      }
 -                              }
 -                              else
 -                                      r.first->second.push_back(port_name);
 -                      }
+       dict<IdString,std::vector<IdString>> box_ports;
+ 
+       for (auto m : design->modules()) {
+               if (!m->attributes.count(ID(abc9_box_id)))
+                       continue;
+ 
+               auto r = box_ports.insert(m->name);
 -                      if (carry_in != IdString() && carry_out == IdString())
 -                              log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
 -                      if (carry_in == IdString() && carry_out != IdString())
 -                              log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
 -                      if (carry_in != IdString()) {
 -                              r.first->second.push_back(carry_in);
 -                              r.first->second.push_back(carry_out);
++              if (!r.second)
++                      continue;
+ 
++              // Make carry in the last PI, and carry out the last PO
++              //   since ABC requires it this way
++              IdString carry_in, carry_out;
++              for (const auto &port_name : m->ports) {
++                      auto w = m->wire(port_name);
++                      log_assert(w);
++                      if (w->get_bool_attribute("\\abc9_carry")) {
++                              log_assert(w->port_input != w->port_output);
++                              if (w->port_input)
++                                      carry_in = port_name;
++                              else if (w->port_output)
++                                      carry_out = port_name;
+                       }
++                      else
++                              r.first->second.push_back(port_name);
++              }
++
++              if (carry_in != IdString()) {
++                      r.first->second.push_back(carry_in);
++                      r.first->second.push_back(carry_out);
+               }
+       }
+ 
        std::vector<Cell*> boxes;
        for (auto cell : module->cells().to_vector()) {
                if (cell->has_keep_attr())
@@@ -688,28 -506,14 +731,29 @@@
                }
                else {
                        RTLIL::Cell *existing_cell = module->cell(mapped_cell->name);
 -                      log_assert(existing_cell);
 +                      if (!existing_cell)
 +                              log_error("Cannot find existing box cell with name '%s' in original design.\n", log_id(mapped_cell));
- #ifndef NDEBUG
-                       RTLIL::Module* box_module = design->module(existing_cell->type);
-                       IdString derived_type = box_module->derive(design, existing_cell->parameters);
-                       RTLIL::Module* derived_module = design->module(derived_type);
-                       log_assert(derived_module);
-                       log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
- #endif
-                       mapped_cell->type = existing_cell->type;
 +
-                       if (mapped_cell->type == ID($__ABC9_DELAY)) {
++                      if (existing_cell->type == ID($__ABC9_DELAY)) {
 +                              SigBit I = mapped_cell->getPort(ID(i));
 +                              SigBit O = mapped_cell->getPort(ID(o));
 +                              if (I.wire)
 +                                      I.wire = module->wires_.at(remap_name(I.wire->name));
 +                              log_assert(O.wire);
 +                              O.wire = module->wires_.at(remap_name(O.wire->name));
 +                              module->connect(O, I);
 +                              continue;
 +                      }
  
 -                      auto it = box_module->attributes.find(ID(abc9_box_id));
 -                      log_assert(it != box_module->attributes.end());
 -                      log_assert(mapped_cell->type == stringf("$__boxid%d", it->second.as_int()));
++#ifndef NDEBUG
+                       RTLIL::Module* box_module = design->module(existing_cell->type);
++                      IdString derived_type = box_module->derive(design, existing_cell->parameters);
++                      RTLIL::Module* derived_module = design->module(derived_type);
++                      log_assert(derived_module);
++                      log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
++#endif
+                       mapped_cell->type = existing_cell->type;
+ 
                        RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
                        cell->parameters = existing_cell->parameters;
                        cell->attributes = existing_cell->attributes;

diff --cc techlibs/xilinx/abc9_model.v
Simple merge