MIPS: Take advantage of new PCState syntax.

diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 3f3bd370a5af56c55e545f8a185d36ab131d1e1b..8a8033a007cd1844eb20358b2581e99a323ac8fc 100644 (file)
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -133,33 +133,29 @@ decode OPCODE_HI default Unknown::unknown() {
                         0x1: jr_hb({{
                             Config1Reg config1 = Config1;
                             if (config1.ca == 0) {
-                                pc.nnpc(Rs);
+                                NNPC = Rs;
                             } else {
                                 panic("MIPS16e not supported\n");
                             }
-                            PCS = pc;
                         }}, IsReturn, ClearHazards);
                         default: jr({{
                             Config1Reg config1 = Config1;
                             if (config1.ca == 0) {
-                                pc.nnpc(Rs);
+                                NNPC = Rs;
                             } else {
                                 panic("MIPS16e not supported\n");
                             }
-                            PCS = pc;
                         }}, IsReturn);
                     }
 
                     0x1: decode HINT {
                         0x1: jalr_hb({{
-                            Rd = pc.nnpc();
-                            pc.nnpc(Rs);
-                            PCS = pc;
+                            Rd = NNPC;
+                            NNPC = Rs;
                         }}, IsCall, ClearHazards);
                         default: jalr({{
-                            Rd = pc.nnpc();
-                            pc.nnpc(Rs);
-                            PCS = pc;
+                            Rd = NNPC;
+                            NNPC = Rs;
                         }}, IsCall);
                     }
                 }
@@ -332,14 +328,9 @@ decode OPCODE_HI default Unknown::unknown() {
         }
 
         format Jump {
-            0x2: j({{
-                pc.nnpc((pc.npc() & 0xF0000000) | (JMPTARG << 2));
-                PCS = pc;
-            }});
-            0x3: jal({{
-                pc.nnpc((pc.npc() & 0xF0000000) | (JMPTARG << 2));
-                PCS = pc;
-            }}, IsCall, Link);
+            0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }});
+            0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},
+                     IsCall, Link);
         }
 
         format Branch {
@@ -708,16 +699,15 @@ decode OPCODE_HI default Unknown::unknown() {
                         ConfigReg config = Config;
                         SRSCtlReg srsCtl = SRSCtl;
                         DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC);
-                        MipsISA::PCState pc = PCS;
                         if (status.erl == 1) {
                             status.erl = 0;
-                            pc.npc(ErrorEPC);
+                            NPC = ErrorEPC;
                             // Need to adjust NNPC, otherwise things break
-                            pc.nnpc(ErrorEPC + sizeof(MachInst));
+                            NNPC = ErrorEPC + sizeof(MachInst);
                         } else {
-                            pc.npc(EPC);
+                            NPC = EPC;
                             // Need to adjust NNPC, otherwise things break
-                            pc.nnpc(EPC + sizeof(MachInst));
+                            NNPC = EPC + sizeof(MachInst);
                             status.exl = 0;
                             if (config.ar >=1 &&
                                     srsCtl.hss > 0 &&
@@ -726,7 +716,6 @@ decode OPCODE_HI default Unknown::unknown() {
                                 //xc->setShadowSet(srsCtl.pss);
                             }
                         }
-                        PCS = pc;
                         LLFlag = 0;
                         Status = status;
                         SRSCtl = srsCtl;
@@ -734,15 +723,14 @@ decode OPCODE_HI default Unknown::unknown() {
 
                     0x1F: deret({{
                         DebugReg debug = Debug;
-                        MipsISA::PCState pc = PCS;
                         if (debug.dm == 1) {
                             debug.dm = 1;
                             debug.iexi = 0;
-                            pc.npc(DEPC);
+                            NPC = DEPC;
                         } else {
+                            NPC = NPC;
                             // Undefined;
                         }
-                        PCS = pc;
                         Debug = debug;
                     }}, IsReturn, IsSerializing, IsERET);
                 }

diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index 232a743a718d55312dce345ce16848066eb5457b..ecc62d75dfccb004e5da90c40a48e8ffdb310028 100644 (file)
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -225,16 +225,16 @@ output decoder {{
 }};
 
 def format Branch(code, *opt_flags) {{
-    not_taken_code = ''
+    not_taken_code = 'NNPC = NNPC; NPC = NPC;'
 
     #Build Instruction Flags
     #Use Link & Likely Flags to Add Link/Condition Code
     inst_flags = ('IsDirectControl', )
     for x in opt_flags:
         if x == 'Link':
-            code += 'R31 = pc.nnpc();\n'
+            code += 'R31 = NNPC;\n'
         elif x == 'Likely':
-            not_taken_code = 'pc.advance();'
+            not_taken_code = 'NNPC = NPC; NPC = PC;'
             inst_flags += ('IsCondDelaySlot', )
         else:
             inst_flags += (x, )
@@ -248,14 +248,12 @@ def format Branch(code, *opt_flags) {{
     #Condition code
     code = '''
     bool cond;
-    MipsISA::PCState pc = PCS;
     %(code)s
     if (cond) {
-        pc.nnpc(pc.npc() + disp);
+        NNPC = NPC + disp;
     } else {
         %(not_taken_code)s
     }
-    PCS = pc;
     ''' % { "code" : code, "not_taken_code" : not_taken_code }
 
     iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
@@ -266,16 +264,16 @@ def format Branch(code, *opt_flags) {{
 }};
 
 def format DspBranch(code, *opt_flags) {{
-    not_taken_code = ''
+    not_taken_code = 'NNPC = NNPC; NPC = NPC;'
 
     #Build Instruction Flags
     #Use Link & Likely Flags to Add Link/Condition Code
     inst_flags = ('IsDirectControl', )
     for x in opt_flags:
         if x == 'Link':
-            code += 'R32 = pc.nnpc();'
+            code += 'R32 = NNPC;'
         elif x == 'Likely':
-            not_taken_code = 'pc.advance();'
+            not_taken_code = 'NNPC = NPC, NPC = PC;'
             inst_flags += ('IsCondDelaySlot', )
         else:
             inst_flags += (x, )
@@ -288,16 +286,14 @@ def format DspBranch(code, *opt_flags) {{
 
     #Condition code
     code = '''
-    MipsISA::PCState pc = PCS;
     bool cond;
     uint32_t dspctl = DSPControl;
     %(code)s
     if (cond) {
-        pc.nnpc(pc.npc() + disp);
+        NNPC = NPC + disp;
     } else {
         %(not_taken_code)s
     }
-    PCS = pc;
     ''' % { "code" : code, "not_taken_code" : not_taken_code }
 
     iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
@@ -314,17 +310,13 @@ def format Jump(code, *opt_flags) {{
     for x in opt_flags:
         if x == 'Link':
             code = '''
-            R31 = pc.nnpc();
+            R31 = NNPC;
             ''' + code
         elif x == 'ClearHazards':
             code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
         else:
             inst_flags += (x, )
 
-    code = '''
-    MipsISA::PCState pc = PCS;
-    ''' + code
-
     iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)

diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa
index 1bb5ae5b3a1c1927695ecda97f5b41f4f5a85361..792c7e2fae2a05629aaf638eb09eb20f7befea34 100644 (file)
--- a/src/arch/mips/isa/operands.isa
+++ b/src/arch/mips/isa/operands.isa
@@ -151,5 +151,7 @@ def operands {{
     'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
 
     #Program Counter Operands
-    'PCS': ('PCState', 'uw', None, (None, None, 'IsControl'), 4)
+    'PC': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 4),
+    'NPC': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 4),
+    'NNPC': ('PCState', 'uw', 'nnpc', (None, None, 'IsControl'), 4)
 }};